target/linux/mvebu/patches-3.10/0088-ARM-mvebu-re-enable-PCIe-on-Armada-370-DB.patch

   1 From 98e6b600e81f71f8621e316f5d46cf261a9f1da4 Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Mon, 25 Nov 2013 17:26:47 +0100
   4 Subject: [PATCH 088/203] ARM: mvebu: re-enable PCIe on Armada 370 DB
   5
   6 Commit 14fd8ed0a7fd19913 ("ARM: mvebu: Relocate Armada 370/XP PCIe
   7 device tree nodes") relocated the PCIe controller DT nodes one level
   8 up in the Device Tree, to reflect a more correct representation of the
   9 hardware introduced by the mvebu-mbus Device Tree binding.
  10
  11 However, while most of the boards were properly adjusted accordingly,
  12 the Armada 370 DB board was left unchanged, and therefore, PCIe is
  13 seen as not enabled on this board. This patch fixes that by moving the
  14 PCIe controller node one level-up in armada-370-db.dts.
  15
  16 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  17 Cc: stable@vger.kernel.org
  18 ---
  19  arch/arm/boot/dts/armada-370-db.dts | 28 ++++++++++++++--------------
  20  1 file changed, 14 insertions(+), 14 deletions(-)
  21
  22 --- a/arch/arm/boot/dts/armada-370-db.dts
  23 +++ b/arch/arm/boot/dts/armada-370-db.dts
  24 @@ -99,22 +99,22 @@
  25                                         spi-max-frequency = <50000000>;
  26                                 };
  27                         };
  28 +               };
  29
  30 -                       pcie-controller {
  31 +               pcie-controller {
  32 +                       status = "okay";
  33 +                       /*
  34 +                        * The two PCIe units are accessible through
  35 +                        * both standard PCIe slots and mini-PCIe
  36 +                        * slots on the board.
  37 +                        */
  38 +                       pcie@1,0 {
  39 +                               /* Port 0, Lane 0 */
  40 +                               status = "okay";
  41 +                       };
  42 +                       pcie@2,0 {
  43 +                               /* Port 1, Lane 0 */
  44                                 status = "okay";
  45 -                               /*
  46 -                                * The two PCIe units are accessible through
  47 -                                * both standard PCIe slots and mini-PCIe
  48 -                                * slots on the board.
  49 -                                */
  50 -                               pcie@1,0 {
  51 -                                       /* Port 0, Lane 0 */
  52 -                                       status = "okay";
  53 -                               };
  54 -                               pcie@2,0 {
  55 -                                       /* Port 1, Lane 0 */
  56 -                                       status = "okay";
  57 -                               };
  58                         };
  59                 };
  60         };