target/linux/mvebu/patches-3.10/0090-mtd-add-datasheet-s-ECC-information-to-nand_chip.patch

   1 From 4aa571afd29f88898ef2fb954effcf53fec3264e Mon Sep 17 00:00:00 2001
   2 From: Huang Shijie <b32955@freescale.com>
   3 Date: Fri, 17 May 2013 11:17:25 +0800
   4 Subject: [PATCH 090/203] mtd: add datasheet's ECC information to nand_chip{}
   5
   6 1.) Why add the ECC information to the nand_chip{} ?
   7    Each nand chip has its requirement for the ECC correctability, such as
   8    "4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte".
   9    This ECC info is very important to the nand controller, such as gpmi.
  10
  11    Take the Micron MT29F64G08CBABA for example, its geometry is
  12    8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB.
  13    If we do not provide the ECC info to the gpmi nand driver, it has to
  14    calculate the ECC correctability itself. The gpmi driver will gets the 56bit
  15    ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility.
  16    The gpmi will quits in this case. But in actually, the gpmi can supports
  17    this nand chip if it can get the right ECC info.
  18
  19 2.) about the new fields.
  20    The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds.
  21    The two fields should be set from the nand chip's datasheets.
  22
  23    For example:
  24         "4bit ECC for each 512Byte" could be:
  25                 @ecc_strength_ds = 4, @ecc_step_ds = 512.
  26         "40bit ECC for each 1024Byte" could be:
  27                 @ecc_strength_ds = 40, @ecc_step_ds = 1024.
  28
  29 3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}?
  30    The @strength and @size in nand_ecc_ctrl{} is used by the nand controller
  31    driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet.
  32
  33 Signed-off-by: Huang Shijie <b32955@freescale.com>
  34 Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
  35 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  36 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  37 ---
  38  include/linux/mtd/nand.h | 8 ++++++++
  39  1 file changed, 8 insertions(+)
  40
  41 --- a/include/linux/mtd/nand.h
  42 +++ b/include/linux/mtd/nand.h
  43 @@ -434,6 +434,12 @@ struct nand_buffers {
  44   *                     bad block marker position; i.e., BBM == 11110111b is
  45   *                     not bad when badblockbits == 7
  46   * @cellinfo:          [INTERN] MLC/multichip data from chip ident
  47 + * @ecc_strength_ds:   [INTERN] ECC correctability from the datasheet.
  48 + *                     Minimum amount of bit errors per @ecc_step_ds guaranteed
  49 + *                     to be correctable. If unknown, set to zero.
  50 + * @ecc_step_ds:       [INTERN] ECC step required by the @ecc_strength_ds,
  51 + *                      also from the datasheet. It is the recommended ECC step
  52 + *                     size, if known; if unknown, set to zero.
  53   * @numchips:          [INTERN] number of physical chips
  54   * @chipsize:          [INTERN] the size of one chip for multichip arrays
  55   * @pagemask:          [INTERN] page number mask = number of (pages / chip) - 1
  56 @@ -510,6 +516,8 @@ struct nand_chip {
  57         unsigned int pagebuf_bitflips;
  58         int subpagesize;
  59         uint8_t cellinfo;
  60 +       uint16_t ecc_strength_ds;
  61 +       uint16_t ecc_step_ds;
  62         int badblockpos;
  63         int badblockbits;
  64