target/linux/mvebu/patches-3.10/0117-mtd-nand-pxa3xx-Support-command-buffer-3.patch

   1 From 6bbda039fe5e9d1b3c04f4f0dd8479a2c102d28e Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Mon, 12 Aug 2013 14:14:50 -0300
   4 Subject: [PATCH 117/203] mtd: nand: pxa3xx: Support command buffer #3
   5
   6 Some newer controllers support a fourth command buffer. This additional
   7 command buffer allows to set an arbitrary length count, using the
   8 NDCB3.NDLENCNT field, to perform non-standard length operations
   9 such as the ONFI parameter page read.
  10
  11 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  12 Tested-by: Daniel Mack <zonque@gmail.com>
  13 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  14 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  15 ---
  16  drivers/mtd/nand/pxa3xx_nand.c | 15 +++++++++++++++
  17  1 file changed, 15 insertions(+)
  18
  19 --- a/drivers/mtd/nand/pxa3xx_nand.c
  20 +++ b/drivers/mtd/nand/pxa3xx_nand.c
  21 @@ -197,6 +197,7 @@ struct pxa3xx_nand_info {
  22         uint32_t                ndcb0;
  23         uint32_t                ndcb1;
  24         uint32_t                ndcb2;
  25 +       uint32_t                ndcb3;
  26  };
  27
  28  static bool use_dma = 1;
  29 @@ -493,9 +494,22 @@ static irqreturn_t pxa3xx_nand_irq(int i
  30                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
  31                 status &= ~NDSR_WRCMDREQ;
  32                 info->state = STATE_CMD_HANDLE;
  33 +
  34 +               /*
  35 +                * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  36 +                * must be loaded by writing directly either 12 or 16
  37 +                * bytes directly to NDCB0, four bytes at a time.
  38 +                *
  39 +                * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  40 +                * but each NDCBx register can be read.
  41 +                */
  42                 nand_writel(info, NDCB0, info->ndcb0);
  43                 nand_writel(info, NDCB0, info->ndcb1);
  44                 nand_writel(info, NDCB0, info->ndcb2);
  45 +
  46 +               /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  47 +               if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  48 +                       nand_writel(info, NDCB0, info->ndcb3);
  49         }
  50
  51         /* clear NDSR to let the controller exit the IRQ */
  52 @@ -554,6 +568,7 @@ static int prepare_command_pool(struct p
  53         default:
  54                 info->ndcb1 = 0;
  55                 info->ndcb2 = 0;
  56 +               info->ndcb3 = 0;
  57                 break;
  58         }
  59