target/linux/mvebu/patches-3.10/0167-clocksource-armada-370-xp-Simplify-TIMER_CTRL-regist.patch

   1 From 7a5e03909417ccecc85819837d10cbb6ffe1d759 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Tue, 13 Aug 2013 11:43:11 -0300
   4 Subject: [PATCH 167/203] clocksource: armada-370-xp: Simplify TIMER_CTRL
   5  register access
   6
   7 This commit creates two functions to access the TIMER_CTRL register:
   8 one for global one for the per-cpu. This makes the code much more
   9 readable. In addition, since the TIMER_CTRL register is also used for
  10 watchdog, this is preparation work for future thread-safe improvements.
  11
  12 Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  13 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  14 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  15 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  16 ---
  17  drivers/clocksource/time-armada-370-xp.c | 69 ++++++++++++++------------------
  18  1 file changed, 30 insertions(+), 39 deletions(-)
  19
  20 --- a/drivers/clocksource/time-armada-370-xp.c
  21 +++ b/drivers/clocksource/time-armada-370-xp.c
  22 @@ -71,6 +71,18 @@ static u32 ticks_per_jiffy;
  23
  24  static struct clock_event_device __percpu **percpu_armada_370_xp_evt;
  25
  26 +static void timer_ctrl_clrset(u32 clr, u32 set)
  27 +{
  28 +       writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
  29 +               timer_base + TIMER_CTRL_OFF);
  30 +}
  31 +
  32 +static void local_timer_ctrl_clrset(u32 clr, u32 set)
  33 +{
  34 +       writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
  35 +               local_base + TIMER_CTRL_OFF);
  36 +}
  37 +
  38  static u32 notrace armada_370_xp_read_sched_clock(void)
  39  {
  40         return ~readl(timer_base + TIMER0_VAL_OFF);
  41 @@ -83,7 +95,6 @@ static int
  42  armada_370_xp_clkevt_next_event(unsigned long delta,
  43                                 struct clock_event_device *dev)
  44  {
  45 -       u32 u;
  46         /*
  47          * Clear clockevent timer interrupt.
  48          */
  49 @@ -97,11 +108,8 @@ armada_370_xp_clkevt_next_event(unsigned
  50         /*
  51          * Enable the timer.
  52          */
  53 -       u = readl(local_base + TIMER_CTRL_OFF);
  54 -       u = ((u & ~TIMER0_RELOAD_EN) | TIMER0_EN |
  55 -            TIMER0_DIV(TIMER_DIVIDER_SHIFT));
  56 -       writel(u, local_base + TIMER_CTRL_OFF);
  57 -
  58 +       local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
  59 +                               TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
  60         return 0;
  61  }
  62
  63 @@ -109,8 +117,6 @@ static void
  64  armada_370_xp_clkevt_mode(enum clock_event_mode mode,
  65                           struct clock_event_device *dev)
  66  {
  67 -       u32 u;
  68 -
  69         if (mode == CLOCK_EVT_MODE_PERIODIC) {
  70
  71                 /*
  72 @@ -122,18 +128,14 @@ armada_370_xp_clkevt_mode(enum clock_eve
  73                 /*
  74                  * Enable timer.
  75                  */
  76 -
  77 -               u = readl(local_base + TIMER_CTRL_OFF);
  78 -
  79 -               writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
  80 -                       TIMER0_DIV(TIMER_DIVIDER_SHIFT)),
  81 -                       local_base + TIMER_CTRL_OFF);
  82 +               local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
  83 +                                          TIMER0_EN |
  84 +                                          TIMER0_DIV(TIMER_DIVIDER_SHIFT));
  85         } else {
  86                 /*
  87                  * Disable timer.
  88                  */
  89 -               u = readl(local_base + TIMER_CTRL_OFF);
  90 -               writel(u & ~TIMER0_EN, local_base + TIMER_CTRL_OFF);
  91 +               local_timer_ctrl_clrset(TIMER0_EN, 0);
  92
  93                 /*
  94                  * ACK pending timer interrupt.
  95 @@ -169,18 +171,18 @@ static irqreturn_t armada_370_xp_timer_i
  96   */
  97  static int __cpuinit armada_370_xp_timer_setup(struct clock_event_device *evt)
  98  {
  99 -       u32 u;
 100 +       u32 clr = 0, set = 0;
 101         int cpu = smp_processor_id();
 102
 103         /* Use existing clock_event for cpu 0 */
 104         if (!smp_processor_id())
 105                 return 0;
 106
 107 -       u = readl(local_base + TIMER_CTRL_OFF);
 108         if (timer25Mhz)
 109 -               writel(u | TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
 110 +               set = TIMER0_25MHZ;
 111         else
 112 -               writel(u & ~TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
 113 +               clr = TIMER0_25MHZ;
 114 +       local_timer_ctrl_clrset(clr, set);
 115
 116         evt->name               = armada_370_xp_clkevt.name;
 117         evt->irq                = armada_370_xp_clkevt.irq;
 118 @@ -212,7 +214,7 @@ static struct local_timer_ops armada_370
 119
 120  static void __init armada_370_xp_timer_init(struct device_node *np)
 121  {
 122 -       u32 u;
 123 +       u32 clr = 0, set = 0;
 124         int res;
 125
 126         timer_base = of_iomap(np, 0);
 127 @@ -221,29 +223,20 @@ static void __init armada_370_xp_timer_i
 128
 129         if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
 130                 /* The fixed 25MHz timer is available so let's use it */
 131 -               u = readl(local_base + TIMER_CTRL_OFF);
 132 -               writel(u | TIMER0_25MHZ,
 133 -                      local_base + TIMER_CTRL_OFF);
 134 -               u = readl(timer_base + TIMER_CTRL_OFF);
 135 -               writel(u | TIMER0_25MHZ,
 136 -                      timer_base + TIMER_CTRL_OFF);
 137 +               set = TIMER0_25MHZ;
 138                 timer_clk = 25000000;
 139         } else {
 140                 unsigned long rate = 0;
 141                 struct clk *clk = of_clk_get(np, 0);
 142                 WARN_ON(IS_ERR(clk));
 143                 rate =  clk_get_rate(clk);
 144 -               u = readl(local_base + TIMER_CTRL_OFF);
 145 -               writel(u & ~(TIMER0_25MHZ),
 146 -                      local_base + TIMER_CTRL_OFF);
 147 -
 148 -               u = readl(timer_base + TIMER_CTRL_OFF);
 149 -               writel(u & ~(TIMER0_25MHZ),
 150 -                      timer_base + TIMER_CTRL_OFF);
 151 -
 152                 timer_clk = rate / TIMER_DIVIDER;
 153 +
 154 +               clr = TIMER0_25MHZ;
 155                 timer25Mhz = false;
 156         }
 157 +       timer_ctrl_clrset(clr, set);
 158 +       local_timer_ctrl_clrset(clr, set);
 159
 160         /*
 161          * We use timer 0 as clocksource, and private(local) timer 0
 162 @@ -265,10 +258,8 @@ static void __init armada_370_xp_timer_i
 163         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 164         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 165
 166 -       u = readl(timer_base + TIMER_CTRL_OFF);
 167 -
 168 -       writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
 169 -               TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
 170 +       timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
 171 +                            TIMER0_DIV(TIMER_DIVIDER_SHIFT));
 172
 173         clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
 174                               "armada_370_xp_clocksource",