target/linux/mvebu/patches-3.10/0202-ARM-mvebu-second-PCIe-unit-of-Armada-XP-mv78230-is-o.patch

   1 From b2ea44bd7bca49fe5696857327a1d1514edd1196 Mon Sep 17 00:00:00 2001
   2 From: Arnaud Ebalard <arno@natisbad.org>
   3 Date: Tue, 5 Nov 2013 21:45:48 +0100
   4 Subject: [PATCH 202/203] ARM: mvebu: second PCIe unit of Armada XP mv78230 is
   5  only x1 capable
   6
   7 Various Marvell datasheets advertise second PCIe unit of mv78230
   8 flavour of Armada XP as x4/quad x1 capable. This second unit is in
   9 fact only x1 capable. This patch fixes current mv78230 .dtsi to
  10 reflect that, i.e. makes 1.0 the second interface (instead of 2.0
  11 at the moment). This was successfully tested on a mv78230-based
  12 ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller)
  13 connected to this second interface.
  14
  15 Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
  16 Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  17 Cc: <stable@vger.kernel.org> # v3.10.x
  18 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  19 ---
  20  arch/arm/boot/dts/armada-xp-mv78230.dtsi | 24 ++++++++++++------------
  21  1 file changed, 12 insertions(+), 12 deletions(-)
  22
  23 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
  24 +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
  25 @@ -47,7 +47,7 @@
  26                 /*
  27                  * MV78230 has 2 PCIe units Gen2.0: One unit can be
  28                  * configured as x4 or quad x1 lanes. One unit is
  29 -                * x4/x1.
  30 +                * x1 only.
  31                  */
  32                 pcie-controller {
  33                         compatible = "marvell,armada-xp-pcie";
  34 @@ -62,10 +62,10 @@
  35
  36                         ranges =
  37                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  38 -                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  39                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
  40                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
  41                                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
  42 +                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
  43                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  44                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
  45                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
  46 @@ -74,8 +74,8 @@
  47                                 0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
  48                                 0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
  49                                 0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
  50 -                               0x82000000 0x9 0       MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
  51 -                               0x81000000 0x9 0       MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
  52 +                               0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
  53 +                               0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;
  54
  55                         pcie@1,0 {
  56                                 device_type = "pci";
  57 @@ -145,20 +145,20 @@
  58                                 status = "disabled";
  59                         };
  60
  61 -                       pcie@9,0 {
  62 +                       pcie@5,0 {
  63                                 device_type = "pci";
  64 -                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
  65 -                               reg = <0x4800 0 0 0 0>;
  66 +                               assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  67 +                               reg = <0x2800 0 0 0 0>;
  68                                 #address-cells = <3>;
  69                                 #size-cells = <2>;
  70                                 #interrupt-cells = <1>;
  71 -                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
  72 -                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
  73 +                               ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
  74 +                                         0x81000000 0 0 0x81000000 0x5 0 1 0>;
  75                                 interrupt-map-mask = <0 0 0 0>;
  76 -                               interrupt-map = <0 0 0 0 &mpic 99>;
  77 -                               marvell,pcie-port = <2>;
  78 +                               interrupt-map = <0 0 0 0 &mpic 62>;
  79 +                               marvell,pcie-port = <1>;
  80                                 marvell,pcie-lane = <0>;
  81 -                               clocks = <&gateclk 26>;
  82 +                               clocks = <&gateclk 9>;
  83                                 status = "disabled";
  84                         };
  85                 };