ramips: update device tree source files
[openwrt/staging/wigyori.git] / target / linux / ramips / dts / WL-351.dts
1 /dts-v1/;
2
3 #include "rt3050.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "sitecom,wl-351", "ralink,rt3052-soc";
10 model = "Sitecom WL-351 v1 002";
11
12 cfi@1f000000 {
13 compatible = "cfi-flash";
14 reg = <0x1f000000 0x800000>;
15 bank-width = <2>;
16 device-width = <2>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 partition@0 {
21 label = "u-boot";
22 reg = <0x0 0x30000>;
23 read-only;
24 };
25
26 partition@30000 {
27 label = "u-boot-env";
28 reg = <0x30000 0x10000>;
29 read-only;
30 };
31
32 factory: partition@40000 {
33 label = "factory";
34 reg = <0x40000 0x10000>;
35 read-only;
36 };
37
38 partition@50000 {
39 label = "firmware";
40 reg = <0x50000 0x3b0000>;
41 };
42 };
43
44 gpio-leds {
45 compatible = "gpio-leds";
46
47 power {
48 label = "wl-351:amber:power";
49 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
50 };
51
52 unpopulated {
53 label = "wl-351:amber:unpopulated";
54 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
55 };
56
57 unpopulated2 {
58 label = "wl-351:blue:unpopulated";
59 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
60 };
61 };
62
63 gpio-keys-polled {
64 compatible = "gpio-keys-polled";
65 #address-cells = <1>;
66 #size-cells = <0>;
67 poll-interval = <20>;
68
69 reset {
70 label = "reset";
71 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
72 linux,code = <KEY_RESTART>;
73 };
74
75 wps {
76 label = "wps";
77 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
78 linux,code = <KEY_WPS_BUTTON>;
79 };
80 };
81
82 rtl8366rb {
83 compatible = "realtek,rtl8366rb";
84 gpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;
85 gpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;
86 };
87 };
88
89 &pinctrl {
90 state_default: pinctrl0 {
91 gpio {
92 ralink,group = "spi", "i2c", "jtag", "mdio", "uartf";
93 ralink,function = "gpio";
94 };
95 rgmii {
96 ralink,group = "rgmii";
97 ralink,function = "rgmii";
98 };
99 };
100 };
101
102 &ethernet {
103 mtd-mac-address = <&factory 0x4>;
104 };
105
106 &esw {
107 ralink,rgmii = <1>;
108 mediatek,portmap = <0x3f>;
109 ralink,fct2 = <0x0002500c>;
110 /*
111 * ext phy base addr 31, rx/tx clock skew 0,
112 * turbo mii off, rgmi 3.3v off, port 5 polling off
113 * port5: enabled, gige, full-duplex, rx/tx-flow-control
114 * port6: enabled, gige, full-duplex, rx/tx-flow-control
115 */
116 ralink,fpa2 = <0x1f003fff>;
117 };
118
119 &wmac {
120 ralink,mtd-eeprom = <&factory 0>;
121 };
122
123 &otg {
124 status = "okay";
125 };