target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3 #include <dt-bindings/gpio/gpio.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "mediatek,mt7621-soc";
   9
  10         cpus {
  11                 #address-cells = <1>;
  12                 #size-cells = <0>;
  13
  14                 cpu@0 {
  15                         device_type = "cpu";
  16                         compatible = "mips,mips1004Kc";
  17                         reg = <0>;
  18                 };
  19
  20                 cpu@1 {
  21                         device_type = "cpu";
  22                         compatible = "mips,mips1004Kc";
  23                         reg = <1>;
  24                 };
  25         };
  26
  27         cpuintc: cpuintc {
  28                 #address-cells = <0>;
  29                 #interrupt-cells = <1>;
  30                 interrupt-controller;
  31                 compatible = "mti,cpu-interrupt-controller";
  32         };
  33
  34         aliases {
  35                 serial0 = &uartlite;
  36         };
  37
  38         chosen {
  39                 bootargs = "console=ttyS0,57600";
  40         };
  41
  42         pll: pll {
  43                 compatible = "mediatek,mt7621-pll", "syscon";
  44
  45                 #clock-cells = <1>;
  46                 clock-output-names = "cpu", "bus";
  47         };
  48
  49         sysclock: sysclock {
  50                 #clock-cells = <0>;
  51                 compatible = "fixed-clock";
  52
  53                 /* FIXME: there should be way to detect this */
  54                 clock-frequency = <50000000>;
  55         };
  56
  57         palmbus: palmbus@1E000000 {
  58                 compatible = "palmbus";
  59                 reg = <0x1E000000 0x100000>;
  60                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  61
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64
  65                 sysc: sysc@0 {
  66                         compatible = "mtk,mt7621-sysc";
  67                         reg = <0x0 0x100>;
  68                 };
  69
  70                 wdt: wdt@100 {
  71                         compatible = "mediatek,mt7621-wdt";
  72                         reg = <0x100 0x100>;
  73                 };
  74
  75                 gpio: gpio@600 {
  76                         #gpio-cells = <2>;
  77                         #interrupt-cells = <2>;
  78                         compatible = "mediatek,mt7621-gpio";
  79                         gpio-controller;
  80                         interrupt-controller;
  81                         reg = <0x600 0x100>;
  82                         interrupt-parent = <&gic>;
  83                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  84                 };
  85
  86                 i2c: i2c@900 {
  87                         compatible = "mediatek,mt7621-i2c";
  88                         reg = <0x900 0x100>;
  89
  90                         clocks = <&sysclock>;
  91
  92                         resets = <&rstctrl 16>;
  93                         reset-names = "i2c";
  94
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97
  98                         status = "disabled";
  99
 100                         pinctrl-names = "default";
 101                         pinctrl-0 = <&i2c_pins>;
 102                 };
 103
 104                 i2s: i2s@a00 {
 105                         compatible = "mediatek,mt7621-i2s";
 106                         reg = <0xa00 0x100>;
 107
 108                         clocks = <&sysclock>;
 109
 110                         resets = <&rstctrl 17>;
 111                         reset-names = "i2s";
 112
 113                         interrupt-parent = <&gic>;
 114                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 115
 116                         txdma-req = <2>;
 117                         rxdma-req = <3>;
 118
 119                         dmas = <&gdma 4>,
 120                                 <&gdma 6>;
 121                         dma-names = "tx", "rx";
 122
 123                         status = "disabled";
 124                 };
 125
 126                 systick: systick@500 {
 127                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 128                         reg = <0x500 0x10>;
 129
 130                         resets = <&rstctrl 28>;
 131                         reset-names = "intc";
 132
 133                         interrupt-parent = <&gic>;
 134                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 135                 };
 136
 137                 memc: memc@5000 {
 138                         compatible = "mtk,mt7621-memc";
 139                         reg = <0x5000 0x1000>;
 140                 };
 141
 142                 cpc: cpc@1fbf0000 {
 143                         compatible = "mtk,mt7621-cpc";
 144                         reg = <0x1fbf0000 0x8000>;
 145                 };
 146
 147                 mc: mc@1fbf8000 {
 148                         compatible = "mtk,mt7621-mc";
 149                         reg = <0x1fbf8000 0x8000>;
 150                 };
 151
 152                 uartlite: uartlite@c00 {
 153                         compatible = "ns16550a";
 154                         reg = <0xc00 0x100>;
 155
 156                         clock-frequency = <50000000>;
 157
 158                         interrupt-parent = <&gic>;
 159                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 160
 161                         reg-shift = <2>;
 162                         reg-io-width = <4>;
 163                         no-loopback-test;
 164                 };
 165
 166                 uartlite2: uartlite2@d00 {
 167                         compatible = "ns16550a";
 168                         reg = <0xd00 0x100>;
 169
 170                         clock-frequency = <50000000>;
 171
 172                         interrupt-parent = <&gic>;
 173                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 174
 175                         reg-shift = <2>;
 176                         reg-io-width = <4>;
 177
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&uart2_pins>;
 180
 181                         status = "disabled";
 182                 };
 183
 184                 uartlite3: uartlite3@e00 {
 185                         compatible = "ns16550a";
 186                         reg = <0xe00 0x100>;
 187
 188                         clock-frequency = <50000000>;
 189
 190                         interrupt-parent = <&gic>;
 191                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 192
 193                         reg-shift = <2>;
 194                         reg-io-width = <4>;
 195
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&uart3_pins>;
 198
 199                         status = "disabled";
 200                 };
 201
 202                 spi0: spi@b00 {
 203                         status = "disabled";
 204
 205                         compatible = "ralink,mt7621-spi";
 206                         reg = <0xb00 0x100>;
 207
 208                         clocks = <&pll MT7621_CLK_BUS>;
 209
 210                         resets = <&rstctrl 18>;
 211                         reset-names = "spi";
 212
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215
 216                         pinctrl-names = "default";
 217                         pinctrl-0 = <&spi_pins>;
 218                 };
 219
 220                 gdma: gdma@2800 {
 221                         compatible = "ralink,rt3883-gdma";
 222                         reg = <0x2800 0x800>;
 223
 224                         resets = <&rstctrl 14>;
 225                         reset-names = "dma";
 226
 227                         interrupt-parent = <&gic>;
 228                         interrupts = <0 13 4>;
 229
 230                         #dma-cells = <1>;
 231                         #dma-channels = <16>;
 232                         #dma-requests = <16>;
 233
 234                         status = "disabled";
 235                 };
 236
 237                 hsdma: hsdma@7000 {
 238                         compatible = "mediatek,mt7621-hsdma";
 239                         reg = <0x7000 0x1000>;
 240
 241                         resets = <&rstctrl 5>;
 242                         reset-names = "hsdma";
 243
 244                         interrupt-parent = <&gic>;
 245                         interrupts = <0 11 4>;
 246
 247                         #dma-cells = <1>;
 248                         #dma-channels = <1>;
 249                         #dma-requests = <1>;
 250
 251                         status = "disabled";
 252                 };
 253         };
 254
 255         pinctrl: pinctrl {
 256                 compatible = "ralink,rt2880-pinmux";
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&state_default>;
 259
 260                 state_default: pinctrl0 {
 261                 };
 262
 263                 i2c_pins: i2c_pins {
 264                         i2c_pins {
 265                                 groups = "i2c";
 266                                 function = "i2c";
 267                         };
 268                 };
 269
 270                 spi_pins: spi_pins {
 271                         spi_pins {
 272                                 groups = "spi";
 273                                 function = "spi";
 274                         };
 275                 };
 276
 277                 uart1_pins: uart1 {
 278                         uart1 {
 279                                 groups = "uart1";
 280                                 function = "uart1";
 281                         };
 282                 };
 283
 284                 uart2_pins: uart2 {
 285                         uart2 {
 286                                 groups = "uart2";
 287                                 function = "uart2";
 288                         };
 289                 };
 290
 291                 uart3_pins: uart3 {
 292                         uart3 {
 293                                 groups = "uart3";
 294                                 function = "uart3";
 295                         };
 296                 };
 297
 298                 rgmii1_pins: rgmii1 {
 299                         rgmii1 {
 300                                 groups = "rgmii1";
 301                                 function = "rgmii1";
 302                         };
 303                 };
 304
 305                 rgmii2_pins: rgmii2 {
 306                         rgmii2 {
 307                                 groups = "rgmii2";
 308                                 function = "rgmii2";
 309                         };
 310                 };
 311
 312                 mdio_pins: mdio {
 313                         mdio {
 314                                 groups = "mdio";
 315                                 function = "mdio";
 316                         };
 317                 };
 318
 319                 pcie_pins: pcie {
 320                         pcie {
 321                                 groups = "pcie";
 322                                 function = "gpio";
 323                         };
 324                 };
 325
 326                 nand_pins: nand {
 327                         spi-nand {
 328                                 groups = "spi";
 329                                 function = "nand1";
 330                         };
 331
 332                         sdhci-nand {
 333                                 groups = "sdhci";
 334                                 function = "nand2";
 335                         };
 336                 };
 337
 338                 sdhci_pins: sdhci {
 339                         sdhci {
 340                                 groups = "sdhci";
 341                                 function = "sdhci";
 342                         };
 343                 };
 344         };
 345
 346         rstctrl: rstctrl {
 347                 compatible = "ralink,rt2880-reset";
 348                 #reset-cells = <1>;
 349         };
 350
 351         clkctrl: clkctrl {
 352                 compatible = "ralink,rt2880-clock";
 353                 #clock-cells = <1>;
 354         };
 355
 356         sdhci: sdhci@1E130000 {
 357                 status = "disabled";
 358
 359                 compatible = "ralink,mt7620-sdhci";
 360                 reg = <0x1E130000 0x4000>;
 361
 362                 interrupt-parent = <&gic>;
 363                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 364
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&sdhci_pins>;
 367         };
 368
 369         xhci: xhci@1E1C0000 {
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 status = "okay";
 373
 374                 compatible = "mediatek,mt8173-xhci";
 375                 reg = <0x1e1c0000 0x1000
 376                        0x1e1d0700 0x0100>;
 377                 reg-names = "mac", "ippc";
 378
 379                 clocks = <&sysclock>;
 380                 clock-names = "sys_ck";
 381
 382                 interrupt-parent = <&gic>;
 383                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 384
 385                 /*
 386                  * Port 1 of both hubs is one usb slot and referenced here.
 387                  * The binding doesn't allow to address individual hubs.
 388                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 389                  */
 390                 xhci_ehci_port1: port@1 {
 391                         reg = <1>;
 392                         #trigger-source-cells = <0>;
 393                 };
 394
 395                 /*
 396                  * Only the second usb hub has a second port. That port serves
 397                  * ehci and ohci.
 398                  */
 399                 ehci_port2: port@2 {
 400                         reg = <2>;
 401                         #trigger-source-cells = <0>;
 402                 };
 403         };
 404
 405         gic: interrupt-controller@1fbc0000 {
 406                 compatible = "mti,gic";
 407                 reg = <0x1fbc0000 0x2000>;
 408
 409                 interrupt-controller;
 410                 #interrupt-cells = <3>;
 411
 412                 mti,reserved-cpu-vectors = <7>;
 413
 414                 timer {
 415                         compatible = "mti,gic-timer";
 416                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 417                         clocks = <&pll MT7621_CLK_CPU>;
 418                 };
 419         };
 420
 421         nficlock: nficlock {
 422                 #clock-cells = <0>;
 423                 compatible = "fixed-clock";
 424
 425                 clock-frequency = <125000000>;
 426         };
 427
 428         nand: nand@1e003000 {
 429                 status = "disabled";
 430
 431                 compatible = "mediatek,mt7621-nfc";
 432                 reg = <0x1e003000 0x800
 433                         0x1e003800 0x800>;
 434                 reg-names = "nfi", "ecc";
 435
 436                 clocks = <&nficlock>;
 437                 clock-names = "nfi_clk";
 438         };
 439
 440         ethsys: syscon@1e000000 {
 441                 compatible = "mediatek,mt7621-ethsys",
 442                              "syscon";
 443                 reg = <0x1e000000 0x1000>;
 444                 #clock-cells = <1>;
 445         };
 446
 447         ethernet: ethernet@1e100000 {
 448                 compatible = "mediatek,mt7621-eth";
 449                 reg = <0x1e100000 0x10000>;
 450
 451                 clocks = <&sysclock>;
 452                 clock-names = "ethif";
 453
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456
 457                 resets = <&rstctrl 6 &rstctrl 23>;
 458                 reset-names = "fe", "eth";
 459
 460                 interrupt-parent = <&gic>;
 461                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 462
 463                 mediatek,ethsys = <&ethsys>;
 464
 465                 gmac0: mac@0 {
 466                         compatible = "mediatek,eth-mac";
 467                         reg = <0>;
 468                         phy-mode = "rgmii";
 469
 470                         fixed-link {
 471                                 speed = <1000>;
 472                                 full-duplex;
 473                                 pause;
 474                         };
 475                 };
 476
 477                 gmac1: mac@1 {
 478                         compatible = "mediatek,eth-mac";
 479                         reg = <1>;
 480                         status = "disabled";
 481                         phy-mode = "rgmii-rxid";
 482                 };
 483
 484                 mdio: mdio-bus {
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487
 488                         switch0: switch@1f {
 489                                 compatible = "mediatek,mt7621";
 490                                 #address-cells = <1>;
 491                                 #size-cells = <0>;
 492                                 reg = <0x1f>;
 493                                 mediatek,mcm;
 494                                 resets = <&rstctrl 2>;
 495                                 reset-names = "mcm";
 496
 497                                 ports {
 498                                         #address-cells = <1>;
 499                                         #size-cells = <0>;
 500                                         reg = <0>;
 501
 502                                         port@0 {
 503                                                 status = "disabled";
 504                                                 reg = <0>;
 505                                                 label = "lan0";
 506                                         };
 507
 508                                         port@1 {
 509                                                 status = "disabled";
 510                                                 reg = <1>;
 511                                                 label = "lan1";
 512                                         };
 513
 514                                         port@2 {
 515                                                 status = "disabled";
 516                                                 reg = <2>;
 517                                                 label = "lan2";
 518                                         };
 519
 520                                         port@3 {
 521                                                 status = "disabled";
 522                                                 reg = <3>;
 523                                                 label = "lan3";
 524                                         };
 525
 526                                         port@4 {
 527                                                 status = "disabled";
 528                                                 reg = <4>;
 529                                                 label = "lan4";
 530                                         };
 531
 532                                         port@6 {
 533                                                 reg = <6>;
 534                                                 label = "cpu";
 535                                                 ethernet = <&gmac0>;
 536                                                 phy-mode = "rgmii";
 537
 538                                                 fixed-link {
 539                                                         speed = <1000>;
 540                                                         full-duplex;
 541                                                 };
 542                                         };
 543                                 };
 544                         };
 545                 };
 546         };
 547
 548         gsw: gsw@1e110000 {
 549                 compatible = "mediatek,mt7621-gsw";
 550                 reg = <0x1e110000 0x8000>;
 551                 interrupt-parent = <&gic>;
 552                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 553         };
 554
 555         pcie: pcie@1e140000 {
 556                 compatible = "mediatek,mt7621-pci";
 557                 reg = <0x1e140000 0x100     /* host-pci bridge registers */
 558                         0x1e142000 0x100    /* pcie port 0 RC control registers */
 559                         0x1e143000 0x100    /* pcie port 1 RC control registers */
 560                         0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 561                 #address-cells = <3>;
 562                 #size-cells = <2>;
 563
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&pcie_pins>;
 566
 567                 device_type = "pci";
 568
 569                 bus-range = <0 255>;
 570                 ranges = <
 571                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 572                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 573                 >;
 574
 575                 interrupt-parent = <&gic>;
 576                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 577                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 578                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 579
 580                 status = "disabled";
 581
 582                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 583                 reset-names = "pcie0", "pcie1", "pcie2";
 584                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 585                 clock-names = "pcie0", "pcie1", "pcie2";
 586                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 587                 phy-names = "pcie-phy0", "pcie-phy2";
 588
 589                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 590
 591                 pcie0: pcie@0,0 {
 592                         reg = <0x0000 0 0 0 0>;
 593                         #address-cells = <3>;
 594                         #size-cells = <2>;
 595                         ranges;
 596                         bus-range = <0x00 0xff>;
 597                 };
 598
 599                 pcie1: pcie@1,0 {
 600                         reg = <0x0800 0 0 0 0>;
 601                         #address-cells = <3>;
 602                         #size-cells = <2>;
 603                         ranges;
 604                         bus-range = <0x00 0xff>;
 605                 };
 606
 607                 pcie2: pcie@2,0 {
 608                         reg = <0x1000 0 0 0 0>;
 609                         #address-cells = <3>;
 610                         #size-cells = <2>;
 611                         ranges;
 612                         bus-range = <0x00 0xff>;
 613                 };
 614         };
 615
 616         pcie0_phy: pcie-phy@1e149000 {
 617                 compatible = "mediatek,mt7621-pci-phy";
 618                 reg = <0x1e149000 0x0700>;
 619                 #phy-cells = <1>;
 620         };
 621
 622         pcie2_phy: pcie-phy@1e14a000 {
 623                 compatible = "mediatek,mt7621-pci-phy";
 624                 reg = <0x1e14a000 0x0700>;
 625                 #phy-cells = <1>;
 626         };
 627 };