target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/mips-gic.h>
   4 #include <dt-bindings/clock/mt7621-clk.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "mediatek,mt7621-soc";
  11
  12         aliases {
  13                 serial0 = &uartlite;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "mips,mips1004Kc";
  23                         reg = <0>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "mips,mips1004Kc";
  29                         reg = <1>;
  30                 };
  31         };
  32
  33         cpuintc: cpuintc {
  34                 #address-cells = <0>;
  35                 #interrupt-cells = <1>;
  36                 interrupt-controller;
  37                 compatible = "mti,cpu-interrupt-controller";
  38         };
  39
  40         chosen {
  41                 bootargs = "console=ttyS0,57600";
  42         };
  43
  44         sysclock: sysclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <50000000>;
  50         };
  51
  52         palmbus: palmbus@1e000000 {
  53                 compatible = "palmbus";
  54                 reg = <0x1e000000 0x100000>;
  55                 ranges = <0x0 0x1e000000 0x0fffff>;
  56
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59
  60                 sysc: syscon@0 {
  61                         compatible = "mediatek,mt7621-sysc", "syscon";
  62                         #clock-cells = <1>;
  63                         ralink,memctl = <&memc>;
  64                         clock-output-names = "xtal", "cpu", "bus",
  65                                              "50m", "125m", "150m",
  66                                              "250m", "270m";
  67                         reg = <0x0 0x100>;
  68                 };
  69
  70                 wdt: wdt@100 {
  71                         compatible = "mediatek,mt7621-wdt";
  72                         reg = <0x100 0x100>;
  73                 };
  74
  75                 gpio: gpio@600 {
  76                         #gpio-cells = <2>;
  77                         #interrupt-cells = <2>;
  78                         compatible = "mediatek,mt7621-gpio";
  79                         gpio-controller;
  80                         gpio-ranges = <&pinctrl 0 0 95>;
  81                         interrupt-controller;
  82                         reg = <0x600 0x100>;
  83                         interrupt-parent = <&gic>;
  84                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  85                 };
  86
  87                 i2c: i2c@900 {
  88                         compatible = "mediatek,mt7621-i2c";
  89                         reg = <0x900 0x100>;
  90
  91                         clocks = <&sysclock>;
  92
  93                         resets = <&rstctrl 16>;
  94                         reset-names = "i2c";
  95
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98
  99                         status = "disabled";
 100
 101                         pinctrl-names = "default";
 102                         pinctrl-0 = <&i2c_pins>;
 103                 };
 104
 105                 i2s: i2s@a00 {
 106                         compatible = "mediatek,mt7621-i2s";
 107                         reg = <0xa00 0x100>;
 108
 109                         clocks = <&sysclock>;
 110
 111                         resets = <&rstctrl 17>;
 112                         reset-names = "i2s";
 113
 114                         interrupt-parent = <&gic>;
 115                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 116
 117                         txdma-req = <2>;
 118                         rxdma-req = <3>;
 119
 120                         dmas = <&gdma 4>,
 121                                 <&gdma 6>;
 122                         dma-names = "tx", "rx";
 123
 124                         status = "disabled";
 125                 };
 126
 127                 systick: systick@500 {
 128                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 129                         reg = <0x500 0x10>;
 130
 131                         resets = <&rstctrl 28>;
 132                         reset-names = "intc";
 133
 134                         interrupt-parent = <&gic>;
 135                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 136                 };
 137
 138                 memc: syscon@5000 {
 139                         compatible = "mediatek,mt7621-memc", "syscon";
 140                         reg = <0x5000 0x1000>;
 141                 };
 142
 143                 uartlite: uartlite@c00 {
 144                         compatible = "ns16550a";
 145                         reg = <0xc00 0x100>;
 146
 147                         clock-frequency = <50000000>;
 148
 149                         interrupt-parent = <&gic>;
 150                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 151
 152                         reg-shift = <2>;
 153                         reg-io-width = <4>;
 154                         no-loopback-test;
 155                 };
 156
 157                 uartlite2: uartlite2@d00 {
 158                         compatible = "ns16550a";
 159                         reg = <0xd00 0x100>;
 160
 161                         clock-frequency = <50000000>;
 162
 163                         interrupt-parent = <&gic>;
 164                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 165
 166                         reg-shift = <2>;
 167                         reg-io-width = <4>;
 168
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&uart2_pins>;
 171
 172                         status = "disabled";
 173                 };
 174
 175                 uartlite3: uartlite3@e00 {
 176                         compatible = "ns16550a";
 177                         reg = <0xe00 0x100>;
 178
 179                         clock-frequency = <50000000>;
 180
 181                         interrupt-parent = <&gic>;
 182                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 183
 184                         reg-shift = <2>;
 185                         reg-io-width = <4>;
 186
 187                         pinctrl-names = "default";
 188                         pinctrl-0 = <&uart3_pins>;
 189
 190                         status = "disabled";
 191                 };
 192
 193                 spi0: spi@b00 {
 194                         status = "disabled";
 195
 196                         compatible = "ralink,mt7621-spi";
 197                         reg = <0xb00 0x100>;
 198
 199                         clocks = <&sysc MT7621_CLK_BUS>;
 200
 201                         resets = <&rstctrl 18>;
 202                         reset-names = "spi";
 203
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&spi_pins>;
 209                 };
 210
 211                 gdma: gdma@2800 {
 212                         compatible = "ralink,rt3883-gdma";
 213                         reg = <0x2800 0x800>;
 214
 215                         resets = <&rstctrl 14>;
 216                         reset-names = "dma";
 217
 218                         interrupt-parent = <&gic>;
 219                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 220
 221                         #dma-cells = <1>;
 222                         #dma-channels = <16>;
 223                         #dma-requests = <16>;
 224
 225                         status = "disabled";
 226                 };
 227
 228                 hsdma: hsdma@7000 {
 229                         compatible = "mediatek,mt7621-hsdma";
 230                         reg = <0x7000 0x1000>;
 231
 232                         resets = <&rstctrl 5>;
 233                         reset-names = "hsdma";
 234
 235                         interrupt-parent = <&gic>;
 236                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 237
 238                         #dma-cells = <1>;
 239                         #dma-channels = <1>;
 240                         #dma-requests = <1>;
 241
 242                         status = "disabled";
 243                 };
 244         };
 245
 246         pinctrl: pinctrl {
 247                 compatible = "ralink,rt2880-pinmux";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&state_default>;
 250
 251                 state_default: pinctrl0 {
 252                 };
 253
 254                 i2c_pins: i2c_pins {
 255                         i2c_pins {
 256                                 groups = "i2c";
 257                                 function = "i2c";
 258                         };
 259                 };
 260
 261                 spi_pins: spi_pins {
 262                         spi_pins {
 263                                 groups = "spi";
 264                                 function = "spi";
 265                         };
 266                 };
 267
 268                 uart1_pins: uart1 {
 269                         uart1 {
 270                                 groups = "uart1";
 271                                 function = "uart1";
 272                         };
 273                 };
 274
 275                 uart2_pins: uart2 {
 276                         uart2 {
 277                                 groups = "uart2";
 278                                 function = "uart2";
 279                         };
 280                 };
 281
 282                 uart3_pins: uart3 {
 283                         uart3 {
 284                                 groups = "uart3";
 285                                 function = "uart3";
 286                         };
 287                 };
 288
 289                 rgmii1_pins: rgmii1 {
 290                         rgmii1 {
 291                                 groups = "rgmii1";
 292                                 function = "rgmii1";
 293                         };
 294                 };
 295
 296                 rgmii2_pins: rgmii2 {
 297                         rgmii2 {
 298                                 groups = "rgmii2";
 299                                 function = "rgmii2";
 300                         };
 301                 };
 302
 303                 mdio_pins: mdio {
 304                         mdio {
 305                                 groups = "mdio";
 306                                 function = "mdio";
 307                         };
 308                 };
 309
 310                 pcie_pins: pcie {
 311                         pcie {
 312                                 groups = "pcie";
 313                                 function = "gpio";
 314                         };
 315                 };
 316
 317                 nand_pins: nand {
 318                         spi-nand {
 319                                 groups = "spi";
 320                                 function = "nand1";
 321                         };
 322
 323                         sdhci-nand {
 324                                 groups = "sdhci";
 325                                 function = "nand2";
 326                         };
 327                 };
 328
 329                 sdhci_pins: sdhci {
 330                         sdhci {
 331                                 groups = "sdhci";
 332                                 function = "sdhci";
 333                         };
 334                 };
 335         };
 336
 337         rstctrl: rstctrl {
 338                 compatible = "ralink,rt2880-reset";
 339                 #reset-cells = <1>;
 340         };
 341
 342         clkctrl: clkctrl {
 343                 compatible = "ralink,rt2880-clock";
 344                 #clock-cells = <1>;
 345         };
 346
 347         sdhci: sdhci@1e130000 {
 348                 status = "disabled";
 349
 350                 compatible = "ralink,mt7620-sdhci";
 351                 reg = <0x1e130000 0x4000>;
 352
 353                 interrupt-parent = <&gic>;
 354                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 355
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&sdhci_pins>;
 358         };
 359
 360         xhci: xhci@1e1c0000 {
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363
 364                 compatible = "mediatek,mt8173-xhci";
 365                 reg = <0x1e1c0000 0x1000
 366                        0x1e1d0700 0x0100>;
 367                 reg-names = "mac", "ippc";
 368
 369                 clocks = <&sysclock>;
 370                 clock-names = "sys_ck";
 371
 372                 interrupt-parent = <&gic>;
 373                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 374
 375                 /*
 376                  * Port 1 of both hubs is one usb slot and referenced here.
 377                  * The binding doesn't allow to address individual hubs.
 378                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 379                  */
 380                 xhci_ehci_port1: port@1 {
 381                         reg = <1>;
 382                         #trigger-source-cells = <0>;
 383                 };
 384
 385                 /*
 386                  * Only the second usb hub has a second port. That port serves
 387                  * ehci and ohci.
 388                  */
 389                 ehci_port2: port@2 {
 390                         reg = <2>;
 391                         #trigger-source-cells = <0>;
 392                 };
 393         };
 394
 395         gic: interrupt-controller@1fbc0000 {
 396                 compatible = "mti,gic";
 397                 reg = <0x1fbc0000 0x2000>;
 398
 399                 interrupt-controller;
 400                 #interrupt-cells = <3>;
 401
 402                 mti,reserved-cpu-vectors = <7>;
 403
 404                 timer {
 405                         compatible = "mti,gic-timer";
 406                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 407                         clocks = <&sysc MT7621_CLK_CPU>;
 408                 };
 409         };
 410
 411         nficlock: nficlock {
 412                 #clock-cells = <0>;
 413                 compatible = "fixed-clock";
 414
 415                 clock-frequency = <125000000>;
 416         };
 417
 418         cpc: cpc@1fbf0000 {
 419                 compatible = "mti,mips-cpc";
 420                 reg = <0x1fbf0000 0x8000>;
 421         };
 422
 423         mc: mc@1fbf8000 {
 424                 compatible = "mti,mips-cdmm";
 425                 reg = <0x1fbf8000 0x8000>;
 426         };
 427
 428         nand: nand@1e003000 {
 429                 status = "disabled";
 430
 431                 compatible = "mediatek,mt7621-nfc";
 432                 reg = <0x1e003000 0x800
 433                         0x1e003800 0x800>;
 434                 reg-names = "nfi", "ecc";
 435
 436                 clocks = <&nficlock>;
 437                 clock-names = "nfi_clk";
 438         };
 439
 440         ethernet: ethernet@1e100000 {
 441                 compatible = "mediatek,mt7621-eth";
 442                 reg = <0x1e100000 0x10000>;
 443
 444                 clocks = <&sysc MT7621_CLK_FE>,
 445                          <&sysc MT7621_CLK_ETH>;
 446                 clock-names = "fe", "ethif";
 447
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450
 451                 resets = <&rstctrl 6>, <&rstctrl 23>;
 452                 reset-names = "fe", "eth";
 453
 454                 interrupt-parent = <&gic>;
 455                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 456
 457                 mediatek,ethsys = <&sysc>;
 458
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
 461
 462                 gmac0: mac@0 {
 463                         compatible = "mediatek,eth-mac";
 464                         reg = <0>;
 465                         phy-mode = "rgmii";
 466
 467                         fixed-link {
 468                                 speed = <1000>;
 469                                 full-duplex;
 470                                 pause;
 471                         };
 472                 };
 473
 474                 gmac1: mac@1 {
 475                         compatible = "mediatek,eth-mac";
 476                         reg = <1>;
 477                         status = "disabled";
 478                         phy-mode = "rgmii";
 479                 };
 480
 481                 mdio: mdio-bus {
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484
 485                         switch0: switch@1f {
 486                                 compatible = "mediatek,mt7621";
 487                                 reg = <0x1f>;
 488                                 mediatek,mcm;
 489                                 resets = <&rstctrl 2>;
 490                                 reset-names = "mcm";
 491                                 interrupt-controller;
 492                                 #interrupt-cells = <1>;
 493                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 494
 495                                 ports {
 496                                         #address-cells = <1>;
 497                                         #size-cells = <0>;
 498
 499                                         port@0 {
 500                                                 status = "disabled";
 501                                                 reg = <0>;
 502                                                 label = "lan0";
 503                                         };
 504
 505                                         port@1 {
 506                                                 status = "disabled";
 507                                                 reg = <1>;
 508                                                 label = "lan1";
 509                                         };
 510
 511                                         port@2 {
 512                                                 status = "disabled";
 513                                                 reg = <2>;
 514                                                 label = "lan2";
 515                                         };
 516
 517                                         port@3 {
 518                                                 status = "disabled";
 519                                                 reg = <3>;
 520                                                 label = "lan3";
 521                                         };
 522
 523                                         port@4 {
 524                                                 status = "disabled";
 525                                                 reg = <4>;
 526                                                 label = "lan4";
 527                                         };
 528
 529                                         port@6 {
 530                                                 reg = <6>;
 531                                                 ethernet = <&gmac0>;
 532                                                 phy-mode = "rgmii";
 533
 534                                                 fixed-link {
 535                                                         speed = <1000>;
 536                                                         full-duplex;
 537                                                         pause;
 538                                                 };
 539                                         };
 540                                 };
 541                         };
 542                 };
 543         };
 544
 545         pcie: pcie@1e140000 {
 546                 compatible = "mediatek,mt7621-pci";
 547                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 548                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 549                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 550                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 551                 #address-cells = <3>;
 552                 #size-cells = <2>;
 553
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&pcie_pins>;
 556
 557                 device_type = "pci";
 558
 559                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 560                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 561
 562                 status = "disabled";
 563
 564                 #interrupt-cells = <1>;
 565                 interrupt-map-mask = <0xF800 0 0 0>;
 566                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 567                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 568                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 569
 570                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 571
 572                 pcie0: pcie@0,0 {
 573                         reg = <0x0000 0 0 0 0>;
 574                         #address-cells = <3>;
 575                         #size-cells = <2>;
 576                         device_type = "pci";
 577                         ranges;
 578                         #interrupt-cells = <1>;
 579                         interrupt-map-mask = <0 0 0 0>;
 580                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 581                         resets = <&rstctrl 24>;
 582                         clocks = <&sysc MT7621_CLK_PCIE0>;
 583                         phys = <&pcie0_phy 1>;
 584                         phy-names = "pcie-phy0";
 585                 };
 586
 587                 pcie1: pcie@1,0 {
 588                         reg = <0x0800 0 0 0 0>;
 589                         #address-cells = <3>;
 590                         #size-cells = <2>;
 591                         device_type = "pci";
 592                         ranges;
 593                         #interrupt-cells = <1>;
 594                         interrupt-map-mask = <0 0 0 0>;
 595                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 596                         resets = <&rstctrl 25>;
 597                         clocks = <&sysc MT7621_CLK_PCIE1>;
 598                         phys = <&pcie0_phy 1>;
 599                         phy-names = "pcie-phy1";
 600                 };
 601
 602                 pcie2: pcie@2,0 {
 603                         reg = <0x1000 0 0 0 0>;
 604                         #address-cells = <3>;
 605                         #size-cells = <2>;
 606                         device_type = "pci";
 607                         ranges;
 608                         #interrupt-cells = <1>;
 609                         interrupt-map-mask = <0 0 0 0>;
 610                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 611                         resets = <&rstctrl 26>;
 612                         clocks = <&sysc MT7621_CLK_PCIE2>;
 613                         phys = <&pcie2_phy 0>;
 614                         phy-names = "pcie-phy2";
 615                 };
 616         };
 617
 618         pcie0_phy: pcie-phy@1e149000 {
 619                 compatible = "mediatek,mt7621-pci-phy";
 620                 reg = <0x1e149000 0x0700>;
 621                 clocks = <&sysc MT7621_CLK_XTAL>;
 622                 #phy-cells = <1>;
 623         };
 624
 625         pcie2_phy: pcie-phy@1e14a000 {
 626                 compatible = "mediatek,mt7621-pci-phy";
 627                 reg = <0x1e14a000 0x0700>;
 628                 clocks = <&sysc MT7621_CLK_XTAL>;
 629                 #phy-cells = <1>;
 630         };
 631 };