target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/clock/mt7621-clk.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/interrupt-controller/mips-gic.h>
   6 #include <dt-bindings/reset/mt7621-reset.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         compatible = "mediatek,mt7621-soc";
  12
  13         aliases {
  14                 serial0 = &uartlite;
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "mips,mips1004Kc";
  24                         reg = <0>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "mips,mips1004Kc";
  30                         reg = <1>;
  31                 };
  32         };
  33
  34         cpuintc: cpuintc {
  35                 #address-cells = <0>;
  36                 #interrupt-cells = <1>;
  37                 interrupt-controller;
  38                 compatible = "mti,cpu-interrupt-controller";
  39         };
  40
  41         chosen {
  42                 bootargs = "console=ttyS0,57600";
  43         };
  44
  45         palmbus: palmbus@1e000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1e000000 0x100000>;
  48                 ranges = <0x0 0x1e000000 0x0fffff>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: syscon@0 {
  54                         compatible = "mediatek,mt7621-sysc", "syscon";
  55                         #clock-cells = <1>;
  56                         #reset-cells = <1>;
  57                         ralink,memctl = <&memc>;
  58                         clock-output-names = "xtal", "cpu", "bus",
  59                                              "50m", "125m", "150m",
  60                                              "250m", "270m";
  61                         reg = <0x0 0x100>;
  62                 };
  63
  64                 wdt: wdt@100 {
  65                         compatible = "mediatek,mt7621-wdt";
  66                         reg = <0x100 0x100>;
  67                 };
  68
  69                 gpio: gpio@600 {
  70                         #gpio-cells = <2>;
  71                         #interrupt-cells = <2>;
  72                         compatible = "mediatek,mt7621-gpio";
  73                         gpio-controller;
  74                         gpio-ranges = <&pinctrl 0 0 95>;
  75                         interrupt-controller;
  76                         reg = <0x600 0x100>;
  77                         interrupt-parent = <&gic>;
  78                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  79                 };
  80
  81                 i2c: i2c@900 {
  82                         compatible = "mediatek,mt7621-i2c";
  83                         reg = <0x900 0x100>;
  84
  85                         clocks = <&sysc MT7621_CLK_I2C>;
  86                         clock-names = "i2c";
  87
  88                         resets = <&sysc MT7621_RST_I2C>;
  89                         reset-names = "i2c";
  90
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93
  94                         status = "disabled";
  95
  96                         pinctrl-names = "default";
  97                         pinctrl-0 = <&i2c_pins>;
  98                 };
  99
 100                 i2s: i2s@a00 {
 101                         compatible = "mediatek,mt7621-i2s";
 102                         reg = <0xa00 0x100>;
 103
 104                         clocks = <&sysc MT7621_CLK_I2S>;
 105
 106                         resets = <&sysc MT7621_RST_I2S>;
 107                         reset-names = "i2s";
 108
 109                         interrupt-parent = <&gic>;
 110                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 111
 112                         txdma-req = <2>;
 113                         rxdma-req = <3>;
 114
 115                         dmas = <&gdma 4>,
 116                                 <&gdma 6>;
 117                         dma-names = "tx", "rx";
 118
 119                         status = "disabled";
 120                 };
 121
 122                 systick: systick@500 {
 123                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 124                         reg = <0x500 0x10>;
 125
 126                         resets = <&sysc MT7621_RST_AUX_STCK>;
 127                         reset-names = "intc";
 128
 129                         interrupt-parent = <&gic>;
 130                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 131                 };
 132
 133                 memc: memory-controller@5000 {
 134                         compatible = "mediatek,mt7621-memc", "syscon";
 135                         reg = <0x5000 0x1000>;
 136                 };
 137
 138                 uartlite: uartlite@c00 {
 139                         compatible = "ns16550a";
 140                         reg = <0xc00 0x100>;
 141
 142                         clocks = <&sysc MT7621_CLK_UART1>;
 143
 144                         resets = <&sysc MT7621_RST_UART1>;
 145
 146                         interrupt-parent = <&gic>;
 147                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 148
 149                         reg-shift = <2>;
 150                         reg-io-width = <4>;
 151                         no-loopback-test;
 152                 };
 153
 154                 uartlite2: uartlite2@d00 {
 155                         compatible = "ns16550a";
 156                         reg = <0xd00 0x100>;
 157
 158                         clocks = <&sysc MT7621_CLK_UART2>;
 159
 160                         resets = <&sysc MT7621_RST_UART2>;
 161
 162                         interrupt-parent = <&gic>;
 163                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 164
 165                         reg-shift = <2>;
 166                         reg-io-width = <4>;
 167
 168                         pinctrl-names = "default";
 169                         pinctrl-0 = <&uart2_pins>;
 170
 171                         status = "disabled";
 172                 };
 173
 174                 uartlite3: uartlite3@e00 {
 175                         compatible = "ns16550a";
 176                         reg = <0xe00 0x100>;
 177
 178                         clocks = <&sysc MT7621_CLK_UART3>;
 179
 180                         resets = <&sysc MT7621_RST_UART3>;
 181
 182                         interrupt-parent = <&gic>;
 183                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                         reg-shift = <2>;
 186                         reg-io-width = <4>;
 187
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&uart3_pins>;
 190
 191                         status = "disabled";
 192                 };
 193
 194                 spi0: spi@b00 {
 195                         status = "disabled";
 196
 197                         compatible = "ralink,mt7621-spi";
 198                         reg = <0xb00 0x100>;
 199
 200                         clocks = <&sysc MT7621_CLK_SPI>;
 201                         clock-names = "spi";
 202
 203                         resets = <&sysc MT7621_RST_SPI>;
 204                         reset-names = "spi";
 205
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208
 209                         pinctrl-names = "default";
 210                         pinctrl-0 = <&spi_pins>;
 211                 };
 212
 213                 gdma: gdma@2800 {
 214                         compatible = "ralink,rt3883-gdma";
 215                         reg = <0x2800 0x800>;
 216
 217                         resets = <&sysc MT7621_RST_GDMA>;
 218                         reset-names = "dma";
 219
 220                         interrupt-parent = <&gic>;
 221                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 222
 223                         #dma-cells = <1>;
 224                         #dma-channels = <16>;
 225                         #dma-requests = <16>;
 226
 227                         status = "disabled";
 228                 };
 229
 230                 hsdma: hsdma@7000 {
 231                         compatible = "mediatek,mt7621-hsdma";
 232                         reg = <0x7000 0x1000>;
 233
 234                         resets = <&sysc MT7621_RST_HSDMA>;
 235                         reset-names = "hsdma";
 236
 237                         interrupt-parent = <&gic>;
 238                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 239
 240                         #dma-cells = <1>;
 241                         #dma-channels = <1>;
 242                         #dma-requests = <1>;
 243
 244                         status = "disabled";
 245                 };
 246         };
 247
 248         pinctrl: pinctrl {
 249                 compatible = "ralink,rt2880-pinmux";
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&state_default>;
 252
 253                 state_default: pinctrl0 {
 254                 };
 255
 256                 i2c_pins: i2c_pins {
 257                         i2c_pins {
 258                                 groups = "i2c";
 259                                 function = "i2c";
 260                         };
 261                 };
 262
 263                 spi_pins: spi_pins {
 264                         spi_pins {
 265                                 groups = "spi";
 266                                 function = "spi";
 267                         };
 268                 };
 269
 270                 uart1_pins: uart1 {
 271                         uart1 {
 272                                 groups = "uart1";
 273                                 function = "uart1";
 274                         };
 275                 };
 276
 277                 uart2_pins: uart2 {
 278                         uart2 {
 279                                 groups = "uart2";
 280                                 function = "uart2";
 281                         };
 282                 };
 283
 284                 uart3_pins: uart3 {
 285                         uart3 {
 286                                 groups = "uart3";
 287                                 function = "uart3";
 288                         };
 289                 };
 290
 291                 rgmii1_pins: rgmii1 {
 292                         rgmii1 {
 293                                 groups = "rgmii1";
 294                                 function = "rgmii1";
 295                         };
 296                 };
 297
 298                 rgmii2_pins: rgmii2 {
 299                         rgmii2 {
 300                                 groups = "rgmii2";
 301                                 function = "rgmii2";
 302                         };
 303                 };
 304
 305                 mdio_pins: mdio {
 306                         mdio {
 307                                 groups = "mdio";
 308                                 function = "mdio";
 309                         };
 310                 };
 311
 312                 pcie_pins: pcie {
 313                         pcie {
 314                                 groups = "pcie";
 315                                 function = "gpio";
 316                         };
 317                 };
 318
 319                 nand_pins: nand {
 320                         spi-nand {
 321                                 groups = "spi";
 322                                 function = "nand1";
 323                         };
 324
 325                         sdhci-nand {
 326                                 groups = "sdhci";
 327                                 function = "nand2";
 328                         };
 329                 };
 330
 331                 sdhci_pins: sdhci {
 332                         sdhci {
 333                                 groups = "sdhci";
 334                                 function = "sdhci";
 335                         };
 336                 };
 337         };
 338
 339         sdhci: sdhci@1e130000 {
 340                 status = "disabled";
 341
 342                 compatible = "ralink,mt7620-sdhci";
 343                 reg = <0x1e130000 0x4000>;
 344
 345                 interrupt-parent = <&gic>;
 346                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 347
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&sdhci_pins>;
 350         };
 351
 352         xhci: xhci@1e1c0000 {
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355
 356                 compatible = "mediatek,mt8173-xhci";
 357                 reg = <0x1e1c0000 0x1000
 358                        0x1e1d0700 0x0100>;
 359                 reg-names = "mac", "ippc";
 360
 361                 clocks = <&sysc MT7621_CLK_XTAL>;
 362                 clock-names = "sys_ck";
 363
 364                 interrupt-parent = <&gic>;
 365                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 366
 367                 /*
 368                  * Port 1 of both hubs is one usb slot and referenced here.
 369                  * The binding doesn't allow to address individual hubs.
 370                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 371                  */
 372                 xhci_ehci_port1: port@1 {
 373                         reg = <1>;
 374                         #trigger-source-cells = <0>;
 375                 };
 376
 377                 /*
 378                  * Only the second usb hub has a second port. That port serves
 379                  * ehci and ohci.
 380                  */
 381                 ehci_port2: port@2 {
 382                         reg = <2>;
 383                         #trigger-source-cells = <0>;
 384                 };
 385         };
 386
 387         gic: interrupt-controller@1fbc0000 {
 388                 compatible = "mti,gic";
 389                 reg = <0x1fbc0000 0x2000>;
 390
 391                 interrupt-controller;
 392                 #interrupt-cells = <3>;
 393
 394                 mti,reserved-cpu-vectors = <7>;
 395
 396                 timer {
 397                         compatible = "mti,gic-timer";
 398                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 399                         clocks = <&sysc MT7621_CLK_CPU>;
 400                 };
 401         };
 402
 403         cpc: cpc@1fbf0000 {
 404                 compatible = "mti,mips-cpc";
 405                 reg = <0x1fbf0000 0x8000>;
 406         };
 407
 408         mc: mc@1fbf8000 {
 409                 compatible = "mti,mips-cdmm";
 410                 reg = <0x1fbf8000 0x8000>;
 411         };
 412
 413         nand: nand@1e003000 {
 414                 status = "disabled";
 415
 416                 compatible = "mediatek,mt7621-nfc";
 417                 reg = <0x1e003000 0x800
 418                         0x1e003800 0x800>;
 419                 reg-names = "nfi", "ecc";
 420
 421                 clocks = <&sysc MT7621_CLK_NAND>;
 422                 clock-names = "nfi_clk";
 423         };
 424
 425         ethernet: ethernet@1e100000 {
 426                 compatible = "mediatek,mt7621-eth";
 427                 reg = <0x1e100000 0x10000>;
 428
 429                 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
 430                 clock-names = "fe", "ethif";
 431
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434
 435                 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
 436                 reset-names = "fe", "eth";
 437
 438                 interrupt-parent = <&gic>;
 439                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 440
 441                 mediatek,ethsys = <&sysc>;
 442
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
 445
 446                 gmac0: mac@0 {
 447                         compatible = "mediatek,eth-mac";
 448                         reg = <0>;
 449                         phy-mode = "rgmii";
 450
 451                         fixed-link {
 452                                 speed = <1000>;
 453                                 full-duplex;
 454                                 pause;
 455                         };
 456                 };
 457
 458                 gmac1: mac@1 {
 459                         compatible = "mediatek,eth-mac";
 460                         reg = <1>;
 461                         status = "disabled";
 462                         phy-mode = "rgmii";
 463                 };
 464
 465                 mdio: mdio-bus {
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468
 469                         switch0: switch@1f {
 470                                 compatible = "mediatek,mt7621";
 471                                 reg = <0x1f>;
 472                                 mediatek,mcm;
 473                                 resets = <&sysc MT7621_RST_MCM>;
 474                                 reset-names = "mcm";
 475                                 interrupt-controller;
 476                                 #interrupt-cells = <1>;
 477                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 478
 479                                 ports {
 480                                         #address-cells = <1>;
 481                                         #size-cells = <0>;
 482
 483                                         port@0 {
 484                                                 status = "disabled";
 485                                                 reg = <0>;
 486                                                 label = "lan0";
 487                                         };
 488
 489                                         port@1 {
 490                                                 status = "disabled";
 491                                                 reg = <1>;
 492                                                 label = "lan1";
 493                                         };
 494
 495                                         port@2 {
 496                                                 status = "disabled";
 497                                                 reg = <2>;
 498                                                 label = "lan2";
 499                                         };
 500
 501                                         port@3 {
 502                                                 status = "disabled";
 503                                                 reg = <3>;
 504                                                 label = "lan3";
 505                                         };
 506
 507                                         port@4 {
 508                                                 status = "disabled";
 509                                                 reg = <4>;
 510                                                 label = "lan4";
 511                                         };
 512
 513                                         port@6 {
 514                                                 reg = <6>;
 515                                                 ethernet = <&gmac0>;
 516                                                 phy-mode = "rgmii";
 517
 518                                                 fixed-link {
 519                                                         speed = <1000>;
 520                                                         full-duplex;
 521                                                         pause;
 522                                                 };
 523                                         };
 524                                 };
 525                         };
 526                 };
 527         };
 528
 529         pcie: pcie@1e140000 {
 530                 compatible = "mediatek,mt7621-pci";
 531                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 532                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 533                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 534                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 535                 #address-cells = <3>;
 536                 #size-cells = <2>;
 537
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&pcie_pins>;
 540
 541                 device_type = "pci";
 542
 543                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 544                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 545
 546                 status = "disabled";
 547
 548                 #interrupt-cells = <1>;
 549                 interrupt-map-mask = <0xF800 0 0 0>;
 550                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 551                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 552                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 553
 554                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 555
 556                 pcie0: pcie@0,0 {
 557                         reg = <0x0000 0 0 0 0>;
 558                         #address-cells = <3>;
 559                         #size-cells = <2>;
 560                         device_type = "pci";
 561                         ranges;
 562                         #interrupt-cells = <1>;
 563                         interrupt-map-mask = <0 0 0 0>;
 564                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 565                         resets = <&sysc MT7621_RST_PCIE0>;
 566                         clocks = <&sysc MT7621_CLK_PCIE0>;
 567                         phys = <&pcie0_phy 1>;
 568                         phy-names = "pcie-phy0";
 569                 };
 570
 571                 pcie1: pcie@1,0 {
 572                         reg = <0x0800 0 0 0 0>;
 573                         #address-cells = <3>;
 574                         #size-cells = <2>;
 575                         device_type = "pci";
 576                         ranges;
 577                         #interrupt-cells = <1>;
 578                         interrupt-map-mask = <0 0 0 0>;
 579                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 580                         resets = <&sysc MT7621_RST_PCIE1>;
 581                         clocks = <&sysc MT7621_CLK_PCIE1>;
 582                         phys = <&pcie0_phy 1>;
 583                         phy-names = "pcie-phy1";
 584                 };
 585
 586                 pcie2: pcie@2,0 {
 587                         reg = <0x1000 0 0 0 0>;
 588                         #address-cells = <3>;
 589                         #size-cells = <2>;
 590                         device_type = "pci";
 591                         ranges;
 592                         #interrupt-cells = <1>;
 593                         interrupt-map-mask = <0 0 0 0>;
 594                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 595                         resets = <&sysc MT7621_RST_PCIE2>;
 596                         clocks = <&sysc MT7621_CLK_PCIE2>;
 597                         phys = <&pcie2_phy 0>;
 598                         phy-names = "pcie-phy2";
 599                 };
 600         };
 601
 602         pcie0_phy: pcie-phy@1e149000 {
 603                 compatible = "mediatek,mt7621-pci-phy";
 604                 reg = <0x1e149000 0x0700>;
 605                 clocks = <&sysc MT7621_CLK_XTAL>;
 606                 #phy-cells = <1>;
 607         };
 608
 609         pcie2_phy: pcie-phy@1e14a000 {
 610                 compatible = "mediatek,mt7621-pci-phy";
 611                 reg = <0x1e14a000 0x0700>;
 612                 clocks = <&sysc MT7621_CLK_XTAL>;
 613                 #phy-cells = <1>;
 614         };
 615 };