target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/mips-gic.h>
   4 #include <dt-bindings/clock/mt7621-clk.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "mediatek,mt7621-soc";
  11
  12         aliases {
  13                 serial0 = &uartlite;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "mips,mips1004Kc";
  23                         reg = <0>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "mips,mips1004Kc";
  29                         reg = <1>;
  30                 };
  31         };
  32
  33         cpuintc: cpuintc {
  34                 #address-cells = <0>;
  35                 #interrupt-cells = <1>;
  36                 interrupt-controller;
  37                 compatible = "mti,cpu-interrupt-controller";
  38         };
  39
  40         chosen {
  41                 bootargs = "console=ttyS0,57600";
  42         };
  43
  44         pll: pll {
  45                 compatible = "mediatek,mt7621-pll", "syscon";
  46
  47                 #clock-cells = <1>;
  48                 clock-output-names = "cpu", "bus";
  49         };
  50
  51         sysclock: sysclock {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-clock";
  54
  55                 /* FIXME: there should be way to detect this */
  56                 clock-frequency = <50000000>;
  57         };
  58
  59         palmbus: palmbus@1e000000 {
  60                 compatible = "palmbus";
  61                 reg = <0x1e000000 0x100000>;
  62                 ranges = <0x0 0x1e000000 0x0fffff>;
  63
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66
  67                 sysc: sysc@0 {
  68                         compatible = "mtk,mt7621-sysc";
  69                         reg = <0x0 0x100>;
  70                 };
  71
  72                 wdt: wdt@100 {
  73                         compatible = "mediatek,mt7621-wdt";
  74                         reg = <0x100 0x100>;
  75                 };
  76
  77                 gpio: gpio@600 {
  78                         #gpio-cells = <2>;
  79                         #interrupt-cells = <2>;
  80                         compatible = "mediatek,mt7621-gpio";
  81                         gpio-controller;
  82                         interrupt-controller;
  83                         reg = <0x600 0x100>;
  84                         interrupt-parent = <&gic>;
  85                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  86                 };
  87
  88                 i2c: i2c@900 {
  89                         compatible = "mediatek,mt7621-i2c";
  90                         reg = <0x900 0x100>;
  91
  92                         clocks = <&sysclock>;
  93
  94                         resets = <&rstctrl 16>;
  95                         reset-names = "i2c";
  96
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99
 100                         status = "disabled";
 101
 102                         pinctrl-names = "default";
 103                         pinctrl-0 = <&i2c_pins>;
 104                 };
 105
 106                 i2s: i2s@a00 {
 107                         compatible = "mediatek,mt7621-i2s";
 108                         reg = <0xa00 0x100>;
 109
 110                         clocks = <&sysclock>;
 111
 112                         resets = <&rstctrl 17>;
 113                         reset-names = "i2s";
 114
 115                         interrupt-parent = <&gic>;
 116                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 117
 118                         txdma-req = <2>;
 119                         rxdma-req = <3>;
 120
 121                         dmas = <&gdma 4>,
 122                                 <&gdma 6>;
 123                         dma-names = "tx", "rx";
 124
 125                         status = "disabled";
 126                 };
 127
 128                 systick: systick@500 {
 129                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 130                         reg = <0x500 0x10>;
 131
 132                         resets = <&rstctrl 28>;
 133                         reset-names = "intc";
 134
 135                         interrupt-parent = <&gic>;
 136                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 137                 };
 138
 139                 memc: memc@5000 {
 140                         compatible = "mtk,mt7621-memc";
 141                         reg = <0x5000 0x1000>;
 142                 };
 143
 144                 uartlite: uartlite@c00 {
 145                         compatible = "ns16550a";
 146                         reg = <0xc00 0x100>;
 147
 148                         clock-frequency = <50000000>;
 149
 150                         interrupt-parent = <&gic>;
 151                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 152
 153                         reg-shift = <2>;
 154                         reg-io-width = <4>;
 155                         no-loopback-test;
 156                 };
 157
 158                 uartlite2: uartlite2@d00 {
 159                         compatible = "ns16550a";
 160                         reg = <0xd00 0x100>;
 161
 162                         clock-frequency = <50000000>;
 163
 164                         interrupt-parent = <&gic>;
 165                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 166
 167                         reg-shift = <2>;
 168                         reg-io-width = <4>;
 169
 170                         pinctrl-names = "default";
 171                         pinctrl-0 = <&uart2_pins>;
 172
 173                         status = "disabled";
 174                 };
 175
 176                 uartlite3: uartlite3@e00 {
 177                         compatible = "ns16550a";
 178                         reg = <0xe00 0x100>;
 179
 180                         clock-frequency = <50000000>;
 181
 182                         interrupt-parent = <&gic>;
 183                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                         reg-shift = <2>;
 186                         reg-io-width = <4>;
 187
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&uart3_pins>;
 190
 191                         status = "disabled";
 192                 };
 193
 194                 spi0: spi@b00 {
 195                         status = "disabled";
 196
 197                         compatible = "ralink,mt7621-spi";
 198                         reg = <0xb00 0x100>;
 199
 200                         clocks = <&pll MT7621_CLK_BUS>;
 201
 202                         resets = <&rstctrl 18>;
 203                         reset-names = "spi";
 204
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&spi_pins>;
 210                 };
 211
 212                 gdma: gdma@2800 {
 213                         compatible = "ralink,rt3883-gdma";
 214                         reg = <0x2800 0x800>;
 215
 216                         resets = <&rstctrl 14>;
 217                         reset-names = "dma";
 218
 219                         interrupt-parent = <&gic>;
 220                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 221
 222                         #dma-cells = <1>;
 223                         #dma-channels = <16>;
 224                         #dma-requests = <16>;
 225
 226                         status = "disabled";
 227                 };
 228
 229                 hsdma: hsdma@7000 {
 230                         compatible = "mediatek,mt7621-hsdma";
 231                         reg = <0x7000 0x1000>;
 232
 233                         resets = <&rstctrl 5>;
 234                         reset-names = "hsdma";
 235
 236                         interrupt-parent = <&gic>;
 237                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 238
 239                         #dma-cells = <1>;
 240                         #dma-channels = <1>;
 241                         #dma-requests = <1>;
 242
 243                         status = "disabled";
 244                 };
 245         };
 246
 247         pinctrl: pinctrl {
 248                 compatible = "ralink,rt2880-pinmux";
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&state_default>;
 251
 252                 state_default: pinctrl0 {
 253                 };
 254
 255                 i2c_pins: i2c_pins {
 256                         i2c_pins {
 257                                 groups = "i2c";
 258                                 function = "i2c";
 259                         };
 260                 };
 261
 262                 spi_pins: spi_pins {
 263                         spi_pins {
 264                                 groups = "spi";
 265                                 function = "spi";
 266                         };
 267                 };
 268
 269                 uart1_pins: uart1 {
 270                         uart1 {
 271                                 groups = "uart1";
 272                                 function = "uart1";
 273                         };
 274                 };
 275
 276                 uart2_pins: uart2 {
 277                         uart2 {
 278                                 groups = "uart2";
 279                                 function = "uart2";
 280                         };
 281                 };
 282
 283                 uart3_pins: uart3 {
 284                         uart3 {
 285                                 groups = "uart3";
 286                                 function = "uart3";
 287                         };
 288                 };
 289
 290                 rgmii1_pins: rgmii1 {
 291                         rgmii1 {
 292                                 groups = "rgmii1";
 293                                 function = "rgmii1";
 294                         };
 295                 };
 296
 297                 rgmii2_pins: rgmii2 {
 298                         rgmii2 {
 299                                 groups = "rgmii2";
 300                                 function = "rgmii2";
 301                         };
 302                 };
 303
 304                 mdio_pins: mdio {
 305                         mdio {
 306                                 groups = "mdio";
 307                                 function = "mdio";
 308                         };
 309                 };
 310
 311                 pcie_pins: pcie {
 312                         pcie {
 313                                 groups = "pcie";
 314                                 function = "gpio";
 315                         };
 316                 };
 317
 318                 nand_pins: nand {
 319                         spi-nand {
 320                                 groups = "spi";
 321                                 function = "nand1";
 322                         };
 323
 324                         sdhci-nand {
 325                                 groups = "sdhci";
 326                                 function = "nand2";
 327                         };
 328                 };
 329
 330                 sdhci_pins: sdhci {
 331                         sdhci {
 332                                 groups = "sdhci";
 333                                 function = "sdhci";
 334                         };
 335                 };
 336         };
 337
 338         rstctrl: rstctrl {
 339                 compatible = "ralink,rt2880-reset";
 340                 #reset-cells = <1>;
 341         };
 342
 343         clkctrl: clkctrl {
 344                 compatible = "ralink,rt2880-clock";
 345                 #clock-cells = <1>;
 346         };
 347
 348         sdhci: sdhci@1e130000 {
 349                 status = "disabled";
 350
 351                 compatible = "ralink,mt7620-sdhci";
 352                 reg = <0x1e130000 0x4000>;
 353
 354                 interrupt-parent = <&gic>;
 355                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 356
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&sdhci_pins>;
 359         };
 360
 361         xhci: xhci@1e1c0000 {
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364
 365                 compatible = "mediatek,mt8173-xhci";
 366                 reg = <0x1e1c0000 0x1000
 367                        0x1e1d0700 0x0100>;
 368                 reg-names = "mac", "ippc";
 369
 370                 clocks = <&sysclock>;
 371                 clock-names = "sys_ck";
 372
 373                 interrupt-parent = <&gic>;
 374                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 375
 376                 /*
 377                  * Port 1 of both hubs is one usb slot and referenced here.
 378                  * The binding doesn't allow to address individual hubs.
 379                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 380                  */
 381                 xhci_ehci_port1: port@1 {
 382                         reg = <1>;
 383                         #trigger-source-cells = <0>;
 384                 };
 385
 386                 /*
 387                  * Only the second usb hub has a second port. That port serves
 388                  * ehci and ohci.
 389                  */
 390                 ehci_port2: port@2 {
 391                         reg = <2>;
 392                         #trigger-source-cells = <0>;
 393                 };
 394         };
 395
 396         gic: interrupt-controller@1fbc0000 {
 397                 compatible = "mti,gic";
 398                 reg = <0x1fbc0000 0x2000>;
 399
 400                 interrupt-controller;
 401                 #interrupt-cells = <3>;
 402
 403                 mti,reserved-cpu-vectors = <7>;
 404
 405                 timer {
 406                         compatible = "mti,gic-timer";
 407                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 408                         clocks = <&pll MT7621_CLK_CPU>;
 409                 };
 410         };
 411
 412         nficlock: nficlock {
 413                 #clock-cells = <0>;
 414                 compatible = "fixed-clock";
 415
 416                 clock-frequency = <125000000>;
 417         };
 418
 419         cpc: cpc@1fbf0000 {
 420                 compatible = "mti,mips-cpc";
 421                 reg = <0x1fbf0000 0x8000>;
 422         };
 423
 424         mc: mc@1fbf8000 {
 425                 compatible = "mti,mips-cdmm";
 426                 reg = <0x1fbf8000 0x8000>;
 427         };
 428
 429         nand: nand@1e003000 {
 430                 status = "disabled";
 431
 432                 compatible = "mediatek,mt7621-nfc";
 433                 reg = <0x1e003000 0x800
 434                         0x1e003800 0x800>;
 435                 reg-names = "nfi", "ecc";
 436
 437                 clocks = <&nficlock>;
 438                 clock-names = "nfi_clk";
 439         };
 440
 441         ethsys: syscon@1e000000 {
 442                 compatible = "mediatek,mt7621-ethsys",
 443                              "syscon";
 444                 reg = <0x1e000000 0x1000>;
 445                 #clock-cells = <1>;
 446         };
 447
 448         ethernet: ethernet@1e100000 {
 449                 compatible = "mediatek,mt7621-eth";
 450                 reg = <0x1e100000 0x10000>;
 451
 452                 clocks = <&sysclock>;
 453                 clock-names = "ethif";
 454
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457
 458                 resets = <&rstctrl 6 &rstctrl 23>;
 459                 reset-names = "fe", "eth";
 460
 461                 interrupt-parent = <&gic>;
 462                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 463
 464                 mediatek,ethsys = <&ethsys>;
 465
 466                 gmac0: mac@0 {
 467                         compatible = "mediatek,eth-mac";
 468                         reg = <0>;
 469                         phy-mode = "rgmii";
 470
 471                         fixed-link {
 472                                 speed = <1000>;
 473                                 full-duplex;
 474                                 pause;
 475                         };
 476                 };
 477
 478                 gmac1: mac@1 {
 479                         compatible = "mediatek,eth-mac";
 480                         reg = <1>;
 481                         status = "disabled";
 482                         phy-mode = "rgmii-rxid";
 483                 };
 484
 485                 mdio: mdio-bus {
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488
 489                         switch0: switch@1f {
 490                                 compatible = "mediatek,mt7621";
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                                 reg = <0x1f>;
 494                                 mediatek,mcm;
 495                                 resets = <&rstctrl 2>;
 496                                 reset-names = "mcm";
 497
 498                                 ports {
 499                                         #address-cells = <1>;
 500                                         #size-cells = <0>;
 501                                         reg = <0>;
 502
 503                                         port@0 {
 504                                                 status = "disabled";
 505                                                 reg = <0>;
 506                                                 label = "lan0";
 507                                         };
 508
 509                                         port@1 {
 510                                                 status = "disabled";
 511                                                 reg = <1>;
 512                                                 label = "lan1";
 513                                         };
 514
 515                                         port@2 {
 516                                                 status = "disabled";
 517                                                 reg = <2>;
 518                                                 label = "lan2";
 519                                         };
 520
 521                                         port@3 {
 522                                                 status = "disabled";
 523                                                 reg = <3>;
 524                                                 label = "lan3";
 525                                         };
 526
 527                                         port@4 {
 528                                                 status = "disabled";
 529                                                 reg = <4>;
 530                                                 label = "lan4";
 531                                         };
 532
 533                                         port@6 {
 534                                                 reg = <6>;
 535                                                 label = "cpu";
 536                                                 ethernet = <&gmac0>;
 537                                                 phy-mode = "rgmii";
 538
 539                                                 fixed-link {
 540                                                         speed = <1000>;
 541                                                         full-duplex;
 542                                                 };
 543                                         };
 544                                 };
 545                         };
 546                 };
 547         };
 548
 549         pcie: pcie@1e140000 {
 550                 compatible = "mediatek,mt7621-pci";
 551                 reg = <0x1e140000 0x100     /* host-pci bridge registers */
 552                         0x1e142000 0x100    /* pcie port 0 RC control registers */
 553                         0x1e143000 0x100    /* pcie port 1 RC control registers */
 554                         0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 555                 #address-cells = <3>;
 556                 #size-cells = <2>;
 557
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&pcie_pins>;
 560
 561                 device_type = "pci";
 562
 563                 bus-range = <0 255>;
 564                 ranges = <
 565                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 566                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 567                 >;
 568
 569                 interrupt-parent = <&gic>;
 570                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 571                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 572                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 573
 574                 status = "disabled";
 575
 576                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 577                 reset-names = "pcie0", "pcie1", "pcie2";
 578                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 579                 clock-names = "pcie0", "pcie1", "pcie2";
 580                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 581                 phy-names = "pcie-phy0", "pcie-phy2";
 582
 583                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 584
 585                 pcie0: pcie@0,0 {
 586                         reg = <0x0000 0 0 0 0>;
 587                         #address-cells = <3>;
 588                         #size-cells = <2>;
 589                         ranges;
 590                         bus-range = <0x00 0xff>;
 591                 };
 592
 593                 pcie1: pcie@1,0 {
 594                         reg = <0x0800 0 0 0 0>;
 595                         #address-cells = <3>;
 596                         #size-cells = <2>;
 597                         ranges;
 598                         bus-range = <0x00 0xff>;
 599                 };
 600
 601                 pcie2: pcie@2,0 {
 602                         reg = <0x1000 0 0 0 0>;
 603                         #address-cells = <3>;
 604                         #size-cells = <2>;
 605                         ranges;
 606                         bus-range = <0x00 0xff>;
 607                 };
 608         };
 609
 610         pcie0_phy: pcie-phy@1e149000 {
 611                 compatible = "mediatek,mt7621-pci-phy";
 612                 reg = <0x1e149000 0x0700>;
 613                 #phy-cells = <1>;
 614         };
 615
 616         pcie2_phy: pcie-phy@1e14a000 {
 617                 compatible = "mediatek,mt7621-pci-phy";
 618                 reg = <0x1e14a000 0x0700>;
 619                 #phy-cells = <1>;
 620         };
 621 };