target/linux/ramips/dts/mt7621.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/clock/mt7621-clk.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/interrupt-controller/mips-gic.h>
   6 #include <dt-bindings/reset/mt7621-reset.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         compatible = "mediatek,mt7621-soc";
  12
  13         aliases {
  14                 serial0 = &uartlite;
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "mips,mips1004Kc";
  24                         reg = <0>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "mips,mips1004Kc";
  30                         reg = <1>;
  31                 };
  32         };
  33
  34         cpuintc: cpuintc {
  35                 #address-cells = <0>;
  36                 #interrupt-cells = <1>;
  37                 interrupt-controller;
  38                 compatible = "mti,cpu-interrupt-controller";
  39         };
  40
  41         chosen {
  42                 bootargs = "console=ttyS0,57600";
  43         };
  44
  45         palmbus: palmbus@1e000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1e000000 0x100000>;
  48                 ranges = <0x0 0x1e000000 0x0fffff>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: syscon@0 {
  54                         compatible = "mediatek,mt7621-sysc", "syscon";
  55                         #clock-cells = <1>;
  56                         #reset-cells = <1>;
  57                         ralink,memctl = <&memc>;
  58                         clock-output-names = "xtal", "cpu", "bus",
  59                                              "50m", "125m", "150m",
  60                                              "250m", "270m";
  61                         reg = <0x0 0x100>;
  62                 };
  63
  64                 wdt: watchdog@100 {
  65                         compatible = "mediatek,mt7621-wdt";
  66                         reg = <0x100 0x100>;
  67                         mediatek,sysctl = <&sysc>;
  68                 };
  69
  70                 gpio: gpio@600 {
  71                         #gpio-cells = <2>;
  72                         #interrupt-cells = <2>;
  73                         compatible = "mediatek,mt7621-gpio";
  74                         gpio-controller;
  75                         gpio-ranges = <&pinctrl 0 0 95>;
  76                         interrupt-controller;
  77                         reg = <0x600 0x100>;
  78                         interrupt-parent = <&gic>;
  79                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  80                 };
  81
  82                 i2c: i2c@900 {
  83                         compatible = "mediatek,mt7621-i2c";
  84                         reg = <0x900 0x100>;
  85
  86                         clocks = <&sysc MT7621_CLK_I2C>;
  87                         clock-names = "i2c";
  88
  89                         resets = <&sysc MT7621_RST_I2C>;
  90                         reset-names = "i2c";
  91
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94
  95                         status = "disabled";
  96
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&i2c_pins>;
  99                 };
 100
 101                 i2s: i2s@a00 {
 102                         compatible = "mediatek,mt7621-i2s";
 103                         reg = <0xa00 0x100>;
 104
 105                         clocks = <&sysc MT7621_CLK_I2S>;
 106
 107                         resets = <&sysc MT7621_RST_I2S>;
 108                         reset-names = "i2s";
 109
 110                         interrupt-parent = <&gic>;
 111                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 112
 113                         txdma-req = <2>;
 114                         rxdma-req = <3>;
 115
 116                         dmas = <&gdma 4>,
 117                                 <&gdma 6>;
 118                         dma-names = "tx", "rx";
 119
 120                         status = "disabled";
 121                 };
 122
 123                 memc: memory-controller@5000 {
 124                         compatible = "mediatek,mt7621-memc", "syscon";
 125                         reg = <0x5000 0x1000>;
 126                 };
 127
 128                 uartlite: uartlite@c00 {
 129                         compatible = "ns16550a";
 130                         reg = <0xc00 0x100>;
 131
 132                         clocks = <&sysc MT7621_CLK_UART1>;
 133
 134                         resets = <&sysc MT7621_RST_UART1>;
 135
 136                         interrupt-parent = <&gic>;
 137                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 138
 139                         reg-shift = <2>;
 140                         reg-io-width = <4>;
 141                         no-loopback-test;
 142                 };
 143
 144                 uartlite2: uartlite2@d00 {
 145                         compatible = "ns16550a";
 146                         reg = <0xd00 0x100>;
 147
 148                         clocks = <&sysc MT7621_CLK_UART2>;
 149
 150                         resets = <&sysc MT7621_RST_UART2>;
 151
 152                         interrupt-parent = <&gic>;
 153                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 154
 155                         reg-shift = <2>;
 156                         reg-io-width = <4>;
 157
 158                         pinctrl-names = "default";
 159                         pinctrl-0 = <&uart2_pins>;
 160
 161                         status = "disabled";
 162                 };
 163
 164                 uartlite3: uartlite3@e00 {
 165                         compatible = "ns16550a";
 166                         reg = <0xe00 0x100>;
 167
 168                         clocks = <&sysc MT7621_CLK_UART3>;
 169
 170                         resets = <&sysc MT7621_RST_UART3>;
 171
 172                         interrupt-parent = <&gic>;
 173                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 174
 175                         reg-shift = <2>;
 176                         reg-io-width = <4>;
 177
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&uart3_pins>;
 180
 181                         status = "disabled";
 182                 };
 183
 184                 spi0: spi@b00 {
 185                         status = "disabled";
 186
 187                         compatible = "ralink,mt7621-spi";
 188                         reg = <0xb00 0x100>;
 189
 190                         clocks = <&sysc MT7621_CLK_SPI>;
 191                         clock-names = "spi";
 192
 193                         resets = <&sysc MT7621_RST_SPI>;
 194                         reset-names = "spi";
 195
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198
 199                         pinctrl-names = "default";
 200                         pinctrl-0 = <&spi_pins>;
 201                 };
 202
 203                 gdma: gdma@2800 {
 204                         compatible = "ralink,rt3883-gdma";
 205                         reg = <0x2800 0x800>;
 206
 207                         resets = <&sysc MT7621_RST_GDMA>;
 208                         reset-names = "dma";
 209
 210                         interrupt-parent = <&gic>;
 211                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 212
 213                         #dma-cells = <1>;
 214                         #dma-channels = <16>;
 215                         #dma-requests = <16>;
 216
 217                         status = "disabled";
 218                 };
 219
 220                 hsdma: hsdma@7000 {
 221                         compatible = "mediatek,mt7621-hsdma";
 222                         reg = <0x7000 0x1000>;
 223
 224                         resets = <&sysc MT7621_RST_HSDMA>;
 225                         reset-names = "hsdma";
 226
 227                         interrupt-parent = <&gic>;
 228                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 229
 230                         #dma-cells = <1>;
 231                         #dma-channels = <1>;
 232                         #dma-requests = <1>;
 233
 234                         status = "disabled";
 235                 };
 236         };
 237
 238         pinctrl: pinctrl {
 239                 compatible = "ralink,rt2880-pinmux";
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&state_default>;
 242
 243                 state_default: pinctrl0 {
 244                 };
 245
 246                 i2c_pins: i2c_pins {
 247                         i2c_pins {
 248                                 groups = "i2c";
 249                                 function = "i2c";
 250                         };
 251                 };
 252
 253                 spi_pins: spi_pins {
 254                         spi_pins {
 255                                 groups = "spi";
 256                                 function = "spi";
 257                         };
 258                 };
 259
 260                 uart1_pins: uart1 {
 261                         uart1 {
 262                                 groups = "uart1";
 263                                 function = "uart1";
 264                         };
 265                 };
 266
 267                 uart2_pins: uart2 {
 268                         uart2 {
 269                                 groups = "uart2";
 270                                 function = "uart2";
 271                         };
 272                 };
 273
 274                 uart3_pins: uart3 {
 275                         uart3 {
 276                                 groups = "uart3";
 277                                 function = "uart3";
 278                         };
 279                 };
 280
 281                 rgmii1_pins: rgmii1 {
 282                         rgmii1 {
 283                                 groups = "rgmii1";
 284                                 function = "rgmii1";
 285                         };
 286                 };
 287
 288                 rgmii2_pins: rgmii2 {
 289                         rgmii2 {
 290                                 groups = "rgmii2";
 291                                 function = "rgmii2";
 292                         };
 293                 };
 294
 295                 mdio_pins: mdio {
 296                         mdio {
 297                                 groups = "mdio";
 298                                 function = "mdio";
 299                         };
 300                 };
 301
 302                 pcie_pins: pcie {
 303                         pcie {
 304                                 groups = "pcie";
 305                                 function = "gpio";
 306                         };
 307                 };
 308
 309                 nand_pins: nand {
 310                         spi-nand {
 311                                 groups = "spi";
 312                                 function = "nand1";
 313                         };
 314
 315                         sdhci-nand {
 316                                 groups = "sdhci";
 317                                 function = "nand2";
 318                         };
 319                 };
 320
 321                 sdhci_pins: sdhci {
 322                         sdhci {
 323                                 groups = "sdhci";
 324                                 function = "sdhci";
 325                         };
 326                 };
 327         };
 328
 329         sdhci: sdhci@1e130000 {
 330                 status = "disabled";
 331
 332                 compatible = "ralink,mt7620-sdhci";
 333                 reg = <0x1e130000 0x4000>;
 334
 335                 interrupt-parent = <&gic>;
 336                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 337
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&sdhci_pins>;
 340         };
 341
 342         xhci: xhci@1e1c0000 {
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345
 346                 compatible = "mediatek,mt8173-xhci";
 347                 reg = <0x1e1c0000 0x1000
 348                        0x1e1d0700 0x0100>;
 349                 reg-names = "mac", "ippc";
 350
 351                 clocks = <&sysc MT7621_CLK_XTAL>;
 352                 clock-names = "sys_ck";
 353
 354                 interrupt-parent = <&gic>;
 355                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 356
 357                 /*
 358                  * Port 1 of both hubs is one usb slot and referenced here.
 359                  * The binding doesn't allow to address individual hubs.
 360                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 361                  */
 362                 xhci_ehci_port1: port@1 {
 363                         reg = <1>;
 364                         #trigger-source-cells = <0>;
 365                 };
 366
 367                 /*
 368                  * Only the second usb hub has a second port. That port serves
 369                  * ehci and ohci.
 370                  */
 371                 ehci_port2: port@2 {
 372                         reg = <2>;
 373                         #trigger-source-cells = <0>;
 374                 };
 375         };
 376
 377         gic: interrupt-controller@1fbc0000 {
 378                 compatible = "mti,gic";
 379                 reg = <0x1fbc0000 0x2000>;
 380
 381                 interrupt-controller;
 382                 #interrupt-cells = <3>;
 383
 384                 mti,reserved-cpu-vectors = <7>;
 385
 386                 timer {
 387                         compatible = "mti,gic-timer";
 388                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 389                         clocks = <&sysc MT7621_CLK_CPU>;
 390                 };
 391         };
 392
 393         cpc: cpc@1fbf0000 {
 394                 compatible = "mti,mips-cpc";
 395                 reg = <0x1fbf0000 0x8000>;
 396         };
 397
 398         mc: mc@1fbf8000 {
 399                 compatible = "mti,mips-cdmm";
 400                 reg = <0x1fbf8000 0x8000>;
 401         };
 402
 403         nand: nand@1e003000 {
 404                 status = "disabled";
 405
 406                 compatible = "mediatek,mt7621-nfc";
 407                 reg = <0x1e003000 0x800
 408                         0x1e003800 0x800>;
 409                 reg-names = "nfi", "ecc";
 410
 411                 clocks = <&sysc MT7621_CLK_NAND>;
 412                 clock-names = "nfi_clk";
 413         };
 414
 415         crypto: crypto@1e004000 {
 416                 compatible = "mediatek,mtk-eip93";
 417                 reg = <0x1e004000 0x1000>;
 418
 419                 interrupt-parent = <&gic>;
 420                 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
 421         };
 422
 423         ethernet: ethernet@1e100000 {
 424                 compatible = "mediatek,mt7621-eth";
 425                 reg = <0x1e100000 0x10000>;
 426
 427                 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
 428                 clock-names = "fe", "ethif";
 429
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432
 433                 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
 434                 reset-names = "fe", "eth";
 435
 436                 interrupt-parent = <&gic>;
 437                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 438
 439                 mediatek,ethsys = <&sysc>;
 440
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
 443
 444                 gmac0: mac@0 {
 445                         compatible = "mediatek,eth-mac";
 446                         reg = <0>;
 447                         phy-mode = "rgmii";
 448
 449                         fixed-link {
 450                                 speed = <1000>;
 451                                 full-duplex;
 452                                 pause;
 453                         };
 454                 };
 455
 456                 gmac1: mac@1 {
 457                         compatible = "mediatek,eth-mac";
 458                         reg = <1>;
 459                         status = "disabled";
 460                         phy-mode = "rgmii";
 461                 };
 462
 463                 mdio: mdio-bus {
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466
 467                         switch0: switch@1f {
 468                                 compatible = "mediatek,mt7621";
 469                                 reg = <0x1f>;
 470                                 mediatek,mcm;
 471                                 resets = <&sysc MT7621_RST_MCM>;
 472                                 reset-names = "mcm";
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <1>;
 475                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 476
 477                                 ports {
 478                                         #address-cells = <1>;
 479                                         #size-cells = <0>;
 480
 481                                         port@0 {
 482                                                 status = "disabled";
 483                                                 reg = <0>;
 484                                                 label = "lan0";
 485                                         };
 486
 487                                         port@1 {
 488                                                 status = "disabled";
 489                                                 reg = <1>;
 490                                                 label = "lan1";
 491                                         };
 492
 493                                         port@2 {
 494                                                 status = "disabled";
 495                                                 reg = <2>;
 496                                                 label = "lan2";
 497                                         };
 498
 499                                         port@3 {
 500                                                 status = "disabled";
 501                                                 reg = <3>;
 502                                                 label = "lan3";
 503                                         };
 504
 505                                         port@4 {
 506                                                 status = "disabled";
 507                                                 reg = <4>;
 508                                                 label = "lan4";
 509                                         };
 510
 511                                         port@6 {
 512                                                 reg = <6>;
 513                                                 ethernet = <&gmac0>;
 514                                                 phy-mode = "rgmii";
 515
 516                                                 fixed-link {
 517                                                         speed = <1000>;
 518                                                         full-duplex;
 519                                                         pause;
 520                                                 };
 521                                         };
 522                                 };
 523                         };
 524                 };
 525         };
 526
 527         pcie: pcie@1e140000 {
 528                 compatible = "mediatek,mt7621-pci";
 529                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 530                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 531                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 532                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 533                 #address-cells = <3>;
 534                 #size-cells = <2>;
 535
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&pcie_pins>;
 538
 539                 device_type = "pci";
 540
 541                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 542                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 543
 544                 status = "disabled";
 545
 546                 #interrupt-cells = <1>;
 547                 interrupt-map-mask = <0xF800 0 0 0>;
 548                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 549                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 550                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 551
 552                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 553
 554                 pcie0: pcie@0,0 {
 555                         reg = <0x0000 0 0 0 0>;
 556                         #address-cells = <3>;
 557                         #size-cells = <2>;
 558                         device_type = "pci";
 559                         ranges;
 560                         #interrupt-cells = <1>;
 561                         interrupt-map-mask = <0 0 0 0>;
 562                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 563                         resets = <&sysc MT7621_RST_PCIE0>;
 564                         clocks = <&sysc MT7621_CLK_PCIE0>;
 565                         phys = <&pcie0_phy 1>;
 566                         phy-names = "pcie-phy0";
 567                 };
 568
 569                 pcie1: pcie@1,0 {
 570                         reg = <0x0800 0 0 0 0>;
 571                         #address-cells = <3>;
 572                         #size-cells = <2>;
 573                         device_type = "pci";
 574                         ranges;
 575                         #interrupt-cells = <1>;
 576                         interrupt-map-mask = <0 0 0 0>;
 577                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 578                         resets = <&sysc MT7621_RST_PCIE1>;
 579                         clocks = <&sysc MT7621_CLK_PCIE1>;
 580                         phys = <&pcie0_phy 1>;
 581                         phy-names = "pcie-phy1";
 582                 };
 583
 584                 pcie2: pcie@2,0 {
 585                         reg = <0x1000 0 0 0 0>;
 586                         #address-cells = <3>;
 587                         #size-cells = <2>;
 588                         device_type = "pci";
 589                         ranges;
 590                         #interrupt-cells = <1>;
 591                         interrupt-map-mask = <0 0 0 0>;
 592                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 593                         resets = <&sysc MT7621_RST_PCIE2>;
 594                         clocks = <&sysc MT7621_CLK_PCIE2>;
 595                         phys = <&pcie2_phy 0>;
 596                         phy-names = "pcie-phy2";
 597                 };
 598         };
 599
 600         pcie0_phy: pcie-phy@1e149000 {
 601                 compatible = "mediatek,mt7621-pci-phy";
 602                 reg = <0x1e149000 0x0700>;
 603                 clocks = <&sysc MT7621_CLK_XTAL>;
 604                 #phy-cells = <1>;
 605         };
 606
 607         pcie2_phy: pcie-phy@1e14a000 {
 608                 compatible = "mediatek,mt7621-pci-phy";
 609                 reg = <0x1e14a000 0x0700>;
 610                 clocks = <&sysc MT7621_CLK_XTAL>;
 611                 #phy-cells = <1>;
 612         };
 613 };