target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

   1 /*
   2  * Ralink RT305x SoC specific setup
   3  *
   4  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  * Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17
  18 #include <asm/mipsregs.h>
  19
  20 #include <asm/mach-ralink/common.h>
  21 #include <asm/mach-ralink/ramips_gpio.h>
  22 #include <asm/mach-ralink/rt305x.h>
  23 #include <asm/mach-ralink/rt305x_regs.h>
  24
  25 void __iomem * rt305x_sysc_base;
  26 void __iomem * rt305x_memc_base;
  27 enum rt305x_soc_type rt305x_soc;
  28
  29 void __init ramips_soc_prom_init(void)
  30 {
  31         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  32         const char *name = "unknown";
  33         u32 n0;
  34         u32 n1;
  35         u32 id;
  36
  37         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  38         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  39
  40         if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
  41                 unsigned long icache_sets;
  42
  43                 icache_sets = (read_c0_config1() >> 22) & 7;
  44                 if (icache_sets == 1) {
  45                         rt305x_soc = RT305X_SOC_RT3050;
  46                         name = "RT3050";
  47                 } else {
  48                         rt305x_soc = RT305X_SOC_RT3052;
  49                         name = "RT3052";
  50                 }
  51         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
  52                 rt305x_soc = RT305X_SOC_RT3352;
  53                 name = "RT3352";
  54         } else {
  55                 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  56         }
  57
  58         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  59
  60         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  61                 "Ralink %s id:%u rev:%u",
  62                 name,
  63                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  64                 (id & CHIP_ID_REV_MASK));
  65
  66         ramips_mem_base = RT305X_SDRAM_BASE;
  67         ramips_mem_size_min = RT305X_MEM_SIZE_MIN;
  68         ramips_mem_size_max = RT305X_MEM_SIZE_MAX;
  69 }
  70
  71 static struct ramips_gpio_chip rt305x_gpio_chips[] = {
  72         {
  73                 .chip = {
  74                         .label  = "RT305X-GPIO0",
  75                         .base   = 0,
  76                         .ngpio  = 24,
  77                 },
  78                 .regs = {
  79                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  80                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  81                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  82                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  83                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  84                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  85                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  86                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  87                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  88                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  89                 },
  90                 .map_base = RT305X_PIO_BASE,
  91                 .map_size = RT305X_PIO_SIZE,
  92         },
  93         {
  94                 .chip = {
  95                         .label  = "RT305X-GPIO1",
  96                         .base   = 24,
  97                         .ngpio  = 16,
  98                 },
  99                 .regs = {
 100                         [RAMIPS_GPIO_REG_INT]   = 0x38,
 101                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
 102                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
 103                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
 104                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
 105                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
 106                         [RAMIPS_GPIO_REG_POL]   = 0x50,
 107                         [RAMIPS_GPIO_REG_SET]   = 0x54,
 108                         [RAMIPS_GPIO_REG_RESET] = 0x58,
 109                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
 110                 },
 111                 .map_base = RT305X_PIO_BASE,
 112                 .map_size = RT305X_PIO_SIZE,
 113         },
 114         {
 115                 .chip = {
 116                         .label  = "RT305X-GPIO2",
 117                         .base   = 40,
 118                         .ngpio  = 12,
 119                 },
 120                 .regs = {
 121                         [RAMIPS_GPIO_REG_INT]   = 0x60,
 122                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
 123                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
 124                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 125                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 126                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 127                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 128                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 129                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 130                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 131                 },
 132                 .map_base = RT305X_PIO_BASE,
 133                 .map_size = RT305X_PIO_SIZE,
 134         },
 135 };
 136
 137 static struct ramips_gpio_data rt305x_gpio_data = {
 138         .chips = rt305x_gpio_chips,
 139         .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
 140 };
 141
 142 static void rt305x_gpio_reserve(int first, int last)
 143 {
 144         for (; first <= last; first++)
 145                 gpio_request(first, "reserved");
 146 }
 147
 148 void __init rt305x_gpio_init(u32 mode)
 149 {
 150         u32 t;
 151
 152         rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 153
 154         ramips_gpio_init(&rt305x_gpio_data);
 155         if ((mode & RT305X_GPIO_MODE_I2C) == 0)
 156                 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
 157
 158         if ((mode & RT305X_GPIO_MODE_SPI) == 0)
 159                 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
 160
 161         t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
 162         t &= RT305X_GPIO_MODE_UART0_MASK;
 163         switch (t) {
 164         case RT305X_GPIO_MODE_UARTF:
 165         case RT305X_GPIO_MODE_PCM_UARTF:
 166         case RT305X_GPIO_MODE_PCM_I2S:
 167         case RT305X_GPIO_MODE_I2S_UARTF:
 168                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
 169                 break;
 170         case RT305X_GPIO_MODE_PCM_GPIO:
 171                 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
 172                 break;
 173         case RT305X_GPIO_MODE_GPIO_UARTF:
 174         case RT305X_GPIO_MODE_GPIO_I2S:
 175                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
 176                 break;
 177         }
 178
 179         if ((mode & RT305X_GPIO_MODE_UART1) == 0)
 180                 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
 181                                     RT305X_GPIO_UART1_RXD);
 182
 183         if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
 184                 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
 185
 186         if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
 187                 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
 188                                     RT305X_GPIO_MDIO_MDIO);
 189
 190         if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
 191                 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
 192                                     RT305X_GPIO_SDRAM_MD31);
 193
 194         if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
 195                 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
 196                                     RT305X_GPIO_GE0_RXCLK);
 197 }