projects / openwrt / staging / wigyori.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ralink: move ethernet driver to files/
[openwrt/staging/wigyori.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 };
83
84 static const u32 *fe_reg_table = fe_reg_table_default;
85
86 static void __iomem *fe_base = 0;
87
88 void fe_w32(u32 val, unsigned reg)
89 {
90 __raw_writel(val, fe_base + reg);
91 }
92
93 u32 fe_r32(unsigned reg)
94 {
95 return __raw_readl(fe_base + reg);
96 }
97
98 void fe_reg_w32(u32 val, enum fe_reg reg)
99 {
100 fe_w32(val, fe_reg_table[reg]);
101 }
102
103 u32 fe_reg_r32(enum fe_reg reg)
104 {
105 return fe_r32(fe_reg_table[reg]);
106 }
107
108 static inline void fe_int_disable(u32 mask)
109 {
110 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
111 FE_REG_FE_INT_ENABLE);
112 /* flush write */
113 fe_reg_r32(FE_REG_FE_INT_ENABLE);
114 }
115
116 static inline void fe_int_enable(u32 mask)
117 {
118 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
119 FE_REG_FE_INT_ENABLE);
120 /* flush write */
121 fe_reg_r32(FE_REG_FE_INT_ENABLE);
122 }
123
124 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
125 {
126 unsigned long flags;
127
128 spin_lock_irqsave(&priv->page_lock, flags);
129 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
130 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
131 FE_GDMA1_MAC_ADRL);
132 spin_unlock_irqrestore(&priv->page_lock, flags);
133 }
134
135 static int fe_set_mac_address(struct net_device *dev, void *p)
136 {
137 int ret = eth_mac_addr(dev, p);
138
139 if (!ret) {
140 struct fe_priv *priv = netdev_priv(dev);
141
142 if (priv->soc->set_mac)
143 priv->soc->set_mac(priv, dev->dev_addr);
144 else
145 fe_hw_set_macaddr(priv, p);
146 }
147
148 return ret;
149 }
150
151 static inline int fe_max_frag_size(int mtu)
152 {
153 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
154 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
155 }
156
157 static inline int fe_max_buf_size(int frag_size)
158 {
159 return frag_size - FE_RX_HLEN -
160 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
161 }
162
163 static void fe_clean_rx(struct fe_priv *priv)
164 {
165 int i;
166
167 if (priv->rx_data) {
168 for (i = 0; i < NUM_DMA_DESC; i++)
169 if (priv->rx_data[i]) {
170 if (priv->rx_dma && priv->rx_dma[i].rxd1)
171 dma_unmap_single(&priv->netdev->dev,
172 priv->rx_dma[i].rxd1,
173 priv->rx_buf_size,
174 DMA_FROM_DEVICE);
175 put_page(virt_to_head_page(priv->rx_data[i]));
176 }
177
178 kfree(priv->rx_data);
179 priv->rx_data = NULL;
180 }
181
182 if (priv->rx_dma) {
183 dma_free_coherent(&priv->netdev->dev,
184 NUM_DMA_DESC * sizeof(*priv->rx_dma),
185 priv->rx_dma,
186 priv->rx_phys);
187 priv->rx_dma = NULL;
188 }
189 }
190
191 static int fe_alloc_rx(struct fe_priv *priv)
192 {
193 struct net_device *netdev = priv->netdev;
194 int i;
195
196 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
197 GFP_KERNEL);
198 if (!priv->rx_data)
199 goto no_rx_mem;
200
201 for (i = 0; i < NUM_DMA_DESC; i++) {
202 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
203 if (!priv->rx_data[i])
204 goto no_rx_mem;
205 }
206
207 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
208 NUM_DMA_DESC * sizeof(*priv->rx_dma),
209 &priv->rx_phys,
210 GFP_ATOMIC | __GFP_ZERO);
211 if (!priv->rx_dma)
212 goto no_rx_mem;
213
214 for (i = 0; i < NUM_DMA_DESC; i++) {
215 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
216 priv->rx_data[i] + FE_RX_OFFSET,
217 priv->rx_buf_size,
218 DMA_FROM_DEVICE);
219 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
220 goto no_rx_mem;
221 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
222
223 if (priv->soc->rx_dma)
224 priv->soc->rx_dma(priv, i, priv->rx_buf_size);
225 else
226 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
227 }
228 wmb();
229
230 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
231 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
232 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
233 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
234
235 return 0;
236
237 no_rx_mem:
238 return -ENOMEM;
239 }
240
241 static void fe_clean_tx(struct fe_priv *priv)
242 {
243 int i;
244
245 if (priv->tx_skb) {
246 for (i = 0; i < NUM_DMA_DESC; i++) {
247 if (priv->tx_skb[i])
248 dev_kfree_skb_any(priv->tx_skb[i]);
249 }
250 kfree(priv->tx_skb);
251 priv->tx_skb = NULL;
252 }
253
254 if (priv->tx_dma) {
255 dma_free_coherent(&priv->netdev->dev,
256 NUM_DMA_DESC * sizeof(*priv->tx_dma),
257 priv->tx_dma,
258 priv->tx_phys);
259 priv->tx_dma = NULL;
260 }
261 }
262
263 static int fe_alloc_tx(struct fe_priv *priv)
264 {
265 int i;
266
267 priv->tx_free_idx = 0;
268
269 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
270 GFP_KERNEL);
271 if (!priv->tx_skb)
272 goto no_tx_mem;
273
274 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
275 NUM_DMA_DESC * sizeof(*priv->tx_dma),
276 &priv->tx_phys,
277 GFP_ATOMIC | __GFP_ZERO);
278 if (!priv->tx_dma)
279 goto no_tx_mem;
280
281 for (i = 0; i < NUM_DMA_DESC; i++) {
282 if (priv->soc->tx_dma) {
283 priv->soc->tx_dma(priv, i, NULL);
284 continue;
285 }
286 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
287 }
288 wmb();
289
290 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
291 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
292 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
293 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
294
295 return 0;
296
297 no_tx_mem:
298 return -ENOMEM;
299 }
300
301 static int fe_init_dma(struct fe_priv *priv)
302 {
303 int err;
304
305 err = fe_alloc_tx(priv);
306 if (err)
307 return err;
308
309 err = fe_alloc_rx(priv);
310 if (err)
311 return err;
312
313 return 0;
314 }
315
316 static void fe_free_dma(struct fe_priv *priv)
317 {
318 fe_clean_tx(priv);
319 fe_clean_rx(priv);
320
321 netdev_reset_queue(priv->netdev);
322 }
323
324 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
325 {
326 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
327 dma_unmap_single(dev, txd->txd1,
328 TX_DMA_GET_PLEN0(txd->txd2),
329 DMA_TO_DEVICE);
330 }
331
332 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
333 {
334 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
335 dma_unmap_page(dev, txd->txd1,
336 TX_DMA_GET_PLEN0(txd->txd2),
337 DMA_TO_DEVICE);
338 }
339
340 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
341 {
342 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
343 dma_unmap_page(dev, txd->txd3,
344 TX_DMA_GET_PLEN1(txd->txd2),
345 DMA_TO_DEVICE);
346 }
347
348 void fe_stats_update(struct fe_priv *priv)
349 {
350 struct fe_hw_stats *hwstats = priv->hw_stats;
351 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
352
353 u64_stats_update_begin(&hwstats->syncp);
354
355 hwstats->tx_bytes += fe_r32(base);
356 hwstats->tx_packets += fe_r32(base + 0x04);
357 hwstats->tx_skip += fe_r32(base + 0x08);
358 hwstats->tx_collisions += fe_r32(base + 0x0c);
359 hwstats->rx_bytes += fe_r32(base + 0x20);
360 hwstats->rx_packets += fe_r32(base + 0x24);
361 hwstats->rx_overflow += fe_r32(base + 0x28);
362 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
363 hwstats->rx_short_errors += fe_r32(base + 0x30);
364 hwstats->rx_long_errors += fe_r32(base + 0x34);
365 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
366 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
367
368 u64_stats_update_end(&hwstats->syncp);
369 }
370
371 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
372 struct rtnl_link_stats64 *storage)
373 {
374 struct fe_priv *priv = netdev_priv(dev);
375 struct fe_hw_stats *hwstats = priv->hw_stats;
376 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
377 unsigned int start;
378
379 if (!base) {
380 netdev_stats_to_stats64(storage, &dev->stats);
381 return storage;
382 }
383
384 if (netif_running(dev) && netif_device_present(dev)) {
385 if (spin_trylock(&hwstats->stats_lock)) {
386 fe_stats_update(priv);
387 spin_unlock(&hwstats->stats_lock);
388 }
389 }
390
391 do {
392 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
393 storage->rx_packets = hwstats->rx_packets;
394 storage->tx_packets = hwstats->tx_packets;
395 storage->rx_bytes = hwstats->rx_bytes;
396 storage->tx_bytes = hwstats->tx_bytes;
397 storage->collisions = hwstats->tx_collisions;
398 storage->rx_length_errors = hwstats->rx_short_errors +
399 hwstats->rx_long_errors;
400 storage->rx_over_errors = hwstats->rx_overflow;
401 storage->rx_crc_errors = hwstats->rx_fcs_errors;
402 storage->rx_errors = hwstats->rx_checksum_errors;
403 storage->tx_aborted_errors = hwstats->tx_skip;
404 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
405
406 storage->tx_errors = priv->netdev->stats.tx_errors;
407 storage->rx_dropped = priv->netdev->stats.rx_dropped;
408 storage->tx_dropped = priv->netdev->stats.tx_dropped;
409
410 return storage;
411 }
412
413 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
414 int idx)
415 {
416 struct fe_priv *priv = netdev_priv(dev);
417 struct skb_frag_struct *frag;
418 struct fe_tx_dma *txd;
419 dma_addr_t mapped_addr;
420 unsigned int nr_frags;
421 u32 def_txd4, txd2;
422 int i, j, unmap_idx, tx_num;
423
424 txd = &priv->tx_dma[idx];
425 nr_frags = skb_shinfo(skb)->nr_frags;
426 tx_num = 1 + (nr_frags >> 1);
427
428 /* init tx descriptor */
429 if (priv->soc->tx_dma)
430 priv->soc->tx_dma(priv, idx, skb);
431 else
432 txd->txd4 = TX_DMA_DESP4_DEF;
433 def_txd4 = txd->txd4;
434
435 /* use dma_unmap_single to free it */
436 txd->txd4 |= priv->soc->tx_udf_bit;
437
438 /* TX Checksum offload */
439 if (skb->ip_summed == CHECKSUM_PARTIAL)
440 txd->txd4 |= TX_DMA_CHKSUM;
441
442 /* VLAN header offload */
443 if (vlan_tx_tag_present(skb)) {
444 txd->txd4 |= TX_DMA_INS_VLAN |
445 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
446 (vlan_tx_tag_get(skb) & 0xF);
447 }
448
449 /* TSO: fill MSS info in tcp checksum field */
450 if (skb_is_gso(skb)) {
451 if (skb_cow_head(skb, 0)) {
452 netif_warn(priv, tx_err, dev,
453 "GSO expand head fail.\n");
454 goto err_out;
455 }
456 if (skb_shinfo(skb)->gso_type &
457 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
458 txd->txd4 |= TX_DMA_TSO;
459 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
460 }
461 }
462
463 mapped_addr = dma_map_single(&dev->dev, skb->data,
464 skb_headlen(skb), DMA_TO_DEVICE);
465 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
466 goto err_out;
467 txd->txd1 = mapped_addr;
468 txd2 = TX_DMA_PLEN0(skb_headlen(skb));
469
470 /* TX SG offload */
471 j = idx;
472 for (i = 0; i < nr_frags; i++) {
473
474 frag = &skb_shinfo(skb)->frags[i];
475 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
476 skb_frag_size(frag), DMA_TO_DEVICE);
477 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
478 goto err_dma;
479
480 if (i & 0x1) {
481 j = NEXT_TX_DESP_IDX(j);
482 txd = &priv->tx_dma[j];
483 txd->txd1 = mapped_addr;
484 txd2 = TX_DMA_PLEN0(frag->size);
485 txd->txd4 = def_txd4;
486 } else {
487 txd->txd3 = mapped_addr;
488 txd2 |= TX_DMA_PLEN1(frag->size);
489 if (i != (nr_frags -1))
490 txd->txd2 = txd2;
491 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
492 }
493 }
494
495 /* set last segment */
496 if (nr_frags & 0x1)
497 txd->txd2 = (txd2 | TX_DMA_LS1);
498 else
499 txd->txd2 = (txd2 | TX_DMA_LS0);
500
501 /* store skb to cleanup */
502 priv->tx_skb[j] = skb;
503
504 wmb();
505 j = NEXT_TX_DESP_IDX(j);
506 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
507
508 return 0;
509
510 err_dma:
511 /* unmap dma */
512 txd = &priv->tx_dma[idx];
513 txd_unmap_single(&dev->dev, txd);
514
515 j = idx;
516 unmap_idx = i;
517 for (i = 0; i < unmap_idx; i++) {
518 if (i & 0x1) {
519 j = NEXT_TX_DESP_IDX(j);
520 txd = &priv->tx_dma[j];
521 txd_unmap_page0(&dev->dev, txd);
522 } else {
523 txd_unmap_page1(&dev->dev, txd);
524 }
525 }
526
527 err_out:
528 /* reinit descriptors and skb */
529 j = idx;
530 for (i = 0; i < tx_num; i++) {
531 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
532 priv->tx_skb[j] = NULL;
533 j = NEXT_TX_DESP_IDX(j);
534 }
535 wmb();
536
537 return -1;
538 }
539
540 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
541 unsigned int len;
542 int ret;
543
544 ret = 0;
545 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
546 if ((priv->flags & FE_FLAG_PADDING_64B) &&
547 !(priv->flags & FE_FLAG_PADDING_BUG))
548 return ret;
549
550 if (vlan_tx_tag_present(skb))
551 len = ETH_ZLEN;
552 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
553 len = VLAN_ETH_ZLEN;
554 else if(!(priv->flags & FE_FLAG_PADDING_64B))
555 len = ETH_ZLEN;
556 else
557 return ret;
558
559 if (skb->len < len) {
560 if ((ret = skb_pad(skb, len - skb->len)) < 0)
561 return ret;
562 skb->len = len;
563 skb_set_tail_pointer(skb, len);
564 }
565 }
566
567 return ret;
568 }
569
570 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
571 {
572 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
573 (NUM_DMA_DESC - 1)));
574 }
575
576 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
577 {
578 struct fe_priv *priv = netdev_priv(dev);
579 struct net_device_stats *stats = &dev->stats;
580 u32 tx;
581 int tx_num;
582
583 if (fe_skb_padto(skb, priv)) {
584 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
585 return NETDEV_TX_OK;
586 }
587
588 spin_lock(&priv->page_lock);
589 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
590 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
591 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
592 {
593 netif_stop_queue(dev);
594 spin_unlock(&priv->page_lock);
595 netif_err(priv, tx_queued,dev,
596 "Tx Ring full when queue awake!\n");
597 return NETDEV_TX_BUSY;
598 }
599
600 if (fe_tx_map_dma(skb, dev, tx) < 0) {
601 kfree_skb(skb);
602
603 stats->tx_dropped++;
604 } else {
605 netdev_sent_queue(dev, skb->len);
606 skb_tx_timestamp(skb);
607
608 stats->tx_packets++;
609 stats->tx_bytes += skb->len;
610 }
611
612 spin_unlock(&priv->page_lock);
613
614 return NETDEV_TX_OK;
615 }
616
617 static inline void fe_rx_vlan(struct sk_buff *skb)
618 {
619 struct ethhdr *ehdr;
620 u16 vlanid;
621
622 if (!__vlan_get_tag(skb, &vlanid)) {
623 /* pop the vlan tag */
624 ehdr = (struct ethhdr *)skb->data;
625 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
626 skb_pull(skb, VLAN_HLEN);
627 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
628 }
629 }
630
631 static int fe_poll_rx(struct napi_struct *napi, int budget,
632 struct fe_priv *priv)
633 {
634 struct net_device *netdev = priv->netdev;
635 struct net_device_stats *stats = &netdev->stats;
636 struct fe_soc_data *soc = priv->soc;
637 u32 checksum_bit;
638 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
639 struct sk_buff *skb;
640 u8 *data, *new_data;
641 struct fe_rx_dma *rxd;
642 int done = 0;
643 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
644
645 if (netdev->features & NETIF_F_RXCSUM)
646 checksum_bit = soc->checksum_bit;
647 else
648 checksum_bit = 0;
649
650 while (done < budget) {
651 unsigned int pktlen;
652 dma_addr_t dma_addr;
653 idx = NEXT_RX_DESP_IDX(idx);
654 rxd = &priv->rx_dma[idx];
655 data = priv->rx_data[idx];
656
657 if (!(rxd->rxd2 & RX_DMA_DONE))
658 break;
659
660 /* alloc new buffer */
661 new_data = netdev_alloc_frag(priv->frag_size);
662 if (unlikely(!new_data)) {
663 stats->rx_dropped++;
664 goto release_desc;
665 }
666 dma_addr = dma_map_single(&netdev->dev,
667 new_data + FE_RX_OFFSET,
668 priv->rx_buf_size,
669 DMA_FROM_DEVICE);
670 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
671 put_page(virt_to_head_page(new_data));
672 goto release_desc;
673 }
674
675 /* receive data */
676 skb = build_skb(data, priv->frag_size);
677 if (unlikely(!skb)) {
678 put_page(virt_to_head_page(new_data));
679 goto release_desc;
680 }
681 skb_reserve(skb, FE_RX_OFFSET);
682
683 dma_unmap_single(&netdev->dev, rxd->rxd1,
684 priv->rx_buf_size, DMA_FROM_DEVICE);
685 pktlen = RX_DMA_PLEN0(rxd->rxd2);
686 skb_put(skb, pktlen);
687 skb->dev = netdev;
688 if (rxd->rxd4 & checksum_bit) {
689 skb->ip_summed = CHECKSUM_UNNECESSARY;
690 } else {
691 skb_checksum_none_assert(skb);
692 }
693 if (rx_vlan)
694 fe_rx_vlan(skb);
695 skb->protocol = eth_type_trans(skb, netdev);
696
697 stats->rx_packets++;
698 stats->rx_bytes += pktlen;
699
700 napi_gro_receive(napi, skb);
701
702 priv->rx_data[idx] = new_data;
703 rxd->rxd1 = (unsigned int) dma_addr;
704
705 release_desc:
706 if (soc->rx_dma)
707 soc->rx_dma(priv, idx, priv->rx_buf_size);
708 else
709 rxd->rxd2 = RX_DMA_LSO;
710
711 wmb();
712 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
713 done++;
714 }
715
716 return done;
717 }
718
719 static int fe_poll_tx(struct fe_priv *priv, int budget)
720 {
721 struct net_device *netdev = priv->netdev;
722 struct device *dev = &netdev->dev;
723 unsigned int bytes_compl = 0;
724 struct sk_buff *skb;
725 struct fe_tx_dma *txd;
726 int done = 0, idx;
727 u32 udf_bit = priv->soc->tx_udf_bit;
728
729 idx = priv->tx_free_idx;
730 while (done < budget) {
731 txd = &priv->tx_dma[idx];
732 skb = priv->tx_skb[idx];
733
734 if (!(txd->txd2 & TX_DMA_DONE) || !skb)
735 break;
736
737 txd_unmap_page1(dev, txd);
738
739 if (txd->txd4 & udf_bit)
740 txd_unmap_single(dev, txd);
741 else
742 txd_unmap_page0(dev, txd);
743
744 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
745 bytes_compl += skb->len;
746 dev_kfree_skb_any(skb);
747 done++;
748 }
749 priv->tx_skb[idx] = NULL;
750 idx = NEXT_TX_DESP_IDX(idx);
751 }
752 priv->tx_free_idx = idx;
753
754 if (!done)
755 return 0;
756
757 netdev_completed_queue(netdev, done, bytes_compl);
758 if (unlikely(netif_queue_stopped(netdev) &&
759 netif_carrier_ok(netdev))) {
760 netif_wake_queue(netdev);
761 }
762
763 return done;
764 }
765
766 static int fe_poll(struct napi_struct *napi, int budget)
767 {
768 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
769 struct fe_hw_stats *hwstat = priv->hw_stats;
770 int tx_done, rx_done;
771 u32 status, mask;
772 u32 tx_intr, rx_intr;
773
774 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
775 tx_intr = priv->soc->tx_dly_int;
776 rx_intr = priv->soc->rx_dly_int;
777 tx_done = rx_done = 0;
778
779 poll_again:
780 if (status & tx_intr) {
781 tx_done += fe_poll_tx(priv, budget - tx_done);
782 if (tx_done < budget) {
783 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
784 }
785 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
786 }
787
788 if (status & rx_intr) {
789 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
790 if (rx_done < budget) {
791 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
792 }
793 }
794
795 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
796 if (spin_trylock(&hwstat->stats_lock)) {
797 fe_stats_update(priv);
798 spin_unlock(&hwstat->stats_lock);
799 }
800 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
801 }
802
803 if (unlikely(netif_msg_intr(priv))) {
804 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
805 netdev_info(priv->netdev,
806 "done tx %d, rx %d, intr 0x%x/0x%x\n",
807 tx_done, rx_done, status, mask);
808 }
809
810 if ((tx_done < budget) && (rx_done < budget)) {
811 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
812 if (status & (tx_intr | rx_intr )) {
813 goto poll_again;
814 }
815 napi_complete(napi);
816 fe_int_enable(tx_intr | rx_intr);
817 }
818
819 return rx_done;
820 }
821
822 static void fe_tx_timeout(struct net_device *dev)
823 {
824 struct fe_priv *priv = netdev_priv(dev);
825
826 priv->netdev->stats.tx_errors++;
827 netif_err(priv, tx_err, dev,
828 "transmit timed out, waking up the queue\n");
829 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
830 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
831 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
832 fe_reg_r32(FE_REG_TX_CTX_IDX0),
833 fe_reg_r32(FE_REG_RX_CALC_IDX0));
834 netif_wake_queue(dev);
835 }
836
837 static irqreturn_t fe_handle_irq(int irq, void *dev)
838 {
839 struct fe_priv *priv = netdev_priv(dev);
840 u32 status, dly_int;
841
842 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
843
844 if (unlikely(!status))
845 return IRQ_NONE;
846
847 dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
848 if (likely(status & dly_int)) {
849 fe_int_disable(dly_int);
850 napi_schedule(&priv->rx_napi);
851 } else {
852 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
853 }
854
855 return IRQ_HANDLED;
856 }
857
858 int fe_set_clock_cycle(struct fe_priv *priv)
859 {
860 unsigned long sysclk = priv->sysclk;
861
862 if (!sysclk) {
863 return -EINVAL;
864 }
865
866 sysclk /= FE_US_CYC_CNT_DIVISOR;
867 sysclk <<= FE_US_CYC_CNT_SHIFT;
868
869 fe_w32((fe_r32(FE_FE_GLO_CFG) &
870 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
871 sysclk,
872 FE_FE_GLO_CFG);
873 return 0;
874 }
875
876 void fe_fwd_config(struct fe_priv *priv)
877 {
878 u32 fwd_cfg;
879
880 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
881
882 /* disable jumbo frame */
883 if (priv->flags & FE_FLAG_JUMBO_FRAME)
884 fwd_cfg &= ~FE_GDM1_JMB_EN;
885
886 /* set unicast/multicast/broadcast frame to cpu */
887 fwd_cfg &= ~0xffff;
888
889 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
890 }
891
892 static void fe_rxcsum_config(bool enable)
893 {
894 if (enable)
895 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
896 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
897 FE_GDMA1_FWD_CFG);
898 else
899 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
900 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
901 FE_GDMA1_FWD_CFG);
902 }
903
904 static void fe_txcsum_config(bool enable)
905 {
906 if (enable)
907 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
908 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
909 FE_CDMA_CSG_CFG);
910 else
911 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
912 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
913 FE_CDMA_CSG_CFG);
914 }
915
916 void fe_csum_config(struct fe_priv *priv)
917 {
918 struct net_device *dev = priv_netdev(priv);
919
920 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
921 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
922 }
923
924 static int fe_hw_init(struct net_device *dev)
925 {
926 struct fe_priv *priv = netdev_priv(dev);
927 int i, err;
928
929 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
930 dev_name(priv->device), dev);
931 if (err)
932 return err;
933
934 if (priv->soc->set_mac)
935 priv->soc->set_mac(priv, dev->dev_addr);
936 else
937 fe_hw_set_macaddr(priv, dev->dev_addr);
938
939 fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
940
941 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
942
943 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
944 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
945 for (i = 0; i < 16; i += 2)
946 fe_w32(((i + 1) << 16) + i,
947 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
948 (i * 2));
949
950 BUG_ON(!priv->soc->fwd_config);
951 if (priv->soc->fwd_config(priv))
952 netdev_err(dev, "unable to get clock\n");
953
954 fe_w32(1, FE_FE_RST_GL);
955 fe_w32(0, FE_FE_RST_GL);
956
957 return 0;
958 }
959
960 static int fe_open(struct net_device *dev)
961 {
962 struct fe_priv *priv = netdev_priv(dev);
963 unsigned long flags;
964 u32 val;
965 int err;
966
967 err = fe_init_dma(priv);
968 if (err)
969 goto err_out;
970
971 spin_lock_irqsave(&priv->page_lock, flags);
972 napi_enable(&priv->rx_napi);
973
974 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
975 val |= priv->soc->pdma_glo_cfg;
976 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
977
978 spin_unlock_irqrestore(&priv->page_lock, flags);
979
980 if (priv->phy)
981 priv->phy->start(priv);
982
983 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
984 netif_carrier_on(dev);
985
986 netif_start_queue(dev);
987 fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
988
989 return 0;
990
991 err_out:
992 fe_free_dma(priv);
993 return err;
994 }
995
996 static int fe_stop(struct net_device *dev)
997 {
998 struct fe_priv *priv = netdev_priv(dev);
999 unsigned long flags;
1000 int i;
1001
1002 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1003
1004 netif_tx_disable(dev);
1005
1006 if (priv->phy)
1007 priv->phy->stop(priv);
1008
1009 spin_lock_irqsave(&priv->page_lock, flags);
1010 napi_disable(&priv->rx_napi);
1011
1012 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1013 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1014 FE_REG_PDMA_GLO_CFG);
1015 spin_unlock_irqrestore(&priv->page_lock, flags);
1016
1017 /* wait dma stop */
1018 for (i = 0; i < 10; i++) {
1019 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1020 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1021 msleep(10);
1022 continue;
1023 }
1024 break;
1025 }
1026
1027 fe_free_dma(priv);
1028
1029 return 0;
1030 }
1031
1032 static int __init fe_init(struct net_device *dev)
1033 {
1034 struct fe_priv *priv = netdev_priv(dev);
1035 struct device_node *port;
1036 int err;
1037
1038 BUG_ON(!priv->soc->reset_fe);
1039 priv->soc->reset_fe();
1040
1041 if (priv->soc->switch_init)
1042 priv->soc->switch_init(priv);
1043
1044 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1045 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1046
1047 err = fe_mdio_init(priv);
1048 if (err)
1049 return err;
1050
1051 if (priv->soc->port_init)
1052 for_each_child_of_node(priv->device->of_node, port)
1053 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1054 priv->soc->port_init(priv, port);
1055
1056 if (priv->phy) {
1057 err = priv->phy->connect(priv);
1058 if (err)
1059 goto err_phy_disconnect;
1060 }
1061
1062 err = fe_hw_init(dev);
1063 if (err)
1064 goto err_phy_disconnect;
1065
1066 if (priv->soc->switch_config)
1067 priv->soc->switch_config(priv);
1068
1069 return 0;
1070
1071 err_phy_disconnect:
1072 if (priv->phy)
1073 priv->phy->disconnect(priv);
1074 fe_mdio_cleanup(priv);
1075
1076 return err;
1077 }
1078
1079 static void fe_uninit(struct net_device *dev)
1080 {
1081 struct fe_priv *priv = netdev_priv(dev);
1082
1083 if (priv->phy)
1084 priv->phy->disconnect(priv);
1085 fe_mdio_cleanup(priv);
1086
1087 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1088 free_irq(dev->irq, dev);
1089 }
1090
1091 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1092 {
1093 struct fe_priv *priv = netdev_priv(dev);
1094
1095 if (!priv->phy_dev)
1096 return -ENODEV;
1097
1098 switch (cmd) {
1099 case SIOCETHTOOL:
1100 return phy_ethtool_ioctl(priv->phy_dev,
1101 (void *) ifr->ifr_data);
1102 case SIOCGMIIPHY:
1103 case SIOCGMIIREG:
1104 case SIOCSMIIREG:
1105 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1106 default:
1107 break;
1108 }
1109
1110 return -EOPNOTSUPP;
1111 }
1112
1113 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1114 {
1115 struct fe_priv *priv = netdev_priv(dev);
1116 int frag_size, old_mtu;
1117 u32 fwd_cfg;
1118
1119 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1120 return eth_change_mtu(dev, new_mtu);
1121
1122 frag_size = fe_max_frag_size(new_mtu);
1123 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1124 return -EINVAL;
1125
1126 old_mtu = dev->mtu;
1127 dev->mtu = new_mtu;
1128
1129 /* return early if the buffer sizes will not change */
1130 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1131 return 0;
1132 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1133 return 0;
1134
1135 if (new_mtu <= ETH_DATA_LEN) {
1136 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1137 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1138 } else {
1139 priv->frag_size = PAGE_SIZE;
1140 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1141 }
1142
1143 if (!netif_running(dev))
1144 return 0;
1145
1146 fe_stop(dev);
1147 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1148 if (new_mtu <= ETH_DATA_LEN)
1149 fwd_cfg &= ~FE_GDM1_JMB_EN;
1150 else {
1151 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1152 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1153 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1154 }
1155 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1156
1157 return fe_open(dev);
1158 }
1159
1160 static const struct net_device_ops fe_netdev_ops = {
1161 .ndo_init = fe_init,
1162 .ndo_uninit = fe_uninit,
1163 .ndo_open = fe_open,
1164 .ndo_stop = fe_stop,
1165 .ndo_start_xmit = fe_start_xmit,
1166 .ndo_set_mac_address = fe_set_mac_address,
1167 .ndo_validate_addr = eth_validate_addr,
1168 .ndo_do_ioctl = fe_do_ioctl,
1169 .ndo_change_mtu = fe_change_mtu,
1170 .ndo_tx_timeout = fe_tx_timeout,
1171 .ndo_get_stats64 = fe_get_stats64,
1172 };
1173
1174 static int fe_probe(struct platform_device *pdev)
1175 {
1176 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177 const struct of_device_id *match;
1178 struct fe_soc_data *soc;
1179 struct net_device *netdev;
1180 struct fe_priv *priv;
1181 struct clk *sysclk;
1182 int err;
1183
1184 device_reset(&pdev->dev);
1185
1186 match = of_match_device(of_fe_match, &pdev->dev);
1187 soc = (struct fe_soc_data *) match->data;
1188
1189 if (soc->reg_table)
1190 fe_reg_table = soc->reg_table;
1191 else
1192 soc->reg_table = fe_reg_table;
1193
1194 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1195 if (!fe_base) {
1196 err = -EADDRNOTAVAIL;
1197 goto err_out;
1198 }
1199
1200 netdev = alloc_etherdev(sizeof(*priv));
1201 if (!netdev) {
1202 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1203 err = -ENOMEM;
1204 goto err_iounmap;
1205 }
1206
1207 SET_NETDEV_DEV(netdev, &pdev->dev);
1208 netdev->netdev_ops = &fe_netdev_ops;
1209 netdev->base_addr = (unsigned long) fe_base;
1210 netdev->watchdog_timeo = TX_TIMEOUT;
1211
1212 netdev->irq = platform_get_irq(pdev, 0);
1213 if (netdev->irq < 0) {
1214 dev_err(&pdev->dev, "no IRQ resource found\n");
1215 err = -ENXIO;
1216 goto err_free_dev;
1217 }
1218
1219 if (soc->init_data)
1220 soc->init_data(soc, netdev);
1221 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1222 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1223 netdev->vlan_features = netdev->hw_features &
1224 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1225 netdev->features |= netdev->hw_features;
1226
1227 priv = netdev_priv(netdev);
1228 spin_lock_init(&priv->page_lock);
1229 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1230 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1231 if (!priv->hw_stats) {
1232 err = -ENOMEM;
1233 goto err_free_dev;
1234 }
1235 spin_lock_init(&priv->hw_stats->stats_lock);
1236 }
1237
1238 sysclk = devm_clk_get(&pdev->dev, NULL);
1239 if (!IS_ERR(sysclk))
1240 priv->sysclk = clk_get_rate(sysclk);
1241
1242 priv->netdev = netdev;
1243 priv->device = &pdev->dev;
1244 priv->soc = soc;
1245 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1246 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1247 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1248 if (priv->frag_size > PAGE_SIZE) {
1249 dev_err(&pdev->dev, "error frag size.\n");
1250 err = -EINVAL;
1251 goto err_free_dev;
1252 }
1253
1254 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1255 fe_set_ethtool_ops(netdev);
1256
1257 err = register_netdev(netdev);
1258 if (err) {
1259 dev_err(&pdev->dev, "error bringing up device\n");
1260 goto err_free_dev;
1261 }
1262
1263 platform_set_drvdata(pdev, netdev);
1264
1265 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1266 netdev->base_addr, netdev->irq);
1267
1268 return 0;
1269
1270 err_free_dev:
1271 free_netdev(netdev);
1272 err_iounmap:
1273 devm_iounmap(&pdev->dev, fe_base);
1274 err_out:
1275 return err;
1276 }
1277
1278 static int fe_remove(struct platform_device *pdev)
1279 {
1280 struct net_device *dev = platform_get_drvdata(pdev);
1281 struct fe_priv *priv = netdev_priv(dev);
1282
1283 netif_napi_del(&priv->rx_napi);
1284 if (priv->hw_stats)
1285 kfree(priv->hw_stats);
1286
1287 unregister_netdev(dev);
1288 free_netdev(dev);
1289 platform_set_drvdata(pdev, NULL);
1290
1291 return 0;
1292 }
1293
1294 static struct platform_driver fe_driver = {
1295 .probe = fe_probe,
1296 .remove = fe_remove,
1297 .driver = {
1298 .name = "ralink_soc_eth",
1299 .owner = THIS_MODULE,
1300 .of_match_table = of_fe_match,
1301 },
1302 };
1303
1304 static int __init init_rtfe(void)
1305 {
1306 int ret;
1307
1308 ret = rtesw_init();
1309 if (ret)
1310 return ret;
1311
1312 ret = platform_driver_register(&fe_driver);
1313 if (ret)
1314 rtesw_exit();
1315
1316 return ret;
1317 }
1318
1319 static void __exit exit_rtfe(void)
1320 {
1321 platform_driver_unregister(&fe_driver);
1322 rtesw_exit();
1323 }
1324
1325 module_init(init_rtfe);
1326 module_exit(exit_rtfe);
1327
1328 MODULE_LICENSE("GPL");
1329 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1330 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1331 MODULE_VERSION(FE_DRV_VERSION);
Staging tree of Zoltan Herpai