target/linux/ramips/files/drivers/usb/host/mtk-phy.c

   1 #include <linux/gfp.h>
   2 #include <linux/kernel.h>
   3 #include <linux/slab.h>
   4 #define U3_PHY_LIB
   5 #include "mtk-phy.h"
   6 #ifdef CONFIG_PROJECT_7621
   7 #include "mtk-phy-7621.h"
   8 #endif
   9 #ifdef CONFIG_PROJECT_PHY
  10 static struct u3phy_operator project_operators = {
  11         .init = phy_init,
  12         .change_pipe_phase = phy_change_pipe_phase,
  13         .eyescan_init = eyescan_init,
  14         .eyescan = phy_eyescan,
  15         .u2_slew_rate_calibration = u2_slew_rate_calibration,
  16 };
  17 #endif
  18
  19
  20 PHY_INT32 u3phy_init(){
  21 #ifndef CONFIG_PROJECT_PHY
  22         PHY_INT32 u3phy_version;
  23 #endif
  24
  25         if(u3phy != NULL){
  26                 return PHY_TRUE;
  27         }
  28
  29         u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
  30 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
  31         u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
  32 #endif
  33 #ifdef CONFIG_U3_PHY_GPIO_SUPPORT
  34         u3phy->phyd_version_addr = 0x2000e4;
  35 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
  36         u3phy_p1->phyd_version_addr = 0x2000e4;
  37 #endif
  38 #else
  39         u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
  40 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
  41         u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
  42 #endif
  43 #endif
  44
  45 #ifdef CONFIG_PROJECT_PHY
  46
  47         u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
  48         u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
  49         u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
  50         u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
  51         u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
  52         u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
  53         u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
  54         u3phy_ops = &project_operators;
  55
  56 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
  57         u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
  58         u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
  59         u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
  60         u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
  61         u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
  62         u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
  63         u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
  64 #endif
  65 #endif
  66
  67         return PHY_TRUE;
  68 }
  69
  70 PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
  71         PHY_INT8 cur_value;
  72         PHY_INT8 new_value;
  73
  74         cur_value = U3PhyReadReg8(addr);
  75         new_value = (cur_value & (~mask)) | (value << offset);
  76         //udelay(i2cdelayus);
  77         U3PhyWriteReg8(addr, new_value);
  78         return PHY_TRUE;
  79 }
  80
  81 PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
  82         PHY_INT32 cur_value;
  83         PHY_INT32 new_value;
  84
  85         cur_value = U3PhyReadReg32(addr);
  86         new_value = (cur_value & (~mask)) | ((value << offset) & mask);
  87         U3PhyWriteReg32(addr, new_value);
  88         //DRV_MDELAY(100);
  89
  90         return PHY_TRUE;
  91 }
  92
  93 PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
  94
  95         return ((U3PhyReadReg8(addr) & mask) >> offset);
  96 }
  97
  98 PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
  99
 100         return ((U3PhyReadReg32(addr) & mask) >> offset);
 101 }
 102