target/linux/ramips/files/drivers/usb/host/xhci-mtk.c

   1 #include "xhci-mtk.h"
   2 #include "xhci-mtk-power.h"
   3 #include "xhci.h"
   4 #include "mtk-phy.h"
   5 #ifdef CONFIG_C60802_SUPPORT
   6 #include "mtk-phy-c60802.h"
   7 #endif
   8 #include "xhci-mtk-scheduler.h"
   9 #include <linux/kernel.h>       /* printk() */
  10 #include <linux/slab.h>
  11 #include <linux/delay.h>
  12 #include <asm/uaccess.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/platform_device.h>
  15
  16 void setInitialReg(void )
  17 {
  18         __u32 __iomem *addr;
  19         u32 temp;
  20
  21         /* set SSUSB DMA burst size to 128B */
  22         addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
  23         temp = SSUSB_HDMA_CFG_MT7621_VALUE;
  24         writel(temp, addr);
  25
  26         /* extend U3 LTSSM Polling.LFPS timeout value */
  27         addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
  28         temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
  29         writel(temp, addr);
  30
  31         /* EOF */
  32         addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
  33         temp = SYNC_HS_EOF_VALUE;
  34         writel(temp, addr);
  35
  36 #if defined (CONFIG_PERIODIC_ENP)
  37         /* HSCH_CFG1: SCH2_FIFO_DEPTH */
  38         addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
  39         temp = readl(addr);
  40         temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
  41         writel(temp, addr);
  42 #endif
  43
  44         /* Doorbell handling */
  45         addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
  46         temp = 0x1;
  47         writel(temp, addr);
  48
  49         /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
  50         /* Port 0 */
  51         addr = U2_PHY_BASE + U2_PHYD_CR1;
  52         temp = readl(addr);
  53         temp &= ~(0x3 << 18);
  54         temp |= (1 << 18);
  55         writel(temp, addr);
  56
  57         /* Port 1 */
  58         addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
  59         temp = readl(addr);
  60         temp &= ~(0x3 << 18);
  61         temp |= (1 << 18);
  62         writel(temp, addr);
  63 }
  64
  65
  66 void setLatchSel(void){
  67         __u32 __iomem *latch_sel_addr;
  68         u32 latch_sel_value;
  69         latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
  70         latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
  71         writel(latch_sel_value, latch_sel_addr);
  72 }
  73
  74 void reinitIP(void){
  75         __u32 __iomem *ip_reset_addr;
  76         u32 ip_reset_value;
  77
  78         enableAllClockPower();
  79         mtk_xhci_scheduler_init();
  80 }
  81
  82 void dbg_prb_out(void){
  83         mtk_probe_init(0x0f0f0f0f);
  84         mtk_probe_out(0xffffffff);
  85         mtk_probe_out(0x01010101);
  86         mtk_probe_out(0x02020202);
  87         mtk_probe_out(0x04040404);
  88         mtk_probe_out(0x08080808);
  89         mtk_probe_out(0x10101010);
  90         mtk_probe_out(0x20202020);
  91         mtk_probe_out(0x40404040);
  92         mtk_probe_out(0x80808080);
  93         mtk_probe_out(0x55555555);
  94         mtk_probe_out(0xaaaaaaaa);
  95 }
  96
  97
  98
  99 ///////////////////////////////////////////////////////////////////////////////
 100
 101 #define RET_SUCCESS 0
 102 #define RET_FAIL 1
 103
 104 static int dbg_u3w(int argc, char**argv)
 105 {
 106         int u4TimingValue;
 107         char u1TimingValue;
 108         int u4TimingAddress;
 109
 110         if (argc<3)
 111     {
 112         printk(KERN_ERR "Arg: address value\n");
 113         return RET_FAIL;
 114     }
 115         u3phy_init();
 116
 117         u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
 118         u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
 119         u1TimingValue = u4TimingValue & 0xff;
 120         /* access MMIO directly */
 121         writel(u1TimingValue, u4TimingAddress);
 122         printk(KERN_ERR "Write done\n");
 123         return RET_SUCCESS;
 124
 125 }
 126
 127 static int dbg_u3r(int argc, char**argv)
 128 {
 129         char u1ReadTimingValue;
 130         int u4TimingAddress;
 131         if (argc<2)
 132     {
 133         printk(KERN_ERR "Arg: address\n");
 134         return 0;
 135     }
 136         u3phy_init();
 137         mdelay(500);
 138         u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
 139         /* access MMIO directly */
 140         u1ReadTimingValue = readl(u4TimingAddress);
 141         printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
 142         return 0;
 143 }
 144
 145 static int dbg_u3init(int argc, char**argv)
 146 {
 147         int ret;
 148         ret = u3phy_init();
 149         printk(KERN_ERR "phy registers and operations initial done\n");
 150         if(u3phy_ops->u2_slew_rate_calibration){
 151                 u3phy_ops->u2_slew_rate_calibration(u3phy);
 152         }
 153         else{
 154                 printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
 155         }
 156         if(u3phy_ops->init(u3phy) == PHY_TRUE)
 157                 return RET_SUCCESS;
 158         return RET_FAIL;
 159 }
 160
 161 void dbg_setU1U2(int argc, char**argv){
 162         struct xhci_hcd *xhci;
 163         int u1_value;
 164         int u2_value;
 165         u32 port_id, temp;
 166         u32 __iomem *addr;
 167
 168         if (argc<3)
 169     {
 170         printk(KERN_ERR "Arg: u1value u2value\n");
 171         return RET_FAIL;
 172     }
 173
 174         u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
 175         u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
 176         addr = (SSUSB_U3_XHCI_BASE + 0x424);
 177         temp = readl(addr);
 178         temp = temp & (~(0x0000ffff));
 179         temp = temp | u1_value | (u2_value<<8);
 180         writel(temp, addr);
 181 }
 182 ///////////////////////////////////////////////////////////////////////////////
 183
 184 int call_function(char *buf)
 185 {
 186         int i;
 187         int argc;
 188         char *argv[80];
 189
 190         argc = 0;
 191         do
 192         {
 193                 argv[argc] = strsep(&buf, " ");
 194                 printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
 195                 argc++;
 196         } while (buf);
 197         if (!strcmp("dbg.r", argv[0]))
 198                 dbg_prb_out();
 199         else if (!strcmp("dbg.u3w", argv[0]))
 200                 dbg_u3w(argc, argv);
 201         else if (!strcmp("dbg.u3r", argv[0]))
 202                 dbg_u3r(argc, argv);
 203         else if (!strcmp("dbg.u3i", argv[0]))
 204                 dbg_u3init(argc, argv);
 205         else if (!strcmp("pw.u1u2", argv[0]))
 206                 dbg_setU1U2(argc, argv);
 207         return 0;
 208 }
 209
 210 long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 211 {
 212         char w_buf[200];
 213         char r_buf[200] = "this is a test";
 214         int len = 200;
 215
 216         switch (cmd) {
 217                 case IOCTL_READ:
 218                         copy_to_user((char *) arg, r_buf, len);
 219                         printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
 220                         break;
 221                 case IOCTL_WRITE:
 222                         copy_from_user(w_buf, (char *) arg, len);
 223                         printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
 224
 225                         //invoke function
 226                         return call_function(w_buf);
 227                         break;
 228                 default:
 229                         return -ENOTTY;
 230         }
 231
 232         return len;
 233 }
 234
 235 int xhci_mtk_test_open(struct inode *inode, struct file *file)
 236 {
 237
 238     printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
 239     return 0;
 240 }
 241
 242 int xhci_mtk_test_release(struct inode *inode, struct file *file)
 243 {
 244
 245     printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
 246     return 0;
 247 }
 248
 249 ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
 250 {
 251
 252     printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
 253     return 0;
 254 }
 255
 256 ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
 257 {
 258
 259     printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
 260     return 0;
 261 }
 262
 263
 264
 265