target/linux/ramips/files/drivers/usb/host/xhci-mtk.h

   1 #ifndef _XHCI_MTK_H
   2 #define _XHCI_MTK_H
   3
   4 #include <linux/usb.h>
   5 #include "xhci.h"
   6
   7 #define SSUSB_U3_XHCI_BASE              0xBE1C0000
   8 #define SSUSB_U3_MAC_BASE               0xBE1C2400
   9 #define SSUSB_U3_SYS_BASE               0xBE1C2600
  10 #define SSUSB_U2_SYS_BASE               0xBE1C3400
  11 #define SSUB_SIF_SLV_TOP                0xBE1D0000
  12 #define SIFSLV_IPPC                     (SSUB_SIF_SLV_TOP + 0x700)
  13
  14 #define U3_PIPE_LATCH_SEL_ADD           SSUSB_U3_MAC_BASE + 0x130
  15 #define U3_PIPE_LATCH_TX                0
  16 #define U3_PIPE_LATCH_RX                0
  17
  18 #define U3_UX_EXIT_LFPS_TIMING_PAR      0xa0
  19 #define U3_REF_CK_PAR                   0xb0
  20 #define U3_RX_UX_EXIT_LFPS_REF_OFFSET   8
  21 #define U3_RX_UX_EXIT_LFPS_REF          3
  22 #define U3_REF_CK_VAL                   10
  23
  24 #define U3_TIMING_PULSE_CTRL            0xb4
  25 #define CNT_1US_VALUE                   63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
  26
  27 #define USB20_TIMING_PARAMETER          0x40
  28 #define TIME_VALUE_1US                  63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
  29
  30 #define LINK_PM_TIMER                   0x8
  31 #define PM_LC_TIMEOUT_VALUE             3
  32
  33 #define XHCI_IMOD                       0x624
  34 #define XHCI_IMOD_MT7621_VALUE          0x10
  35
  36 #define SSUSB_HDMA_CFG                  0x950
  37 #define SSUSB_HDMA_CFG_MT7621_VALUE     0x10E0E0C
  38
  39 #define U3_LTSSM_TIMING_PARAMETER3              0x2514
  40 #define U3_LTSSM_TIMING_PARAMETER3_VALUE        0x3E8012C
  41
  42 #define U2_PHYD_CR1                     0x64
  43
  44 #define SSUSB_IP_SPAR0                  0xC8
  45
  46 #define SYNC_HS_EOF                     0x938
  47 #define SYNC_HS_EOF_VALUE               0x201F3
  48
  49 #define HSCH_CFG1                       0x960
  50 #define SCH2_FIFO_DEPTH_OFFSET          16
  51
  52
  53 #define SSUSB_IP_PW_CTRL                (SIFSLV_IPPC+0x0)
  54 #define SSUSB_IP_SW_RST                 (1<<0)
  55 #define SSUSB_IP_PW_CTRL_1              (SIFSLV_IPPC+0x4)
  56 #define SSUSB_IP_PDN                    (1<<0)
  57 #define SSUSB_U3_CTRL(p)                (SIFSLV_IPPC+0x30+(p*0x08))
  58 #define SSUSB_U3_PORT_DIS               (1<<0)
  59 #define SSUSB_U3_PORT_PDN               (1<<1)
  60 #define SSUSB_U3_PORT_HOST_SEL          (1<<2)
  61 #define SSUSB_U3_PORT_CKBG_EN           (1<<3)
  62 #define SSUSB_U3_PORT_MAC_RST           (1<<4)
  63 #define SSUSB_U3_PORT_PHYD_RST          (1<<5)
  64 #define SSUSB_U2_CTRL(p)                (SIFSLV_IPPC+(0x50)+(p*0x08))
  65 #define SSUSB_U2_PORT_DIS               (1<<0)
  66 #define SSUSB_U2_PORT_PDN               (1<<1)
  67 #define SSUSB_U2_PORT_HOST_SEL          (1<<2)
  68 #define SSUSB_U2_PORT_CKBG_EN           (1<<3)
  69 #define SSUSB_U2_PORT_MAC_RST           (1<<4)
  70 #define SSUSB_U2_PORT_PHYD_RST          (1<<5)
  71 #define SSUSB_IP_CAP                    (SIFSLV_IPPC+0x024)
  72
  73 #define SSUSB_U3_PORT_NUM(p)            (p & 0xff)
  74 #define SSUSB_U2_PORT_NUM(p)            ((p>>8) & 0xff)
  75
  76
  77 #define XHCI_MTK_TEST_MAJOR             234
  78 #define DEVICE_NAME                     "xhci_mtk_test"
  79
  80 #define CLI_MAGIC                       'CLI'
  81 #define IOCTL_READ                      _IOR(CLI_MAGIC, 0, int)
  82 #define IOCTL_WRITE                     _IOW(CLI_MAGIC, 1, int)
  83
  84 void reinitIP(void);
  85 void setInitialReg(void);
  86 void dbg_prb_out(void);
  87 int call_function(char *buf);
  88
  89 long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
  90 int xhci_mtk_test_open(struct inode *inode, struct file *file);
  91 int xhci_mtk_test_release(struct inode *inode, struct file *file);
  92 ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
  93 ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
  94
  95 /*
  96   mediatek probe out
  97 */
  98 /************************************************************************************/
  99
 100 #define SW_PRB_OUT_ADDR         (SIFSLV_IPPC+0xc0)
 101 #define PRB_MODULE_SEL_ADDR     (SIFSLV_IPPC+0xbc)
 102
 103 static inline void mtk_probe_init(const u32 byte){
 104         __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
 105         writel(byte, ptr);
 106 }
 107
 108 static inline void mtk_probe_out(const u32 value){
 109         __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
 110         writel(value, ptr);
 111 }
 112
 113 static inline u32 mtk_probe_value(void){
 114         __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
 115
 116         return readl(ptr);
 117 }
 118
 119
 120 #endif