target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch

   1 From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 18 May 2013 22:06:15 +0200
   4 Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/pci/Makefile      |    1 +
   9  arch/mips/pci/pci-mt7620a.c |  363 +++++++++++++++++++++++++++++++++++++++++++
  10  arch/mips/ralink/Kconfig    |    1 +
  11  3 files changed, 365 insertions(+)
  12  create mode 100644 arch/mips/pci/pci-mt7620a.c
  13
  14 --- /dev/null
  15 +++ b/arch/mips/pci/pci-mt7620a.c
  16 @@ -0,0 +1,363 @@
  17 +/*
  18 + *  Ralink MT7620A SoC PCI support
  19 + *
  20 + *  Copyright (C) 2007-2013 Bruce Chang
  21 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  22 + *
  23 + *  This program is free software; you can redistribute it and/or modify it
  24 + *  under the terms of the GNU General Public License version 2 as published
  25 + *  by the Free Software Foundation.
  26 + */
  27 +
  28 +#include <linux/types.h>
  29 +#include <linux/pci.h>
  30 +#include <linux/io.h>
  31 +#include <linux/init.h>
  32 +#include <linux/delay.h>
  33 +#include <linux/interrupt.h>
  34 +#include <linux/module.h>
  35 +#include <linux/of.h>
  36 +#include <linux/of_irq.h>
  37 +#include <linux/of_pci.h>
  38 +#include <linux/reset.h>
  39 +#include <linux/platform_device.h>
  40 +
  41 +#include <asm/mach-ralink/ralink_regs.h>
  42 +
  43 +#define RALINK_PCI_MM_MAP_BASE         0x20000000
  44 +#define RALINK_PCI_IO_MAP_BASE         0x10160000
  45 +
  46 +#define RALINK_INT_PCIE0               4
  47 +#define RALINK_SYSTEM_CONTROL_BASE     0xb0000000
  48 +#define RALINK_SYSCFG1                 0x14
  49 +#define RALINK_CLKCFG1                 0x30
  50 +#define RALINK_GPIOMODE                        0x60
  51 +#define RALINK_PCIE_CLK_GEN            0x7c
  52 +#define RALINK_PCIE_CLK_GEN1           0x80
  53 +#define PCIEPHY0_CFG                   0x90
  54 +#define PPLL_CFG1                      0x9c
  55 +#define PPLL_DRV                       0xa0
  56 +#define RALINK_PCI_HOST_MODE_EN                (1<<7)
  57 +#define RALINK_PCIE_RC_MODE_EN         (1<<8)
  58 +#define RALINK_PCIE_RST                        (1<<23)
  59 +#define RALINK_PCI_RST                 (1<<24)
  60 +#define RALINK_PCI_CLK_EN              (1<<19)
  61 +#define RALINK_PCIE_CLK_EN             (1<<21)
  62 +#define PCI_SLOTx2                     (1<<11)
  63 +#define PCI_SLOTx1                     (2<<11)
  64 +#define PDRV_SW_SET                    (1<<31)
  65 +#define LC_CKDRVPD_                    (1<<19)
  66 +
  67 +#define RALINK_PCI_CONFIG_ADDR         0x20
  68 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
  69 +#define MEMORY_BASE                    0x0
  70 +#define RALINK_PCIE0_RST               (1<<26)
  71 +#define RALINK_PCI_BASE                        0xB0140000
  72 +#define RALINK_PCI_MEMBASE             0x28
  73 +#define RALINK_PCI_IOBASE              0x2C
  74 +
  75 +#define RT6855_PCIE0_OFFSET            0x2000
  76 +
  77 +#define RALINK_PCI_PCICFG_ADDR         0x00
  78 +#define RALINK_PCI0_BAR0SETUP_ADDR     0x10
  79 +#define RALINK_PCI0_IMBASEBAR0_ADDR    0x18
  80 +#define RALINK_PCI0_ID                 0x30
  81 +#define RALINK_PCI0_CLASS              0x34
  82 +#define RALINK_PCI0_SUBID              0x38
  83 +#define RALINK_PCI0_STATUS             0x50
  84 +#define RALINK_PCI_PCIMSK_ADDR         0x0C
  85 +
  86 +#define RALINK_PCIE0_CLK_EN            (1 << 26)
  87 +
  88 +#define BUSY                           0x80000000
  89 +#define WAITRETRY_MAX                  10
  90 +#define WRITE_MODE                     (1UL << 23)
  91 +#define DATA_SHIFT                     0
  92 +#define ADDR_SHIFT                     8
  93 +
  94 +
  95 +static void __iomem *bridge_base;
  96 +static void __iomem *pcie_base;
  97 +
  98 +static struct reset_control *rstpcie0;
  99 +
 100 +static inline void bridge_w32(u32 val, unsigned reg)
 101 +{
 102 +       iowrite32(val, bridge_base + reg);
 103 +}
 104 +
 105 +static inline u32 bridge_r32(unsigned reg)
 106 +{
 107 +       return ioread32(bridge_base + reg);
 108 +}
 109 +
 110 +static inline void pcie_w32(u32 val, unsigned reg)
 111 +{
 112 +       iowrite32(val, pcie_base + reg);
 113 +}
 114 +
 115 +static inline u32 pcie_r32(unsigned reg)
 116 +{
 117 +       return ioread32(pcie_base + reg);
 118 +}
 119 +
 120 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 121 +{
 122 +       u32 val = pcie_r32(reg);
 123 +       val &= ~clr;
 124 +       val |= set;
 125 +       pcie_w32(val, reg);
 126 +}
 127 +
 128 +int wait_pciephy_busy(void)
 129 +{
 130 +       unsigned long reg_value = 0x0, retry = 0;
 131 +
 132 +       while (1) {
 133 +               //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
 134 +               reg_value = pcie_r32(PCIEPHY0_CFG);
 135 +
 136 +               if (reg_value & BUSY)
 137 +                       mdelay(100);
 138 +               else
 139 +                       break;
 140 +               if (retry++ > WAITRETRY_MAX){
 141 +                       printk("PCIE-PHY retry failed.\n");
 142 +                       return -1;
 143 +               }
 144 +       }
 145 +       return 0;
 146 +}
 147 +
 148 +static void pcie_phy(unsigned long addr, unsigned long val)
 149 +{
 150 +       wait_pciephy_busy();
 151 +       pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
 152 +       mdelay(1);
 153 +       wait_pciephy_busy();
 154 +}
 155 +
 156 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 157 +{
 158 +       unsigned int slot = PCI_SLOT(devfn);
 159 +       u8 func = PCI_FUNC(devfn);
 160 +       u32 address;
 161 +       u32 data;
 162 +
 163 +       address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 164 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 165 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 166 +
 167 +       switch (size) {
 168 +       case 1:
 169 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 170 +               break;
 171 +       case 2:
 172 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 173 +               break;
 174 +       case 4:
 175 +               *val = data;
 176 +               break;
 177 +       }
 178 +
 179 +       return PCIBIOS_SUCCESSFUL;
 180 +}
 181 +
 182 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 183 +{
 184 +       unsigned int slot = PCI_SLOT(devfn);
 185 +       u8 func = PCI_FUNC(devfn);
 186 +       u32 address;
 187 +       u32 data;
 188 +
 189 +       address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 190 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 191 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 192 +
 193 +       switch (size) {
 194 +       case 1:
 195 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 196 +                       (val << ((where & 3) << 3));
 197 +               break;
 198 +       case 2:
 199 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 200 +                       (val << ((where & 3) << 3));
 201 +               break;
 202 +       case 4:
 203 +               data = val;
 204 +               break;
 205 +       }
 206 +
 207 +       bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 208 +
 209 +       return PCIBIOS_SUCCESSFUL;
 210 +}
 211 +
 212 +struct pci_ops mt7620a_pci_ops= {
 213 +       .read   = pci_config_read,
 214 +       .write  = pci_config_write,
 215 +};
 216 +
 217 +static struct resource mt7620a_res_pci_mem1 = {
 218 +       .name   = "pci memory",
 219 +       .start  = RALINK_PCI_MM_MAP_BASE,
 220 +       .end    = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 221 +       .flags  = IORESOURCE_MEM,
 222 +};
 223 +static struct resource mt7620a_res_pci_io1 = {
 224 +       .name   = "pci io",
 225 +       .start  = RALINK_PCI_IO_MAP_BASE,
 226 +       .end    = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 227 +       .flags  = IORESOURCE_IO,
 228 +};
 229 +
 230 +struct pci_controller mt7620a_controller = {
 231 +       .pci_ops        = &mt7620a_pci_ops,
 232 +       .mem_resource   = &mt7620a_res_pci_mem1,
 233 +       .io_resource    = &mt7620a_res_pci_io1,
 234 +       .mem_offset     = 0x00000000UL,
 235 +       .io_offset      = 0x00000000UL,
 236 +       .io_map_base    = 0xa0000000,
 237 +};
 238 +
 239 +static int mt7620a_pci_probe(struct platform_device *pdev)
 240 +{
 241 +       struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 242 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 243 +
 244 +       rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
 245 +       if (IS_ERR(rstpcie0))
 246 +               return PTR_ERR(rstpcie0);
 247 +
 248 +       bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
 249 +        if (!bridge_base)
 250 +               return -ENOMEM;
 251 +
 252 +       pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
 253 +        if (!pcie_base)
 254 +               return -ENOMEM;
 255 +
 256 +       iomem_resource.start = 0;
 257 +       iomem_resource.end= ~0;
 258 +       ioport_resource.start= 0;
 259 +       ioport_resource.end = ~0;
 260 +
 261 +       /* PCIE: bypass PCIe DLL */
 262 +       pcie_phy(0x0, 0x80);
 263 +       pcie_phy(0x1, 0x04);
 264 +       /* PCIE: Elastic buffer control */
 265 +       pcie_phy(0x68, 0xB4);
 266 +
 267 +       reset_control_assert(rstpcie0);
 268 +       rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 269 +       rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
 270 +       rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
 271 +
 272 +       reset_control_deassert(rstpcie0);
 273 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 274 +
 275 +       mdelay(100);
 276 +
 277 +       if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
 278 +               printk("MT7620 PPLL unlock\n");
 279 +               reset_control_assert(rstpcie0);
 280 +               rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
 281 +               return 0;
 282 +       }
 283 +       rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
 284 +
 285 +       mdelay(100);
 286 +       reset_control_assert(rstpcie0);
 287 +       rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
 288 +
 289 +       rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
 290 +       rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
 291 +
 292 +       mdelay(50);
 293 +       reset_control_deassert(rstpcie0);
 294 +       pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 295 +       mdelay(100);
 296 +
 297 +       if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 298 +               reset_control_assert(rstpcie0);
 299 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 300 +               rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 301 +               printk("PCIE0 no card, disable it(RST&CLK)\n");
 302 +       }
 303 +
 304 +       bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 305 +       bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 306 +
 307 +       pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
 308 +       pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 309 +       pcie_w32(0x08021814, RALINK_PCI0_ID);
 310 +       pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 311 +       pcie_w32(0x28801814, RALINK_PCI0_SUBID);
 312 +       pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 313 +
 314 +       register_pci_controller(&mt7620a_controller);
 315 +
 316 +       return 0;
 317 +}
 318 +
 319 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 320 +{
 321 +       const struct resource *res;
 322 +       u16 cmd;
 323 +       u32 val;
 324 +       int i, irq = 0;
 325 +
 326 +       if ((dev->bus->number == 0) && (slot == 0)) {
 327 +               pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
 328 +               pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 329 +               pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 330 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 331 +               irq = RALINK_INT_PCIE0;
 332 +       } else {
 333 +               printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 334 +               return 0;
 335 +       }
 336 +
 337 +       for (i = 0; i < 6; i++) {
 338 +               res = &dev->resource[i];
 339 +       }
 340 +
 341 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 342 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 343 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 344 +
 345 +       // FIXME
 346 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 347 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 348 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 349 +       //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
 350 +
 351 +       return irq;
 352 +}
 353 +
 354 +int pcibios_plat_dev_init(struct pci_dev *dev)
 355 +{
 356 +       return 0;
 357 +}
 358 +
 359 +static const struct of_device_id mt7620a_pci_ids[] = {
 360 +       { .compatible = "ralink,mt7620a-pci" },
 361 +       {},
 362 +};
 363 +MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
 364 +
 365 +static struct platform_driver mt7620a_pci_driver = {
 366 +       .probe = mt7620a_pci_probe,
 367 +       .driver = {
 368 +               .name = "mt7620a-pci",
 369 +               .owner = THIS_MODULE,
 370 +               .of_match_table = of_match_ptr(mt7620a_pci_ids),
 371 +       },
 372 +};
 373 +
 374 +static int __init mt7620a_pci_init(void)
 375 +{
 376 +       return platform_driver_register(&mt7620a_pci_driver);
 377 +}
 378 +
 379 +arch_initcall(mt7620a_pci_init);
 380 --- a/arch/mips/ralink/Kconfig
 381 +++ b/arch/mips/ralink/Kconfig
 382 @@ -33,6 +33,7 @@ choice
 383                 bool "MT7620"
 384                 select USB_ARCH_HAS_OHCI
 385                 select USB_ARCH_HAS_EHCI
 386 +               select HW_HAS_PCI
 387
 388  endchoice
 389
 390 --- a/arch/mips/pci/Makefile
 391 +++ b/arch/mips/pci/Makefile
 392 @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
 393  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
 394  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
 395  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
 396 +obj-$(CONFIG_SOC_MT7620)       += pci-mt7620a.o
 397  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
 398  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
 399  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o