target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch

   1 From d4398d880eba386cb85d0a1a2ba39a336876dc0a Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 3 Dec 2013 20:18:13 +0100
   4 Subject: [PATCH 112/133] asoc: add mt7620 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/ralink/of.c            |    2 +
   9  sound/soc/Kconfig                |    1 +
  10  sound/soc/Makefile               |    1 +
  11  sound/soc/ralink/Kconfig         |   15 ++
  12  sound/soc/ralink/Makefile        |   11 +
  13  sound/soc/ralink/mt7620-i2s.c    |  466 ++++++++++++++++++++++++++++++++++++++
  14  sound/soc/ralink/mt7620-wm8960.c |  125 ++++++++++
  15  sound/soc/soc-io.c               |   10 -
  16  8 files changed, 621 insertions(+), 10 deletions(-)
  17  create mode 100644 sound/soc/ralink/Kconfig
  18  create mode 100644 sound/soc/ralink/Makefile
  19  create mode 100644 sound/soc/ralink/mt7620-i2s.c
  20  create mode 100644 sound/soc/ralink/mt7620-wm8960.c
  21
  22 --- a/arch/mips/ralink/of.c
  23 +++ b/arch/mips/ralink/of.c
  24 @@ -15,6 +15,7 @@
  25  #include <linux/of_fdt.h>
  26  #include <linux/kernel.h>
  27  #include <linux/bootmem.h>
  28 +#include <linux/module.h>
  29  #include <linux/of_platform.h>
  30  #include <linux/of_address.h>
  31
  32 @@ -25,6 +26,7 @@
  33  #include "common.h"
  34
  35  __iomem void *rt_sysc_membase;
  36 +EXPORT_SYMBOL(rt_sysc_membase);
  37  __iomem void *rt_memc_membase;
  38
  39  extern struct boot_param_header __dtb_start;
  40 --- a/sound/soc/Kconfig
  41 +++ b/sound/soc/Kconfig
  42 @@ -48,6 +48,7 @@ source "sound/soc/kirkwood/Kconfig"
  43  source "sound/soc/mid-x86/Kconfig"
  44  source "sound/soc/mxs/Kconfig"
  45  source "sound/soc/pxa/Kconfig"
  46 +source "sound/soc/ralink/Kconfig"
  47  source "sound/soc/samsung/Kconfig"
  48  source "sound/soc/s6000/Kconfig"
  49  source "sound/soc/sh/Kconfig"
  50 --- a/sound/soc/Makefile
  51 +++ b/sound/soc/Makefile
  52 @@ -26,6 +26,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
  53  obj-$(CONFIG_SND_SOC)  += omap/
  54  obj-$(CONFIG_SND_SOC)  += kirkwood/
  55  obj-$(CONFIG_SND_SOC)  += pxa/
  56 +obj-$(CONFIG_SND_SOC)  += ralink/
  57  obj-$(CONFIG_SND_SOC)  += samsung/
  58  obj-$(CONFIG_SND_SOC)  += s6000/
  59  obj-$(CONFIG_SND_SOC)  += sh/
  60 --- /dev/null
  61 +++ b/sound/soc/ralink/Kconfig
  62 @@ -0,0 +1,15 @@
  63 +config SND_MT7620_SOC_I2S
  64 +       depends on SOC_MT7620 && SND_SOC
  65 +       select SND_SOC_GENERIC_DMAENGINE_PCM
  66 +       tristate "SoC Audio (I2S protocol) for Ralink MT7620 SoC"
  67 +       help
  68 +         Say Y if you want to use I2S protocol and I2S codec on Ingenic MT7620
  69 +         based boards.
  70 +
  71 +config SND_MT7620_SOC_WM8960
  72 +       tristate "SoC Audio support for Ralink WM8960"
  73 +       select SND_MT7620_SOC_I2S
  74 +       select SND_SOC_WM8960
  75 +       help
  76 +         Say Y if you want to add support for ASoC audio on the Qi LB60 board
  77 +         a.k.a Qi Ben NanoNote.
  78 --- /dev/null
  79 +++ b/sound/soc/ralink/Makefile
  80 @@ -0,0 +1,11 @@
  81 +#
  82 +# Jz4740 Platform Support
  83 +#
  84 +snd-soc-mt7620-i2s-objs := mt7620-i2s.o
  85 +
  86 +obj-$(CONFIG_SND_MT7620_SOC_I2S) += snd-soc-mt7620-i2s.o
  87 +
  88 +# Jz4740 Machine Support
  89 +snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o
  90 +
  91 +obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o
  92 --- /dev/null
  93 +++ b/sound/soc/ralink/mt7620-i2s.c
  94 @@ -0,0 +1,466 @@
  95 +/*
  96 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  97 + *
  98 + *  This program is free software; you can redistribute it and/or modify it
  99 + *  under  the terms of the GNU General  Public License as published by the
 100 + *  Free Software Foundation;  either version 2 of the License, or (at your
 101 + *  option) any later version.
 102 + *
 103 + *  You should have received a copy of the GNU General Public License along
 104 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 105 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 106 + *
 107 + */
 108 +
 109 +#include <linux/init.h>
 110 +#include <linux/io.h>
 111 +#include <linux/kernel.h>
 112 +#include <linux/module.h>
 113 +#include <linux/platform_device.h>
 114 +#include <linux/slab.h>
 115 +
 116 +#include <linux/delay.h>
 117 +
 118 +#include <linux/dma-mapping.h>
 119 +
 120 +#include <sound/core.h>
 121 +#include <sound/pcm.h>
 122 +#include <sound/pcm_params.h>
 123 +#include <sound/soc.h>
 124 +#include <sound/initval.h>
 125 +#include <sound/dmaengine_pcm.h>
 126 +
 127 +#include <ralink_regs.h>
 128 +
 129 +#define I2S_REG_CFG0           0x00
 130 +#define I2S_REG_CFG0_EN                BIT(31)
 131 +#define I2S_REG_CFG0_DMA_EN    BIT(30)
 132 +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
 133 +#define I2S_REG_CFG0_TX_EN     BIT(24)
 134 +#define I2S_REG_CFG0_RX_EN     BIT(20)
 135 +#define I2S_REG_CFG0_SLAVE     BIT(16)
 136 +#define I2S_REG_CFG0_RX_THRES  12
 137 +#define I2S_REG_CFG0_TX_THRES  4
 138 +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
 139 +                                       (4 << I2S_REG_CFG0_TX_THRES)
 140 +
 141 +#define I2S_REG_INT_STATUS     0x04
 142 +#define I2S_REG_INT_EN         0x08
 143 +#define I2S_REG_FF_STATUS      0x0c
 144 +#define I2S_REG_WREG           0x10
 145 +#define I2S_REG_RREG           0x14
 146 +#define I2S_REG_CFG1           0x18
 147 +
 148 +#define I2S_REG_DIVCMP         0x20
 149 +#define I2S_REG_DIVINT         0x24
 150 +#define I2S_REG_CLK_EN         BIT(31)
 151 +
 152 +struct mt7620_i2s {
 153 +       struct resource *mem;
 154 +       void __iomem *base;
 155 +       dma_addr_t phys_base;
 156 +
 157 +       struct snd_dmaengine_dai_dma_data playback_dma_data;
 158 +       struct snd_dmaengine_dai_dma_data capture_dma_data;
 159 +};
 160 +
 161 +static inline uint32_t mt7620_i2s_read(const struct mt7620_i2s *i2s,
 162 +       unsigned int reg)
 163 +{
 164 +       return readl(i2s->base + reg);
 165 +}
 166 +
 167 +static inline void mt7620_i2s_write(const struct mt7620_i2s *i2s,
 168 +       unsigned int reg, uint32_t value)
 169 +{
 170 +       //printk("i2s --> %p = 0x%08X\n", i2s->base + reg, value);
 171 +       writel(value, i2s->base + reg);
 172 +}
 173 +
 174 +static int mt7620_i2s_startup(struct snd_pcm_substream *substream,
 175 +       struct snd_soc_dai *dai)
 176 +{
 177 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 178 +       uint32_t cfg;
 179 +
 180 +       if (dai->active)
 181 +               return 0;
 182 +
 183 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 184 +       cfg |= I2S_REG_CFG0_EN;
 185 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 186 +
 187 +       return 0;
 188 +}
 189 +
 190 +static void mt7620_i2s_shutdown(struct snd_pcm_substream *substream,
 191 +       struct snd_soc_dai *dai)
 192 +{
 193 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 194 +       uint32_t cfg;
 195 +
 196 +       if (dai->active)
 197 +               return;
 198 +
 199 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 200 +       cfg &= ~I2S_REG_CFG0_EN;
 201 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 202 +}
 203 +
 204 +static int mt7620_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 205 +       struct snd_soc_dai *dai)
 206 +{
 207 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 208 +
 209 +       uint32_t cfg;
 210 +       uint32_t mask;
 211 +
 212 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 213 +               mask = I2S_REG_CFG0_TX_EN;
 214 +       else
 215 +               mask = I2S_REG_CFG0_RX_EN;
 216 +
 217 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 218 +
 219 +       switch (cmd) {
 220 +       case SNDRV_PCM_TRIGGER_START:
 221 +       case SNDRV_PCM_TRIGGER_RESUME:
 222 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 223 +               cfg |= mask;
 224 +               break;
 225 +       case SNDRV_PCM_TRIGGER_STOP:
 226 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 227 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 228 +               cfg &= ~mask;
 229 +               break;
 230 +       default:
 231 +               return -EINVAL;
 232 +       }
 233 +
 234 +       if (cfg & (I2S_REG_CFG0_TX_EN | I2S_REG_CFG0_RX_EN))
 235 +               cfg |= I2S_REG_CFG0_DMA_EN;
 236 +       else
 237 +               cfg &= ~I2S_REG_CFG0_DMA_EN;
 238 +
 239 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 240 +
 241 +       return 0;
 242 +}
 243 +
 244 +static int mt7620_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 245 +{
 246 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 247 +       uint32_t cfg;
 248 +
 249 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 250 +
 251 +       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 252 +       case SND_SOC_DAIFMT_CBS_CFS:
 253 +               cfg |= I2S_REG_CFG0_SLAVE;
 254 +               break;
 255 +       case SND_SOC_DAIFMT_CBM_CFM:
 256 +               cfg &= ~I2S_REG_CFG0_SLAVE;
 257 +               break;
 258 +       case SND_SOC_DAIFMT_CBM_CFS:
 259 +       default:
 260 +               return -EINVAL;
 261 +       }
 262 +
 263 +       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 264 +       case SND_SOC_DAIFMT_I2S:
 265 +       case SND_SOC_DAIFMT_MSB:
 266 +               cfg &= ~I2S_REG_CFG0_BYTE_SWAP;
 267 +               break;
 268 +       case SND_SOC_DAIFMT_LSB:
 269 +               cfg |= I2S_REG_CFG0_BYTE_SWAP;
 270 +               break;
 271 +       default:
 272 +               return -EINVAL;
 273 +       }
 274 +
 275 +       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 276 +       case SND_SOC_DAIFMT_NB_NF:
 277 +               break;
 278 +       default:
 279 +               return -EINVAL;
 280 +       }
 281 +
 282 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 283 +
 284 +       return 0;
 285 +}
 286 +
 287 +static int mt7620_i2s_hw_params(struct snd_pcm_substream *substream,
 288 +       struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 289 +{
 290 +
 291 +       return 0;
 292 +}
 293 +
 294 +unsigned long i2sMaster_inclk_int[11] = {
 295 +       78,     56,     52,     39,     28,     26,     19,     14,     13,     9,      6};
 296 +unsigned long i2sMaster_inclk_comp[11] = {
 297 +       64,     352,    42,     32,     176,    21,     272,    88,     10,     455,    261};
 298 +
 299 +
 300 +static int mt7620_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 301 +       unsigned int freq, int dir)
 302 +{
 303 +        struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 304 +
 305 +       printk("Internal REFCLK with fractional division\n");
 306 +
 307 +       mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
 308 +       mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
 309 +               i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
 310 +
 311 +/*     struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 312 +       struct clk *parent;
 313 +       int ret = 0;
 314 +
 315 +       switch (clk_id) {
 316 +       case JZ4740_I2S_CLKSRC_EXT:
 317 +               parent = clk_get(NULL, "ext");
 318 +               clk_set_parent(i2s->clk_i2s, parent);
 319 +               break;
 320 +       case JZ4740_I2S_CLKSRC_PLL:
 321 +               parent = clk_get(NULL, "pll half");
 322 +               clk_set_parent(i2s->clk_i2s, parent);
 323 +               ret = clk_set_rate(i2s->clk_i2s, freq);
 324 +               break;
 325 +       default:
 326 +               return -EINVAL;
 327 +       }
 328 +       clk_put(parent);
 329 +
 330 +       return ret;*/
 331 +       return 0;
 332 +}
 333 +
 334 +static int mt7620_i2s_suspend(struct snd_soc_dai *dai)
 335 +{
 336 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 337 +       uint32_t cfg;
 338 +
 339 +       if (dai->active) {
 340 +               cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 341 +               cfg &= ~I2S_REG_CFG0_TX_EN;
 342 +               mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 343 +       }
 344 +
 345 +       return 0;
 346 +}
 347 +
 348 +static int mt7620_i2s_resume(struct snd_soc_dai *dai)
 349 +{
 350 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 351 +       uint32_t cfg;
 352 +
 353 +       if (dai->active) {
 354 +               cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 355 +               cfg |= I2S_REG_CFG0_TX_EN;
 356 +               mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 357 +       }
 358 +
 359 +       return 0;
 360 +}
 361 +
 362 +static void mt7620_i2c_init_pcm_config(struct mt7620_i2s *i2s)
 363 +{
 364 +       struct snd_dmaengine_dai_dma_data *dma_data;
 365 +
 366 +       /* Playback */
 367 +       dma_data = &i2s->playback_dma_data;
 368 +       dma_data->maxburst = 16;
 369 +       dma_data->slave_id = 2; //JZ4740_DMA_TYPE_AIC_TRANSMIT;
 370 +       dma_data->addr = i2s->phys_base + I2S_REG_WREG;
 371 +
 372 +       /* Capture */
 373 +       dma_data = &i2s->capture_dma_data;
 374 +       dma_data->maxburst = 16;
 375 +       dma_data->slave_id = 3; //JZ4740_DMA_TYPE_AIC_RECEIVE;
 376 +       dma_data->addr = i2s->phys_base + I2S_REG_RREG;
 377 +}
 378 +
 379 +static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai)
 380 +{
 381 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 382 +       uint32_t data;
 383 +
 384 +       mt7620_i2c_init_pcm_config(i2s);
 385 +       dai->playback_dma_data = &i2s->playback_dma_data;
 386 +       dai->capture_dma_data = &i2s->capture_dma_data;
 387 +
 388 +       /* set share pins to i2s/gpio mode and i2c mode */
 389 +       data = rt_sysc_r32(0x60);
 390 +       data &= 0xFFFFFFE2;
 391 +       data |= 0x00000018;
 392 +       rt_sysc_w32(data, 0x60);
 393 +
 394 +       printk("Internal REFCLK with fractional division\n");
 395 +
 396 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES);
 397 +       mt7620_i2s_write(i2s, I2S_REG_CFG1, 0);
 398 +       mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0);
 399 +
 400 +       mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
 401 +       mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
 402 +               i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
 403 +
 404 +       return 0;
 405 +}
 406 +
 407 +static int mt7620_i2s_dai_remove(struct snd_soc_dai *dai)
 408 +{
 409 +       return 0;
 410 +}
 411 +
 412 +static const struct snd_soc_dai_ops mt7620_i2s_dai_ops = {
 413 +       .startup = mt7620_i2s_startup,
 414 +       .shutdown = mt7620_i2s_shutdown,
 415 +       .trigger = mt7620_i2s_trigger,
 416 +       .hw_params = mt7620_i2s_hw_params,
 417 +       .set_fmt = mt7620_i2s_set_fmt,
 418 +       .set_sysclk = mt7620_i2s_set_sysclk,
 419 +};
 420 +
 421 +#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 422 +               SNDRV_PCM_FMTBIT_S16_LE)
 423 +
 424 +static struct snd_soc_dai_driver mt7620_i2s_dai = {
 425 +       .probe = mt7620_i2s_dai_probe,
 426 +       .remove = mt7620_i2s_dai_remove,
 427 +       .playback = {
 428 +               .channels_min = 1,
 429 +               .channels_max = 2,
 430 +               .rates = SNDRV_PCM_RATE_8000_48000,
 431 +               .formats = JZ4740_I2S_FMTS,
 432 +       },
 433 +       .capture = {
 434 +               .channels_min = 2,
 435 +               .channels_max = 2,
 436 +               .rates = SNDRV_PCM_RATE_8000_48000,
 437 +               .formats = JZ4740_I2S_FMTS,
 438 +       },
 439 +       .symmetric_rates = 1,
 440 +       .ops = &mt7620_i2s_dai_ops,
 441 +       .suspend = mt7620_i2s_suspend,
 442 +       .resume = mt7620_i2s_resume,
 443 +};
 444 +
 445 +static const struct snd_pcm_hardware mt7620_pcm_hardware = {
 446 +       .info = SNDRV_PCM_INFO_MMAP |
 447 +               SNDRV_PCM_INFO_MMAP_VALID |
 448 +               SNDRV_PCM_INFO_INTERLEAVED |
 449 +               SNDRV_PCM_INFO_BLOCK_TRANSFER,
 450 +       .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
 451 +       .period_bytes_min       = PAGE_SIZE,
 452 +       .period_bytes_max       = 64 * 1024,
 453 +       .periods_min            = 2,
 454 +       .periods_max            = 128,
 455 +       .buffer_bytes_max       = 128 * 1024,
 456 +       .fifo_size              = 32,
 457 +};
 458 +
 459 +static const struct snd_dmaengine_pcm_config mt7620_dmaengine_pcm_config = {
 460 +       .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 461 +       .pcm_hardware = &mt7620_pcm_hardware,
 462 +       .prealloc_buffer_size = 256 * PAGE_SIZE,
 463 +};
 464 +
 465 +static const struct snd_soc_component_driver mt7620_i2s_component = {
 466 +       .name = "mt7620-i2s",
 467 +};
 468 +
 469 +static int mt7620_i2s_dev_probe(struct platform_device *pdev)
 470 +{
 471 +       struct mt7620_i2s *i2s;
 472 +       int ret;
 473 +
 474 +       snd_dmaengine_pcm_register(&pdev->dev,
 475 +               &mt7620_dmaengine_pcm_config,
 476 +               SND_DMAENGINE_PCM_FLAG_COMPAT);
 477 +
 478 +       i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
 479 +       if (!i2s)
 480 +               return -ENOMEM;
 481 +
 482 +       i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 483 +       if (!i2s->mem) {
 484 +               ret = -ENOENT;
 485 +               goto err_free;
 486 +       }
 487 +
 488 +       i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
 489 +                               pdev->name);
 490 +       if (!i2s->mem) {
 491 +               ret = -EBUSY;
 492 +               goto err_free;
 493 +       }
 494 +
 495 +       i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
 496 +       if (!i2s->base) {
 497 +               ret = -EBUSY;
 498 +               goto err_release_mem_region;
 499 +       }
 500 +
 501 +       i2s->phys_base = i2s->mem->start;
 502 +
 503 +       platform_set_drvdata(pdev, i2s);
 504 +       ret = snd_soc_register_component(&pdev->dev, &mt7620_i2s_component,
 505 +                                        &mt7620_i2s_dai, 1);
 506 +
 507 +       if (!ret) {
 508 +               dev_err(&pdev->dev, "loaded\n");
 509 +               return ret;
 510 +       }
 511 +
 512 +       dev_err(&pdev->dev, "Failed to register DAI\n");
 513 +       iounmap(i2s->base);
 514 +
 515 +err_release_mem_region:
 516 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 517 +err_free:
 518 +       kfree(i2s);
 519 +
 520 +       return ret;
 521 +}
 522 +
 523 +static int mt7620_i2s_dev_remove(struct platform_device *pdev)
 524 +{
 525 +       struct mt7620_i2s *i2s = platform_get_drvdata(pdev);
 526 +
 527 +       snd_soc_unregister_component(&pdev->dev);
 528 +
 529 +       iounmap(i2s->base);
 530 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 531 +
 532 +       kfree(i2s);
 533 +
 534 +       snd_dmaengine_pcm_unregister(&pdev->dev);
 535 +
 536 +       return 0;
 537 +}
 538 +
 539 +static const struct of_device_id mt7620_i2s_match[] = {
 540 +       { .compatible = "ralink,mt7620a-i2s" },
 541 +       {},
 542 +};
 543 +MODULE_DEVICE_TABLE(of, mt7620_i2s_match);
 544 +
 545 +static struct platform_driver mt7620_i2s_driver = {
 546 +       .probe = mt7620_i2s_dev_probe,
 547 +       .remove = mt7620_i2s_dev_remove,
 548 +       .driver = {
 549 +               .name = "mt7620-i2s",
 550 +               .owner = THIS_MODULE,
 551 +               .of_match_table = mt7620_i2s_match,
 552 +       },
 553 +};
 554 +
 555 +module_platform_driver(mt7620_i2s_driver);
 556 +
 557 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 558 +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 559 +MODULE_LICENSE("GPL");
 560 +MODULE_ALIAS("platform:mt7620-i2s");
 561 --- /dev/null
 562 +++ b/sound/soc/ralink/mt7620-wm8960.c
 563 @@ -0,0 +1,125 @@
 564 +/*
 565 + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
 566 + *
 567 + * This program is free software; you can redistribute it and/or modify
 568 + * it under the terms of the GNU General Public License version 2 as
 569 + * published by the Free Software Foundation.
 570 + *
 571 + *  You should have received a copy of the  GNU General Public License along
 572 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 573 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 574 + *
 575 + */
 576 +
 577 +#include <linux/module.h>
 578 +#include <linux/moduleparam.h>
 579 +#include <linux/of.h>
 580 +#include <linux/timer.h>
 581 +#include <linux/interrupt.h>
 582 +#include <linux/platform_device.h>
 583 +#include <sound/core.h>
 584 +#include <sound/pcm.h>
 585 +#include <sound/soc.h>
 586 +
 587 +
 588 +static const struct snd_soc_dapm_widget mt7620_wm8960_widgets[] = {
 589 +       SND_SOC_DAPM_SPK("Speaker", NULL),
 590 +};
 591 +
 592 +static const struct snd_soc_dapm_route mt7620_wm8960_routes[] = {
 593 +       {"Speaker", NULL, "HP_L"},
 594 +       {"Speaker", NULL, "HP_R"},
 595 +};
 596 +
 597 +#define MT7620_DAIFMT (SND_SOC_DAIFMT_I2S | \
 598 +                       SND_SOC_DAIFMT_NB_NF | \
 599 +                       SND_SOC_DAIFMT_CBM_CFM)
 600 +
 601 +static int mt7620_wm8960_codec_init(struct snd_soc_pcm_runtime *rtd)
 602 +{
 603 +       struct snd_soc_codec *codec = rtd->codec;
 604 +       struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 605 +       struct snd_soc_dapm_context *dapm = &codec->dapm;
 606 +       int ret;
 607 +
 608 +       snd_soc_dapm_enable_pin(dapm, "HP_L");
 609 +       snd_soc_dapm_enable_pin(dapm, "HP_R");
 610 +
 611 +       ret = snd_soc_dai_set_fmt(cpu_dai, MT7620_DAIFMT);
 612 +       if (ret < 0) {
 613 +               dev_err(codec->dev, "Failed to set cpu dai format: %d\n", ret);
 614 +               return ret;
 615 +       }
 616 +
 617 +       return 0;
 618 +}
 619 +
 620 +static struct snd_soc_dai_link mt7620_wm8960_dai = {
 621 +       .name = "mt7620",
 622 +       .stream_name = "mt7620",
 623 +       .init = mt7620_wm8960_codec_init,
 624 +       .codec_dai_name = "wm8960-hifi",
 625 +};
 626 +
 627 +static struct snd_soc_card mt7620_wm8960 = {
 628 +       .name = "mt7620-wm8960",
 629 +       .owner = THIS_MODULE,
 630 +       .dai_link = &mt7620_wm8960_dai,
 631 +       .num_links = 1,
 632 +
 633 +       .dapm_widgets = mt7620_wm8960_widgets,
 634 +       .num_dapm_widgets = ARRAY_SIZE(mt7620_wm8960_widgets),
 635 +       .dapm_routes = mt7620_wm8960_routes,
 636 +       .num_dapm_routes = ARRAY_SIZE(mt7620_wm8960_routes),
 637 +};
 638 +
 639 +static int mt7620_wm8960_probe(struct platform_device *pdev)
 640 +{
 641 +       struct device_node *np = pdev->dev.of_node;
 642 +       struct snd_soc_card *card = &mt7620_wm8960;
 643 +       int ret;
 644 +
 645 +       card->dev = &pdev->dev;
 646 +
 647 +       mt7620_wm8960_dai.cpu_of_node = of_parse_phandle(np, "cpu-dai", 0);
 648 +       mt7620_wm8960_dai.codec_of_node = of_parse_phandle(np, "codec-dai", 0);
 649 +       mt7620_wm8960_dai.platform_of_node = mt7620_wm8960_dai.cpu_of_node;
 650 +
 651 +       ret = snd_soc_register_card(card);
 652 +       if (ret) {
 653 +               dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
 654 +                       ret);
 655 +       }
 656 +       return ret;
 657 +}
 658 +
 659 +static int mt7620_wm8960_remove(struct platform_device *pdev)
 660 +{
 661 +       struct snd_soc_card *card = platform_get_drvdata(pdev);
 662 +
 663 +       snd_soc_unregister_card(card);
 664 +       return 0;
 665 +}
 666 +
 667 +static const struct of_device_id mt7620_audio_match[] = {
 668 +       { .compatible = "ralink,wm8960-audio" },
 669 +       {},
 670 +};
 671 +MODULE_DEVICE_TABLE(of, mt7620_audio_match);
 672 +
 673 +static struct platform_driver mt7620_wm8960_driver = {
 674 +       .driver         = {
 675 +               .name   = "wm8960-audio",
 676 +               .owner  = THIS_MODULE,
 677 +               .of_match_table = mt7620_audio_match,
 678 +       },
 679 +       .probe          = mt7620_wm8960_probe,
 680 +       .remove         = mt7620_wm8960_remove,
 681 +};
 682 +
 683 +module_platform_driver(mt7620_wm8960_driver);
 684 +
 685 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 686 +MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
 687 +MODULE_LICENSE("GPL v2");
 688 +MODULE_ALIAS("platform:qi-lb60-audio");
 689 --- a/sound/soc/soc-io.c
 690 +++ b/sound/soc/soc-io.c
 691 @@ -19,7 +19,6 @@
 692
 693  #include <trace/events/asoc.h>
 694
 695 -#ifdef CONFIG_REGMAP
 696  static int hw_write(struct snd_soc_codec *codec, unsigned int reg,
 697                     unsigned int value)
 698  {
 699 @@ -161,12 +160,3 @@ int snd_soc_codec_set_cache_io(struct sn
 700         return PTR_RET(codec->control_data);
 701  }
 702  EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
 703 -#else
 704 -int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
 705 -                              int addr_bits, int data_bits,
 706 -                              enum snd_soc_control_type control)
 707 -{
 708 -       return -ENOTSUPP;
 709 -}
 710 -EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
 711 -#endif