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ralink: refresh patches
[openwrt/staging/wigyori.git] / target / linux / ramips / patches-3.10 / 0113-pinctrl-ralink-add-pinctrl-driver.patch
1 From 47bbf432252b39361728c7685292dc9f889e6537 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 19 Aug 2013 13:49:52 +0200
4 Subject: [PATCH 113/133] pinctrl: ralink: add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
10 arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
11 arch/mips/include/asm/mach-ralink/rt305x.h | 34 +-
12 arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
13 arch/mips/ralink/common.h | 19 --
14 arch/mips/ralink/mt7620.c | 161 ++++------
15 arch/mips/ralink/rt305x.c | 146 ++++-----
16 arch/mips/ralink/rt3883.c | 173 +++--------
17 drivers/pinctrl/Kconfig | 5 +
18 drivers/pinctrl/Makefile | 1 +
19 drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
20 12 files changed, 740 insertions(+), 378 deletions(-)
21 create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
22 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
23
24 --- a/arch/mips/Kconfig
25 +++ b/arch/mips/Kconfig
26 @@ -446,6 +446,8 @@ config RALINK
27 select HAVE_MACH_CLKDEV
28 select CLKDEV_LOOKUP
29 select ARCH_REQUIRE_GPIOLIB
30 + select PINCTRL
31 + select PINCTRL_RT2880
32
33 config SGI_IP22
34 bool "SGI IP22 (Indy/Indigo2)"
35 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
36 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
37 @@ -56,7 +56,6 @@
38 #define MT7620_DDR2_SIZE_MIN 32
39 #define MT7620_DDR2_SIZE_MAX 256
40
41 -#define MT7620_GPIO_MODE_I2C BIT(0)
42 #define MT7620_GPIO_MODE_UART0_SHIFT 2
43 #define MT7620_GPIO_MODE_UART0_MASK 0x7
44 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
45 @@ -68,16 +67,36 @@
46 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
47 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
48 #define MT7620_GPIO_MODE_GPIO 0x7
49 -#define MT7620_GPIO_MODE_UART1 BIT(5)
50 -#define MT7620_GPIO_MODE_MDIO BIT(8)
51 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
52 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
53 -#define MT7620_GPIO_MODE_SPI BIT(11)
54 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
55 -#define MT7620_GPIO_MODE_WLED BIT(13)
56 -#define MT7620_GPIO_MODE_JTAG BIT(15)
57 -#define MT7620_GPIO_MODE_EPHY BIT(15)
58 -#define MT7620_GPIO_MODE_WDT BIT(22)
59 +
60 +#define MT7620_GPIO_MODE_NAND 0
61 +#define MT7620_GPIO_MODE_SD 1
62 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2
63 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
64 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
65 +
66 +#define MT7620_GPIO_MODE_PCIE_RST 0
67 +#define MT7620_GPIO_MODE_PCIE_REF 1
68 +#define MT7620_GPIO_MODE_PCIE_GPIO 2
69 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3
70 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16
71 +
72 +#define MT7620_GPIO_MODE_WDT_RST 0
73 +#define MT7620_GPIO_MODE_WDT_REF 1
74 +#define MT7620_GPIO_MODE_WDT_GPIO 2
75 +#define MT7620_GPIO_MODE_WDT_MASK 0x3
76 +#define MT7620_GPIO_MODE_WDT_SHIFT 21
77 +
78 +#define MT7620_GPIO_MODE_I2C 0
79 +#define MT7620_GPIO_MODE_UART1 5
80 +#define MT7620_GPIO_MODE_MDIO 8
81 +#define MT7620_GPIO_MODE_RGMII1 9
82 +#define MT7620_GPIO_MODE_RGMII2 10
83 +#define MT7620_GPIO_MODE_SPI 11
84 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
85 +#define MT7620_GPIO_MODE_WLED 13
86 +#define MT7620_GPIO_MODE_JTAG 15
87 +#define MT7620_GPIO_MODE_EPHY 15
88 +#define MT7620_GPIO_MODE_PA 20
89
90 static inline int mt7620_get_eco(void)
91 {
92 --- /dev/null
93 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
94 @@ -0,0 +1,53 @@
95 +/*
96 + * This program is free software; you can redistribute it and/or modify
97 + * it under the terms of the GNU General Public License version 2 as
98 + * publishhed by the Free Software Foundation.
99 + *
100 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
101 + */
102 +
103 +#ifndef _RT288X_PINMUX_H__
104 +#define _RT288X_PINMUX_H__
105 +
106 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
107 +#define GRP(_name, _func, _mask, _shift) \
108 + { .name = _name, .mask = _mask, .shift = _shift, \
109 + .func = _func, .gpio = _mask, \
110 + .func_count = ARRAY_SIZE(_func) }
111 +
112 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
113 + { .name = _name, .mask = _mask, .shift = _shift, \
114 + .func = _func, .gpio = _gpio, \
115 + .func_count = ARRAY_SIZE(_func) }
116 +
117 +struct rt2880_pmx_group;
118 +
119 +struct rt2880_pmx_func {
120 + const char *name;
121 + const char value;
122 +
123 + int pin_first;
124 + int pin_count;
125 + int *pins;
126 +
127 + int *groups;
128 + int group_count;
129 +
130 + int enabled;
131 +};
132 +
133 +struct rt2880_pmx_group {
134 + const char *name;
135 + int enabled;
136 +
137 + const u32 shift;
138 + const char mask;
139 + const char gpio;
140 +
141 + struct rt2880_pmx_func *func;
142 + int func_count;
143 +};
144 +
145 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
146 +
147 +#endif
148 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
149 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
150 @@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
151 #define RT305X_GPIO_GE0_TXD0 40
152 #define RT305X_GPIO_GE0_RXCLK 51
153
154 -#define RT305X_GPIO_MODE_I2C BIT(0)
155 -#define RT305X_GPIO_MODE_SPI BIT(1)
156 #define RT305X_GPIO_MODE_UART0_SHIFT 2
157 #define RT305X_GPIO_MODE_UART0_MASK 0x7
158 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
159 -#define RT305X_GPIO_MODE_UARTF 0x0
160 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
161 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
162 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
163 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
164 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
165 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
166 -#define RT305X_GPIO_MODE_GPIO 0x7
167 -#define RT305X_GPIO_MODE_UART1 BIT(5)
168 -#define RT305X_GPIO_MODE_JTAG BIT(6)
169 -#define RT305X_GPIO_MODE_MDIO BIT(7)
170 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
171 -#define RT305X_GPIO_MODE_RGMII BIT(9)
172 +#define RT305X_GPIO_MODE_UARTF 0
173 +#define RT305X_GPIO_MODE_PCM_UARTF 1
174 +#define RT305X_GPIO_MODE_PCM_I2S 2
175 +#define RT305X_GPIO_MODE_I2S_UARTF 3
176 +#define RT305X_GPIO_MODE_PCM_GPIO 4
177 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
178 +#define RT305X_GPIO_MODE_GPIO_I2S 6
179 +#define RT305X_GPIO_MODE_GPIO 7
180 +
181 +#define RT305X_GPIO_MODE_I2C 0
182 +#define RT305X_GPIO_MODE_SPI 1
183 +#define RT305X_GPIO_MODE_UART1 5
184 +#define RT305X_GPIO_MODE_JTAG 6
185 +#define RT305X_GPIO_MODE_MDIO 7
186 +#define RT305X_GPIO_MODE_SDRAM 8
187 +#define RT305X_GPIO_MODE_RGMII 9
188 +#define RT5350_GPIO_MODE_PHY_LED 14
189 +#define RT3352_GPIO_MODE_LNA 18
190 +#define RT3352_GPIO_MODE_PA 20
191
192 #define RT3352_SYSC_REG_SYSCFG0 0x010
193 #define RT3352_SYSC_REG_SYSCFG1 0x014
194 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
195 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
196 @@ -112,8 +112,6 @@
197 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
198 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
199
200 -#define RT3883_GPIO_MODE_I2C BIT(0)
201 -#define RT3883_GPIO_MODE_SPI BIT(1)
202 #define RT3883_GPIO_MODE_UART0_SHIFT 2
203 #define RT3883_GPIO_MODE_UART0_MASK 0x7
204 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
205 @@ -125,11 +123,15 @@
206 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
207 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
208 #define RT3883_GPIO_MODE_GPIO 0x7
209 -#define RT3883_GPIO_MODE_UART1 BIT(5)
210 -#define RT3883_GPIO_MODE_JTAG BIT(6)
211 -#define RT3883_GPIO_MODE_MDIO BIT(7)
212 -#define RT3883_GPIO_MODE_GE1 BIT(9)
213 -#define RT3883_GPIO_MODE_GE2 BIT(10)
214 +
215 +#define RT3883_GPIO_MODE_I2C 0
216 +#define RT3883_GPIO_MODE_SPI 1
217 +#define RT3883_GPIO_MODE_UART1 5
218 +#define RT3883_GPIO_MODE_JTAG 6
219 +#define RT3883_GPIO_MODE_MDIO 7
220 +#define RT3883_GPIO_MODE_GE1 9
221 +#define RT3883_GPIO_MODE_GE2 10
222 +
223 #define RT3883_GPIO_MODE_PCI_SHIFT 11
224 #define RT3883_GPIO_MODE_PCI_MASK 0x7
225 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
226 --- a/arch/mips/ralink/common.h
227 +++ b/arch/mips/ralink/common.h
228 @@ -11,25 +11,6 @@
229
230 #define RAMIPS_SYS_TYPE_LEN 32
231
232 -struct ralink_pinmux_grp {
233 - const char *name;
234 - u32 mask;
235 - int gpio_first;
236 - int gpio_last;
237 -};
238 -
239 -struct ralink_pinmux {
240 - struct ralink_pinmux_grp *mode;
241 - struct ralink_pinmux_grp *uart;
242 - int uart_shift;
243 - u32 uart_mask;
244 - void (*wdt_reset)(void);
245 - struct ralink_pinmux_grp *pci;
246 - int pci_shift;
247 - u32 pci_mask;
248 -};
249 -extern struct ralink_pinmux rt_gpio_pinmux;
250 -
251 struct ralink_soc_info {
252 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
253 unsigned char *compatible;
254 --- a/arch/mips/ralink/mt7620.c
255 +++ b/arch/mips/ralink/mt7620.c
256 @@ -17,6 +17,7 @@
257 #include <asm/mipsregs.h>
258 #include <asm/mach-ralink/ralink_regs.h>
259 #include <asm/mach-ralink/mt7620.h>
260 +#include <asm/mach-ralink/pinmux.h>
261
262 #include "common.h"
263
264 @@ -48,118 +49,58 @@ static int dram_type;
265 /* the pll dividers */
266 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
267
268 -static struct ralink_pinmux_grp mode_mux[] = {
269 - {
270 - .name = "i2c",
271 - .mask = MT7620_GPIO_MODE_I2C,
272 - .gpio_first = 1,
273 - .gpio_last = 2,
274 - }, {
275 - .name = "spi",
276 - .mask = MT7620_GPIO_MODE_SPI,
277 - .gpio_first = 3,
278 - .gpio_last = 6,
279 - }, {
280 - .name = "uartlite",
281 - .mask = MT7620_GPIO_MODE_UART1,
282 - .gpio_first = 15,
283 - .gpio_last = 16,
284 - }, {
285 - .name = "wdt",
286 - .mask = MT7620_GPIO_MODE_WDT,
287 - .gpio_first = 17,
288 - .gpio_last = 17,
289 - }, {
290 - .name = "mdio",
291 - .mask = MT7620_GPIO_MODE_MDIO,
292 - .gpio_first = 22,
293 - .gpio_last = 23,
294 - }, {
295 - .name = "rgmii1",
296 - .mask = MT7620_GPIO_MODE_RGMII1,
297 - .gpio_first = 24,
298 - .gpio_last = 35,
299 - }, {
300 - .name = "spi refclk",
301 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
302 - .gpio_first = 37,
303 - .gpio_last = 39,
304 - }, {
305 - .name = "jtag",
306 - .mask = MT7620_GPIO_MODE_JTAG,
307 - .gpio_first = 40,
308 - .gpio_last = 44,
309 - }, {
310 - /* shared lines with jtag */
311 - .name = "ephy",
312 - .mask = MT7620_GPIO_MODE_EPHY,
313 - .gpio_first = 40,
314 - .gpio_last = 44,
315 - }, {
316 - .name = "nand",
317 - .mask = MT7620_GPIO_MODE_JTAG,
318 - .gpio_first = 45,
319 - .gpio_last = 59,
320 - }, {
321 - .name = "rgmii2",
322 - .mask = MT7620_GPIO_MODE_RGMII2,
323 - .gpio_first = 60,
324 - .gpio_last = 71,
325 - }, {
326 - .name = "wled",
327 - .mask = MT7620_GPIO_MODE_WLED,
328 - .gpio_first = 72,
329 - .gpio_last = 72,
330 - }, {0}
331 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
332 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
333 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
334 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
335 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
336 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
337 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
338 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
339 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
340 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
341 +static struct rt2880_pmx_func uartf_grp[] = {
342 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
343 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
344 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
345 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
346 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
347 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
348 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
349 };
350 -
351 -static struct ralink_pinmux_grp uart_mux[] = {
352 - {
353 - .name = "uartf",
354 - .mask = MT7620_GPIO_MODE_UARTF,
355 - .gpio_first = 7,
356 - .gpio_last = 14,
357 - }, {
358 - .name = "pcm uartf",
359 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
360 - .gpio_first = 7,
361 - .gpio_last = 14,
362 - }, {
363 - .name = "pcm i2s",
364 - .mask = MT7620_GPIO_MODE_PCM_I2S,
365 - .gpio_first = 7,
366 - .gpio_last = 14,
367 - }, {
368 - .name = "i2s uartf",
369 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
370 - .gpio_first = 7,
371 - .gpio_last = 14,
372 - }, {
373 - .name = "pcm gpio",
374 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
375 - .gpio_first = 11,
376 - .gpio_last = 14,
377 - }, {
378 - .name = "gpio uartf",
379 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
380 - .gpio_first = 7,
381 - .gpio_last = 10,
382 - }, {
383 - .name = "gpio i2s",
384 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
385 - .gpio_first = 7,
386 - .gpio_last = 10,
387 - }, {
388 - .name = "gpio",
389 - .mask = MT7620_GPIO_MODE_GPIO,
390 - }, {0}
391 +static struct rt2880_pmx_func wdt_grp[] = {
392 + FUNC("wdt rst", 0, 17, 1),
393 + FUNC("wdt refclk", 0, 17, 1),
394 + };
395 +static struct rt2880_pmx_func pcie_rst_grp[] = {
396 + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
397 + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
398 +};
399 +static struct rt2880_pmx_func nd_sd_grp[] = {
400 + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
401 + FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
402 };
403
404 -struct ralink_pinmux rt_gpio_pinmux = {
405 - .mode = mode_mux,
406 - .uart = uart_mux,
407 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
408 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
409 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
410 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
411 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
412 + MT7620_GPIO_MODE_UART0_SHIFT),
413 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
414 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
415 + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
416 + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
417 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
418 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
419 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
420 + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
421 + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
422 + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
423 + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
424 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
425 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
426 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
427 + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
428 + { 0 }
429 };
430
431 void __init ralink_clk_init(void)
432 @@ -286,4 +227,6 @@ void prom_soc_init(struct ralink_soc_inf
433 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
434 pr_info("Digital PMU set to %s control\n",
435 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
436 +
437 + rt2880_pinmux_data = mt7620a_pinmux_data;
438 }
439 --- a/arch/mips/ralink/rt305x.c
440 +++ b/arch/mips/ralink/rt305x.c
441 @@ -17,90 +17,71 @@
442 #include <asm/mipsregs.h>
443 #include <asm/mach-ralink/ralink_regs.h>
444 #include <asm/mach-ralink/rt305x.h>
445 +#include <asm/mach-ralink/pinmux.h>
446
447 #include "common.h"
448
449 enum rt305x_soc_type rt305x_soc;
450
451 -static struct ralink_pinmux_grp mode_mux[] = {
452 - {
453 - .name = "i2c",
454 - .mask = RT305X_GPIO_MODE_I2C,
455 - .gpio_first = RT305X_GPIO_I2C_SD,
456 - .gpio_last = RT305X_GPIO_I2C_SCLK,
457 - }, {
458 - .name = "spi",
459 - .mask = RT305X_GPIO_MODE_SPI,
460 - .gpio_first = RT305X_GPIO_SPI_EN,
461 - .gpio_last = RT305X_GPIO_SPI_CLK,
462 - }, {
463 - .name = "uartlite",
464 - .mask = RT305X_GPIO_MODE_UART1,
465 - .gpio_first = RT305X_GPIO_UART1_TXD,
466 - .gpio_last = RT305X_GPIO_UART1_RXD,
467 - }, {
468 - .name = "jtag",
469 - .mask = RT305X_GPIO_MODE_JTAG,
470 - .gpio_first = RT305X_GPIO_JTAG_TDO,
471 - .gpio_last = RT305X_GPIO_JTAG_TDI,
472 - }, {
473 - .name = "mdio",
474 - .mask = RT305X_GPIO_MODE_MDIO,
475 - .gpio_first = RT305X_GPIO_MDIO_MDC,
476 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
477 - }, {
478 - .name = "sdram",
479 - .mask = RT305X_GPIO_MODE_SDRAM,
480 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
481 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
482 - }, {
483 - .name = "rgmii",
484 - .mask = RT305X_GPIO_MODE_RGMII,
485 - .gpio_first = RT305X_GPIO_GE0_TXD0,
486 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
487 - }, {0}
488 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
489 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
490 +static struct rt2880_pmx_func uartf_func[] = {
491 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
492 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
493 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
494 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
495 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
496 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
497 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
498 +};
499 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
500 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
501 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
502 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
503 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
504 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
505 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
506 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
507 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
508 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
509 +
510 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
511 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
512 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
513 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
514 + RT305X_GPIO_MODE_UART0_SHIFT),
515 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
516 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
517 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
518 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
519 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
520 + { 0 }
521 +};
522 +
523 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
524 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
525 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
526 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
527 + RT305X_GPIO_MODE_UART0_SHIFT),
528 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
529 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
530 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
531 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
532 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
533 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
534 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
535 + { 0 }
536 };
537
538 -static struct ralink_pinmux_grp uart_mux[] = {
539 - {
540 - .name = "uartf",
541 - .mask = RT305X_GPIO_MODE_UARTF,
542 - .gpio_first = RT305X_GPIO_7,
543 - .gpio_last = RT305X_GPIO_14,
544 - }, {
545 - .name = "pcm uartf",
546 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
547 - .gpio_first = RT305X_GPIO_7,
548 - .gpio_last = RT305X_GPIO_14,
549 - }, {
550 - .name = "pcm i2s",
551 - .mask = RT305X_GPIO_MODE_PCM_I2S,
552 - .gpio_first = RT305X_GPIO_7,
553 - .gpio_last = RT305X_GPIO_14,
554 - }, {
555 - .name = "i2s uartf",
556 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
557 - .gpio_first = RT305X_GPIO_7,
558 - .gpio_last = RT305X_GPIO_14,
559 - }, {
560 - .name = "pcm gpio",
561 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
562 - .gpio_first = RT305X_GPIO_10,
563 - .gpio_last = RT305X_GPIO_14,
564 - }, {
565 - .name = "gpio uartf",
566 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
567 - .gpio_first = RT305X_GPIO_7,
568 - .gpio_last = RT305X_GPIO_10,
569 - }, {
570 - .name = "gpio i2s",
571 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
572 - .gpio_first = RT305X_GPIO_7,
573 - .gpio_last = RT305X_GPIO_10,
574 - }, {
575 - .name = "gpio",
576 - .mask = RT305X_GPIO_MODE_GPIO,
577 - }, {0}
578 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
579 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
580 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
581 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
582 + RT305X_GPIO_MODE_UART0_SHIFT),
583 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
584 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
585 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
586 + { 0 }
587 };
588
589 static void rt305x_wdt_reset(void)
590 @@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
591 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
592 }
593
594 -struct ralink_pinmux rt_gpio_pinmux = {
595 - .mode = mode_mux,
596 - .uart = uart_mux,
597 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
598 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
599 - .wdt_reset = rt305x_wdt_reset,
600 -};
601 -
602 static unsigned long rt5350_get_mem_size(void)
603 {
604 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
605 @@ -290,11 +263,14 @@ void prom_soc_init(struct ralink_soc_inf
606 soc_info->mem_base = RT305X_SDRAM_BASE;
607 if (soc_is_rt5350()) {
608 soc_info->mem_size = rt5350_get_mem_size();
609 + rt2880_pinmux_data = rt5350_pinmux_data;
610 } else if (soc_is_rt305x() || soc_is_rt3350()) {
611 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
612 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
613 + rt2880_pinmux_data = rt3050_pinmux_data;
614 } else if (soc_is_rt3352()) {
615 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
616 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
617 + rt2880_pinmux_data = rt3352_pinmux_data;
618 }
619 }
620 --- a/arch/mips/ralink/rt3883.c
621 +++ b/arch/mips/ralink/rt3883.c
622 @@ -17,132 +17,50 @@
623 #include <asm/mipsregs.h>
624 #include <asm/mach-ralink/ralink_regs.h>
625 #include <asm/mach-ralink/rt3883.h>
626 +#include <asm/mach-ralink/pinmux.h>
627
628 #include "common.h"
629
630 -static struct ralink_pinmux_grp mode_mux[] = {
631 - {
632 - .name = "i2c",
633 - .mask = RT3883_GPIO_MODE_I2C,
634 - .gpio_first = RT3883_GPIO_I2C_SD,
635 - .gpio_last = RT3883_GPIO_I2C_SCLK,
636 - }, {
637 - .name = "spi",
638 - .mask = RT3883_GPIO_MODE_SPI,
639 - .gpio_first = RT3883_GPIO_SPI_CS0,
640 - .gpio_last = RT3883_GPIO_SPI_MISO,
641 - }, {
642 - .name = "uartlite",
643 - .mask = RT3883_GPIO_MODE_UART1,
644 - .gpio_first = RT3883_GPIO_UART1_TXD,
645 - .gpio_last = RT3883_GPIO_UART1_RXD,
646 - }, {
647 - .name = "jtag",
648 - .mask = RT3883_GPIO_MODE_JTAG,
649 - .gpio_first = RT3883_GPIO_JTAG_TDO,
650 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
651 - }, {
652 - .name = "mdio",
653 - .mask = RT3883_GPIO_MODE_MDIO,
654 - .gpio_first = RT3883_GPIO_MDIO_MDC,
655 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
656 - }, {
657 - .name = "ge1",
658 - .mask = RT3883_GPIO_MODE_GE1,
659 - .gpio_first = RT3883_GPIO_GE1_TXD0,
660 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
661 - }, {
662 - .name = "ge2",
663 - .mask = RT3883_GPIO_MODE_GE2,
664 - .gpio_first = RT3883_GPIO_GE2_TXD0,
665 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
666 - }, {
667 - .name = "pci",
668 - .mask = RT3883_GPIO_MODE_PCI,
669 - .gpio_first = RT3883_GPIO_PCI_AD0,
670 - .gpio_last = RT3883_GPIO_PCI_AD31,
671 - }, {
672 - .name = "lna a",
673 - .mask = RT3883_GPIO_MODE_LNA_A,
674 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
675 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
676 - }, {
677 - .name = "lna g",
678 - .mask = RT3883_GPIO_MODE_LNA_G,
679 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
680 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
681 - }, {0}
682 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
683 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
684 +static struct rt2880_pmx_func uartf_func[] = {
685 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
686 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
687 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
688 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
689 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
690 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
691 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
692 };
693 -
694 -static struct ralink_pinmux_grp uart_mux[] = {
695 - {
696 - .name = "uartf",
697 - .mask = RT3883_GPIO_MODE_UARTF,
698 - .gpio_first = RT3883_GPIO_7,
699 - .gpio_last = RT3883_GPIO_14,
700 - }, {
701 - .name = "pcm uartf",
702 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
703 - .gpio_first = RT3883_GPIO_7,
704 - .gpio_last = RT3883_GPIO_14,
705 - }, {
706 - .name = "pcm i2s",
707 - .mask = RT3883_GPIO_MODE_PCM_I2S,
708 - .gpio_first = RT3883_GPIO_7,
709 - .gpio_last = RT3883_GPIO_14,
710 - }, {
711 - .name = "i2s uartf",
712 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
713 - .gpio_first = RT3883_GPIO_7,
714 - .gpio_last = RT3883_GPIO_14,
715 - }, {
716 - .name = "pcm gpio",
717 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
718 - .gpio_first = RT3883_GPIO_11,
719 - .gpio_last = RT3883_GPIO_14,
720 - }, {
721 - .name = "gpio uartf",
722 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
723 - .gpio_first = RT3883_GPIO_7,
724 - .gpio_last = RT3883_GPIO_10,
725 - }, {
726 - .name = "gpio i2s",
727 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
728 - .gpio_first = RT3883_GPIO_7,
729 - .gpio_last = RT3883_GPIO_10,
730 - }, {
731 - .name = "gpio",
732 - .mask = RT3883_GPIO_MODE_GPIO,
733 - }, {0}
734 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
735 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
736 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
737 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
738 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
739 +static struct rt2880_pmx_func pci_func[] = {
740 + FUNC("pci-dev", 0, 40, 32),
741 + FUNC("pci-host2", 1, 40, 32),
742 + FUNC("pci-host1", 2, 40, 32),
743 + FUNC("pci-fnc", 3, 40, 32)
744 };
745 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
746 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
747
748 -static struct ralink_pinmux_grp pci_mux[] = {
749 - {
750 - .name = "pci-dev",
751 - .mask = 0,
752 - .gpio_first = RT3883_GPIO_PCI_AD0,
753 - .gpio_last = RT3883_GPIO_PCI_AD31,
754 - }, {
755 - .name = "pci-host2",
756 - .mask = 1,
757 - .gpio_first = RT3883_GPIO_PCI_AD0,
758 - .gpio_last = RT3883_GPIO_PCI_AD31,
759 - }, {
760 - .name = "pci-host1",
761 - .mask = 2,
762 - .gpio_first = RT3883_GPIO_PCI_AD0,
763 - .gpio_last = RT3883_GPIO_PCI_AD31,
764 - }, {
765 - .name = "pci-fnc",
766 - .mask = 3,
767 - .gpio_first = RT3883_GPIO_PCI_AD0,
768 - .gpio_last = RT3883_GPIO_PCI_AD31,
769 - }, {
770 - .name = "pci-gpio",
771 - .mask = 7,
772 - .gpio_first = RT3883_GPIO_PCI_AD0,
773 - .gpio_last = RT3883_GPIO_PCI_AD31,
774 - }, {0}
775 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
776 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
777 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
778 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
779 + RT3883_GPIO_MODE_UART0_SHIFT),
780 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
781 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
782 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
783 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
784 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
785 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
786 + RT3883_GPIO_MODE_PCI_SHIFT),
787 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
788 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
789 + { 0 }
790 };
791
792 static void rt3883_wdt_reset(void)
793 @@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
794 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
795 }
796
797 -struct ralink_pinmux rt_gpio_pinmux = {
798 - .mode = mode_mux,
799 - .uart = uart_mux,
800 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
801 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
802 - .wdt_reset = rt3883_wdt_reset,
803 - .pci = pci_mux,
804 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
805 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
806 -};
807 -
808 void __init ralink_clk_init(void)
809 {
810 unsigned long cpu_rate, sys_rate;
811 @@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
812 soc_info->mem_base = RT3883_SDRAM_BASE;
813 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
814 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
815 +
816 + rt2880_pinmux_data = rt3883_pinmux_data;
817 }
818 --- a/drivers/pinctrl/Kconfig
819 +++ b/drivers/pinctrl/Kconfig
820 @@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
821 select PINMUX
822 select PINCONF
823
824 +config PINCTRL_RT2880
825 + bool
826 + depends on RALINK
827 + select PINMUX
828 +
829 config PINCTRL_FALCON
830 bool
831 depends on SOC_FALCON
832 --- a/drivers/pinctrl/Makefile
833 +++ b/drivers/pinctrl/Makefile
834 @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinc
835 obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
836 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
837 obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
838 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
839
840 obj-$(CONFIG_PLAT_ORION) += mvebu/
841 obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
842 --- /dev/null
843 +++ b/drivers/pinctrl/pinctrl-rt2880.c
844 @@ -0,0 +1,467 @@
845 +/*
846 + * linux/drivers/pinctrl/pinctrl-rt2880.c
847 + *
848 + * This program is free software; you can redistribute it and/or modify
849 + * it under the terms of the GNU General Public License version 2 as
850 + * publishhed by the Free Software Foundation.
851 + *
852 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
853 + */
854 +
855 +#include <linux/module.h>
856 +#include <linux/device.h>
857 +#include <linux/io.h>
858 +#include <linux/platform_device.h>
859 +#include <linux/slab.h>
860 +#include <linux/of.h>
861 +#include <linux/pinctrl/pinctrl.h>
862 +#include <linux/pinctrl/pinconf.h>
863 +#include <linux/pinctrl/pinmux.h>
864 +#include <linux/pinctrl/consumer.h>
865 +#include <linux/pinctrl/machine.h>
866 +
867 +#include <asm/mach-ralink/ralink_regs.h>
868 +#include <asm/mach-ralink/pinmux.h>
869 +#include <asm/mach-ralink/mt7620.h>
870 +
871 +#include "core.h"
872 +
873 +#define SYSC_REG_GPIO_MODE 0x60
874 +
875 +struct rt2880_priv {
876 + struct device *dev;
877 +
878 + struct pinctrl_pin_desc *pads;
879 + struct pinctrl_desc *desc;
880 +
881 + struct rt2880_pmx_func **func;
882 + int func_count;
883 +
884 + struct rt2880_pmx_group *groups;
885 + const char **group_names;
886 + int group_count;
887 +
888 + uint8_t *gpio;
889 + int max_pins;
890 +};
891 +
892 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
893 +
894 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
895 +{
896 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
897 +
898 + return p->group_count;
899 +}
900 +
901 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
902 + unsigned group)
903 +{
904 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
905 +
906 + if (group >= p->group_count)
907 + return NULL;
908 +
909 + return p->group_names[group];
910 +}
911 +
912 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
913 + unsigned group,
914 + const unsigned **pins,
915 + unsigned *num_pins)
916 +{
917 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
918 +
919 + if (group >= p->group_count)
920 + return -EINVAL;
921 +
922 + *pins = p->groups[group].func[0].pins;
923 + *num_pins = p->groups[group].func[0].pin_count;
924 +
925 + return 0;
926 +}
927 +
928 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
929 + struct pinctrl_map *map, unsigned num_maps)
930 +{
931 + int i;
932 +
933 + for (i = 0; i < num_maps; i++)
934 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
935 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
936 + kfree(map[i].data.configs.configs);
937 + kfree(map);
938 +}
939 +
940 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
941 + struct seq_file *s,
942 + unsigned offset)
943 +{
944 + seq_printf(s, "ralink pio");
945 +}
946 +
947 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
948 + struct device_node *np,
949 + struct pinctrl_map **map)
950 +{
951 + const char *function;
952 + int func = of_property_read_string(np, "ralink,function", &function);
953 + int grps = of_property_count_strings(np, "ralink,group");
954 + int i;
955 +
956 + if (func || !grps)
957 + return;
958 +
959 + for (i = 0; i < grps; i++) {
960 + const char *group;
961 +
962 + of_property_read_string_index(np, "ralink,group", i, &group);
963 +
964 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
965 + (*map)->name = function;
966 + (*map)->data.mux.group = group;
967 + (*map)->data.mux.function = function;
968 + (*map)++;
969 + }
970 +}
971 +
972 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
973 + struct device_node *np_config,
974 + struct pinctrl_map **map,
975 + unsigned *num_maps)
976 +{
977 + int max_maps = 0;
978 + struct pinctrl_map *tmp;
979 + struct device_node *np;
980 +
981 + for_each_child_of_node(np_config, np) {
982 + int ret = of_property_count_strings(np, "ralink,group");
983 +
984 + if (ret >= 0)
985 + max_maps += ret;
986 + }
987 +
988 + if (!max_maps)
989 + return max_maps;
990 +
991 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
992 + if (!*map)
993 + return -ENOMEM;
994 +
995 + tmp = *map;
996 +
997 + for_each_child_of_node(np_config, np)
998 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
999 + *num_maps = max_maps;
1000 +
1001 + return 0;
1002 +}
1003 +
1004 +static const struct pinctrl_ops rt2880_pctrl_ops = {
1005 + .get_groups_count = rt2880_get_group_count,
1006 + .get_group_name = rt2880_get_group_name,
1007 + .get_group_pins = rt2880_get_group_pins,
1008 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
1009 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
1010 + .dt_free_map = rt2880_pinctrl_dt_free_map,
1011 +};
1012 +
1013 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
1014 +{
1015 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1016 +
1017 + return p->func_count;
1018 +}
1019 +
1020 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
1021 + unsigned func)
1022 +{
1023 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1024 +
1025 + return p->func[func]->name;
1026 +}
1027 +
1028 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
1029 + unsigned func,
1030 + const char * const **groups,
1031 + unsigned * const num_groups)
1032 +{
1033 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1034 +
1035 + if (p->func[func]->group_count == 1)
1036 + *groups = &p->group_names[p->func[func]->groups[0]];
1037 + else
1038 + *groups = p->group_names;
1039 +
1040 + *num_groups = p->func[func]->group_count;
1041 +
1042 + return 0;
1043 +}
1044 +
1045 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
1046 + unsigned func,
1047 + unsigned group)
1048 +{
1049 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1050 + u32 mode = 0;
1051 + int i;
1052 +
1053 + /* dont allow double use */
1054 + if (p->groups[group].enabled) {
1055 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
1056 + return -EBUSY;
1057 + }
1058 +
1059 + p->groups[group].enabled = 1;
1060 + p->func[func]->enabled = 1;
1061 +
1062 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
1063 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
1064 +
1065 + /* mark the pins as gpio */
1066 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
1067 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
1068 +
1069 + /* function 0 is gpio and needs special handling */
1070 + if (func == 0) {
1071 + mode |= p->groups[group].gpio << p->groups[group].shift;
1072 + } else {
1073 + for (i = 0; i < p->func[func]->pin_count; i++)
1074 + p->gpio[p->func[func]->pins[i]] = 0;
1075 + mode |= p->func[func]->value << p->groups[group].shift;
1076 + }
1077 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
1078 +
1079 +
1080 + return 0;
1081 +}
1082 +
1083 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
1084 + struct pinctrl_gpio_range *range,
1085 + unsigned pin)
1086 +{
1087 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1088 +
1089 + if (!p->gpio[pin]) {
1090 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
1091 + return -EINVAL;
1092 + }
1093 +
1094 + return 0;
1095 +}
1096 +
1097 +static const struct pinmux_ops rt2880_pmx_group_ops = {
1098 + .get_functions_count = rt2880_pmx_func_count,
1099 + .get_function_name = rt2880_pmx_func_name,
1100 + .get_function_groups = rt2880_pmx_group_get_groups,
1101 + .enable = rt2880_pmx_group_enable,
1102 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
1103 +};
1104 +
1105 +static struct pinctrl_desc rt2880_pctrl_desc = {
1106 + .owner = THIS_MODULE,
1107 + .name = "rt2880-pinmux",
1108 + .pctlops = &rt2880_pctrl_ops,
1109 + .pmxops = &rt2880_pmx_group_ops,
1110 +};
1111 +
1112 +static struct rt2880_pmx_func gpio_func = {
1113 + .name = "gpio",
1114 +};
1115 +
1116 +static int rt2880_pinmux_index(struct rt2880_priv *p)
1117 +{
1118 + struct rt2880_pmx_func **f;
1119 + struct rt2880_pmx_group *mux = p->groups;
1120 + int i, j, c = 0;
1121 +
1122 + /* count the mux functions */
1123 + while (mux->name) {
1124 + p->group_count++;
1125 + mux++;
1126 + }
1127 +
1128 + /* allocate the group names array needed by the gpio function */
1129 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
1130 + if (!p->group_names)
1131 + return -1;
1132 +
1133 + for (i = 0; i < p->group_count; i++) {
1134 + p->group_names[i] = p->groups[i].name;
1135 + p->func_count += p->groups[i].func_count;
1136 + }
1137 +
1138 + /* we have a dummy function[0] for gpio */
1139 + p->func_count++;
1140 +
1141 + /* allocate our function and group mapping index buffers */
1142 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
1143 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
1144 + if (!f || !gpio_func.groups)
1145 + return -1;
1146 +
1147 + /* add a backpointer to the function so it knows its group */
1148 + gpio_func.group_count = p->group_count;
1149 + for (i = 0; i < gpio_func.group_count; i++)
1150 + gpio_func.groups[i] = i;
1151 +
1152 + f[c] = &gpio_func;
1153 + c++;
1154 +
1155 + /* add remaining functions */
1156 + for (i = 0; i < p->group_count; i++) {
1157 + for (j = 0; j < p->groups[i].func_count; j++) {
1158 + f[c] = &p->groups[i].func[j];
1159 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
1160 + f[c]->groups[0] = i;
1161 + f[c]->group_count = 1;
1162 + c++;
1163 + }
1164 + }
1165 + return 0;
1166 +}
1167 +
1168 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
1169 +{
1170 + int i, j;
1171 +
1172 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
1173 + for (i = 0; i < p->func_count; i++) {
1174 + int pin;
1175 +
1176 + if (!p->func[i]->pin_count)
1177 + continue;
1178 +
1179 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
1180 + for (j = 0; j < p->func[i]->pin_count; j++)
1181 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
1182 +
1183 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
1184 + if (pin > p->max_pins)
1185 + p->max_pins = pin;
1186 + }
1187 +
1188 + /* the buffer that tells us which pins are gpio */
1189 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
1190 + GFP_KERNEL);
1191 + /* the pads needed to tell pinctrl about our pins */
1192 + p->pads = devm_kzalloc(p->dev,
1193 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
1194 + GFP_KERNEL);
1195 + if (!p->pads || !p->gpio ) {
1196 + dev_err(p->dev, "Failed to allocate gpio data\n");
1197 + return -ENOMEM;
1198 + }
1199 +
1200 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
1201 + for (i = 0; i < p->func_count; i++) {
1202 + if (!p->func[i]->pin_count)
1203 + continue;
1204 +
1205 + for (j = 0; j < p->func[i]->pin_count; j++)
1206 + p->gpio[p->func[i]->pins[j]] = 0;
1207 + }
1208 +
1209 + /* pin 0 is always a gpio */
1210 + p->gpio[0] = 1;
1211 +
1212 + /* set the pads */
1213 + for (i = 0; i < p->max_pins; i++) {
1214 + /* strlen("ioXY") + 1 = 5 */
1215 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
1216 +
1217 + if (!name) {
1218 + dev_err(p->dev, "Failed to allocate pad name\n");
1219 + return -ENOMEM;
1220 + }
1221 + snprintf(name, 5, "io%d", i);
1222 + p->pads[i].number = i;
1223 + p->pads[i].name = name;
1224 + }
1225 + p->desc->pins = p->pads;
1226 + p->desc->npins = p->max_pins;
1227 +
1228 + return 0;
1229 +}
1230 +
1231 +static int rt2880_pinmux_probe(struct platform_device *pdev)
1232 +{
1233 + struct rt2880_priv *p;
1234 + struct pinctrl_dev *dev;
1235 + struct device_node *np;
1236 +
1237 + if (!rt2880_pinmux_data)
1238 + return -ENOSYS;
1239 +
1240 + /* setup the private data */
1241 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
1242 + if (!p)
1243 + return -ENOMEM;
1244 +
1245 + p->dev = &pdev->dev;
1246 + p->desc = &rt2880_pctrl_desc;
1247 + p->groups = rt2880_pinmux_data;
1248 + platform_set_drvdata(pdev, p);
1249 +
1250 + /* init the device */
1251 + if (rt2880_pinmux_index(p)) {
1252 + dev_err(&pdev->dev, "failed to load index\n");
1253 + return -EINVAL;
1254 + }
1255 + if (rt2880_pinmux_pins(p)) {
1256 + dev_err(&pdev->dev, "failed to load pins\n");
1257 + return -EINVAL;
1258 + }
1259 + dev = pinctrl_register(p->desc, &pdev->dev, p);
1260 + if (IS_ERR(dev))
1261 + return PTR_ERR(dev);
1262 +
1263 + /* finalize by adding gpio ranges for enables gpio controllers */
1264 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
1265 + const __be32 *ngpio, *gpiobase;
1266 + struct pinctrl_gpio_range *range;
1267 + char *name;
1268 +
1269 + if (!of_device_is_available(np))
1270 + continue;
1271 +
1272 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
1273 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
1274 + if (!ngpio || !gpiobase) {
1275 + dev_err(&pdev->dev, "failed to load chip info\n");
1276 + return -EINVAL;
1277 + }
1278 +
1279 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
1280 + range->name = name = (char *) &range[1];
1281 + sprintf(name, "pio");
1282 + range->npins = __be32_to_cpu(*ngpio);
1283 + range->base = __be32_to_cpu(*gpiobase);
1284 + range->pin_base = range->base;
1285 + pinctrl_add_gpio_range(dev, range);
1286 + }
1287 +
1288 + return 0;
1289 +}
1290 +
1291 +static const struct of_device_id rt2880_pinmux_match[] = {
1292 + { .compatible = "ralink,rt2880-pinmux" },
1293 + {},
1294 +};
1295 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
1296 +
1297 +static struct platform_driver rt2880_pinmux_driver = {
1298 + .probe = rt2880_pinmux_probe,
1299 + .driver = {
1300 + .name = "rt2880-pinmux",
1301 + .owner = THIS_MODULE,
1302 + .of_match_table = rt2880_pinmux_match,
1303 + },
1304 +};
1305 +
1306 +int __init rt2880_pinmux_init(void)
1307 +{
1308 + return platform_driver_register(&rt2880_pinmux_driver);
1309 +}
1310 +
1311 +core_initcall_sync(rt2880_pinmux_init);
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