target/linux/ramips/patches-3.10/0122-pinmux.patch

   1 From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 19 Aug 2013 13:49:52 +0200
   4 Subject: [PATCH] pinctrl: ralink; add pinctrl driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/Kconfig                 |    2 +
   9  arch/mips/ralink/common.h         |   21 +--
  10  arch/mips/ralink/dts/mt7620a.dtsi |    7 +
  11  drivers/pinctrl/Kconfig           |    5 +
  12  drivers/pinctrl/Makefile          |    1 +
  13  drivers/pinctrl/pinctrl-rt2880.c  |  368 +++++++++++++++++++++++++++++++++++++
  14  6 files changed, 385 insertions(+), 19 deletions(-)
  15  create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
  16
  17 --- a/arch/mips/Kconfig
  18 +++ b/arch/mips/Kconfig
  19 @@ -446,6 +446,8 @@ config RALINK
  20         select HAVE_MACH_CLKDEV
  21         select CLKDEV_LOOKUP
  22         select ARCH_REQUIRE_GPIOLIB
  23 +       select PINCTRL
  24 +       select PINCTRL_RT2880
  25
  26  config SGI_IP22
  27         bool "SGI IP22 (Indy/Indigo2)"
  28 --- a/drivers/pinctrl/Kconfig
  29 +++ b/drivers/pinctrl/Kconfig
  30 @@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
  31         select PINMUX
  32         select PINCONF
  33
  34 +config PINCTRL_RT2880
  35 +       bool
  36 +       depends on RALINK
  37 +       select PINMUX
  38 +
  39  config PINCTRL_FALCON
  40         bool
  41         depends on SOC_FALCON
  42 --- a/drivers/pinctrl/Makefile
  43 +++ b/drivers/pinctrl/Makefile
  44 @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)      += pinc
  45  obj-$(CONFIG_PINCTRL_S3C64XX)  += pinctrl-s3c64xx.o
  46  obj-$(CONFIG_PINCTRL_XWAY)     += pinctrl-xway.o
  47  obj-$(CONFIG_PINCTRL_LANTIQ)   += pinctrl-lantiq.o
  48 +obj-$(CONFIG_PINCTRL_RT2880)   += pinctrl-rt2880.o
  49
  50  obj-$(CONFIG_PLAT_ORION)        += mvebu/
  51  obj-$(CONFIG_ARCH_SHMOBILE)    += sh-pfc/
  52 --- /dev/null
  53 +++ b/drivers/pinctrl/pinctrl-rt2880.c
  54 @@ -0,0 +1,466 @@
  55 +/*
  56 + *  linux/drivers/pinctrl/pinctrl-rt2880.c
  57 + *
  58 + *  This program is free software; you can redistribute it and/or modify
  59 + *  it under the terms of the GNU General Public License version 2 as
  60 + *  publishhed by the Free Software Foundation.
  61 + *
  62 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  63 + */
  64 +
  65 +#include <linux/module.h>
  66 +#include <linux/device.h>
  67 +#include <linux/io.h>
  68 +#include <linux/platform_device.h>
  69 +#include <linux/slab.h>
  70 +#include <linux/of.h>
  71 +#include <linux/pinctrl/pinctrl.h>
  72 +#include <linux/pinctrl/pinconf.h>
  73 +#include <linux/pinctrl/pinmux.h>
  74 +#include <linux/pinctrl/consumer.h>
  75 +#include <linux/pinctrl/machine.h>
  76 +
  77 +#include <asm/mach-ralink/ralink_regs.h>
  78 +#include <asm/mach-ralink/pinmux.h>
  79 +#include <asm/mach-ralink/mt7620.h>
  80 +
  81 +#include "core.h"
  82 +
  83 +#define SYSC_REG_GPIO_MODE     0x60
  84 +
  85 +struct rt2880_priv {
  86 +       struct device *dev;
  87 +
  88 +       struct pinctrl_pin_desc *pads;
  89 +       struct pinctrl_desc *desc;
  90 +
  91 +       struct rt2880_pmx_func **func;
  92 +       int func_count;
  93 +
  94 +       struct rt2880_pmx_group *groups;
  95 +       const char **group_names;
  96 +       int group_count;
  97 +
  98 +       uint8_t *gpio;
  99 +       int max_pins;
 100 +};
 101 +
 102 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
 103 +
 104 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
 105 +{
 106 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 107 +
 108 +       return p->group_count;
 109 +}
 110 +
 111 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
 112 +                                        unsigned group)
 113 +{
 114 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 115 +
 116 +       if (group >= p->group_count)
 117 +               return NULL;
 118 +
 119 +       return p->group_names[group];
 120 +}
 121 +
 122 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
 123 +                                unsigned group,
 124 +                                const unsigned **pins,
 125 +                                unsigned *num_pins)
 126 +{
 127 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 128 +
 129 +       if (group >= p->group_count)
 130 +               return -EINVAL;
 131 +
 132 +       *pins = p->groups[group].func[0].pins;
 133 +       *num_pins = p->groups[group].func[0].pin_count;
 134 +
 135 +       return 0;
 136 +}
 137 +
 138 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
 139 +                                   struct pinctrl_map *map, unsigned num_maps)
 140 +{
 141 +       int i;
 142 +
 143 +       for (i = 0; i < num_maps; i++)
 144 +               if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
 145 +                   map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 146 +                       kfree(map[i].data.configs.configs);
 147 +       kfree(map);
 148 +}
 149 +
 150 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
 151 +                                       struct seq_file *s,
 152 +                                       unsigned offset)
 153 +{
 154 +       seq_printf(s, "ralink pio");
 155 +}
 156 +
 157 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
 158 +                               struct device_node *np,
 159 +                               struct pinctrl_map **map)
 160 +{
 161 +        const char *function;
 162 +       int func = of_property_read_string(np, "ralink,function", &function);
 163 +       int grps = of_property_count_strings(np, "ralink,group");
 164 +       int i;
 165 +
 166 +       if (func || !grps)
 167 +               return;
 168 +
 169 +       for (i = 0; i < grps; i++) {
 170 +               const char *group;
 171 +
 172 +               of_property_read_string_index(np, "ralink,group", i, &group);
 173 +
 174 +               (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
 175 +               (*map)->name = function;
 176 +               (*map)->data.mux.group = group;
 177 +               (*map)->data.mux.function = function;
 178 +               (*map)++;
 179 +       }
 180 +}
 181 +
 182 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
 183 +                               struct device_node *np_config,
 184 +                               struct pinctrl_map **map,
 185 +                               unsigned *num_maps)
 186 +{
 187 +       int max_maps = 0;
 188 +       struct pinctrl_map *tmp;
 189 +       struct device_node *np;
 190 +
 191 +       for_each_child_of_node(np_config, np) {
 192 +               int ret = of_property_count_strings(np, "ralink,group");
 193 +
 194 +               if (ret >= 0)
 195 +                       max_maps += ret;
 196 +       }
 197 +
 198 +       if (!max_maps)
 199 +               return max_maps;
 200 +
 201 +       *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
 202 +       if (!*map)
 203 +               return -ENOMEM;
 204 +
 205 +       tmp = *map;
 206 +
 207 +       for_each_child_of_node(np_config, np)
 208 +               rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
 209 +       *num_maps = max_maps;
 210 +
 211 +       return 0;
 212 +}
 213 +
 214 +static const struct pinctrl_ops rt2880_pctrl_ops = {
 215 +       .get_groups_count       = rt2880_get_group_count,
 216 +       .get_group_name         = rt2880_get_group_name,
 217 +       .get_group_pins         = rt2880_get_group_pins,
 218 +       .pin_dbg_show           = rt2880_pinctrl_pin_dbg_show,
 219 +       .dt_node_to_map         = rt2880_pinctrl_dt_node_to_map,
 220 +       .dt_free_map            = rt2880_pinctrl_dt_free_map,
 221 +};
 222 +
 223 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
 224 +{
 225 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 226 +
 227 +       return p->func_count;
 228 +}
 229 +
 230 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
 231 +                                        unsigned func)
 232 +{
 233 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 234 +
 235 +       return p->func[func]->name;
 236 +}
 237 +
 238 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
 239 +                               unsigned func,
 240 +                               const char * const **groups,
 241 +                               unsigned * const num_groups)
 242 +{
 243 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 244 +
 245 +       if (p->func[func]->group_count == 1)
 246 +               *groups = &p->group_names[p->func[func]->groups[0]];
 247 +       else
 248 +               *groups = p->group_names;
 249 +
 250 +       *num_groups = p->func[func]->group_count;
 251 +
 252 +       return 0;
 253 +}
 254 +
 255 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
 256 +                               unsigned func,
 257 +                               unsigned group)
 258 +{
 259 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 260 +        u32 mode = 0;
 261 +
 262 +       /* dont allow double use */
 263 +       if (p->groups[group].enabled) {
 264 +               dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
 265 +               return -EBUSY;
 266 +       }
 267 +
 268 +       p->groups[group].enabled = 1;
 269 +       p->func[func]->enabled = 1;
 270 +
 271 +       mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
 272 +       mode &= ~(p->groups[group].mask << p->groups[group].shift);
 273 +
 274 +       /* function 0 is gpio and needs special handling */
 275 +       if (func == 0) {
 276 +               int i;
 277 +
 278 +
 279 +               mode |= p->groups[group].gpio << p->groups[group].shift;
 280 +               /* mark the pins as gpio */
 281 +               for (i = 0; i < p->groups[group].func[0].pin_count; i++)
 282 +                       p->gpio[p->groups[group].func[0].pins[i]] = 1;
 283 +       } else {
 284 +               mode |= p->func[func]->value << p->groups[group].shift;
 285 +       }
 286 +       rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
 287 +
 288 +
 289 +       return 0;
 290 +}
 291 +
 292 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
 293 +                               struct pinctrl_gpio_range *range,
 294 +                               unsigned pin)
 295 +{
 296 +       struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
 297 +
 298 +       if (!p->gpio[pin]) {
 299 +               dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
 300 +               return -EINVAL;
 301 +       }
 302 +
 303 +       return 0;
 304 +}
 305 +
 306 +static const struct pinmux_ops rt2880_pmx_group_ops = {
 307 +       .get_functions_count    = rt2880_pmx_func_count,
 308 +       .get_function_name      = rt2880_pmx_func_name,
 309 +       .get_function_groups    = rt2880_pmx_group_get_groups,
 310 +       .enable                 = rt2880_pmx_group_enable,
 311 +       .gpio_request_enable    = rt2880_pmx_group_gpio_request_enable,
 312 +};
 313 +
 314 +static struct pinctrl_desc rt2880_pctrl_desc = {
 315 +       .owner          = THIS_MODULE,
 316 +       .name           = "rt2880-pinmux",
 317 +       .pctlops        = &rt2880_pctrl_ops,
 318 +       .pmxops         = &rt2880_pmx_group_ops,
 319 +};
 320 +
 321 +static struct rt2880_pmx_func gpio_func = {
 322 +       .name = "gpio",
 323 +};
 324 +
 325 +static int rt2880_pinmux_index(struct rt2880_priv *p)
 326 +{
 327 +       struct rt2880_pmx_func **f;
 328 +       struct rt2880_pmx_group *mux = p->groups;
 329 +       int i, j, c = 0;
 330 +
 331 +       /* count the mux functions */
 332 +       while (mux->name) {
 333 +               p->group_count++;
 334 +               mux++;
 335 +       }
 336 +
 337 +       /* allocate the group names array needed by the gpio function */
 338 +       p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
 339 +       if (!p->group_names)
 340 +               return -1;
 341 +
 342 +       for (i = 0; i < p->group_count; i++) {
 343 +               p->group_names[i] = p->groups[i].name;
 344 +               p->func_count += p->groups[i].func_count;
 345 +       }
 346 +
 347 +       /* we have a dummy function[0] for gpio */
 348 +       p->func_count++;
 349 +
 350 +       /* allocate our function and group mapping index buffers */
 351 +       f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
 352 +       gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
 353 +       if (!f || !gpio_func.groups)
 354 +               return -1;
 355 +
 356 +       /* add a backpointer to the function so it knows its group */
 357 +       gpio_func.group_count = p->group_count;
 358 +       for (i = 0; i < gpio_func.group_count; i++)
 359 +               gpio_func.groups[i] = i;
 360 +
 361 +       f[c] = &gpio_func;
 362 +       c++;
 363 +
 364 +       /* add remaining functions */
 365 +       for (i = 0; i < p->group_count; i++) {
 366 +               for (j = 0; j < p->groups[i].func_count; j++) {
 367 +                       f[c] = &p->groups[i].func[j];
 368 +                       f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
 369 +                       f[c]->groups[0] = i;
 370 +                       f[c]->group_count = 1;
 371 +                       c++;
 372 +               }
 373 +       }
 374 +       return 0;
 375 +}
 376 +
 377 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
 378 +{
 379 +       int i, j;
 380 +
 381 +       /* loop over the functions and initialize the pins array. also work out the highest pin used */
 382 +       for (i = 0; i < p->func_count; i++) {
 383 +               int pin;
 384 +
 385 +               if (!p->func[i]->pin_count)
 386 +                       continue;
 387 +
 388 +               p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
 389 +               for (j = 0; j < p->func[i]->pin_count; j++)
 390 +                       p->func[i]->pins[j] = p->func[i]->pin_first + j;
 391 +
 392 +               pin = p->func[i]->pin_first + p->func[i]->pin_count;
 393 +               if (pin > p->max_pins)
 394 +                       p->max_pins = pin;
 395 +       }
 396 +
 397 +       /* the buffer that tells us which pins are gpio */
 398 +       p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
 399 +               GFP_KERNEL);
 400 +       /* the pads needed to tell pinctrl about our pins */
 401 +       p->pads = devm_kzalloc(p->dev,
 402 +               sizeof(struct pinctrl_pin_desc) * p->max_pins,
 403 +               GFP_KERNEL);
 404 +       if (!p->pads || !p->gpio ) {
 405 +               dev_err(p->dev, "Failed to allocate gpio data\n");
 406 +               return -ENOMEM;
 407 +       }
 408 +
 409 +       memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
 410 +       for (i = 0; i < p->func_count; i++) {
 411 +               if (!p->func[i]->pin_count)
 412 +                       continue;
 413 +
 414 +               for (j = 0; j < p->func[i]->pin_count; j++)
 415 +                       p->gpio[p->func[i]->pins[j]] = 0;
 416 +       }
 417 +
 418 +       /* pin 0 is always a gpio */
 419 +       p->gpio[0] = 1;
 420 +
 421 +       /* set the pads */
 422 +       for (i = 0; i < p->max_pins; i++) {
 423 +               /* strlen("ioXY") + 1 = 5 */
 424 +               char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
 425 +
 426 +               if (!name) {
 427 +                       dev_err(p->dev, "Failed to allocate pad name\n");
 428 +                       return -ENOMEM;
 429 +               }
 430 +               snprintf(name, 5, "io%d", i);
 431 +               p->pads[i].number = i;
 432 +               p->pads[i].name = name;
 433 +       }
 434 +       p->desc->pins = p->pads;
 435 +       p->desc->npins = p->max_pins;
 436 +
 437 +       return 0;
 438 +}
 439 +
 440 +static int rt2880_pinmux_probe(struct platform_device *pdev)
 441 +{
 442 +       struct rt2880_priv *p;
 443 +       struct pinctrl_dev *dev;
 444 +       struct device_node *np;
 445 +
 446 +       if (!rt2880_pinmux_data)
 447 +               return -ENOSYS;
 448 +
 449 +       /* setup the private data */
 450 +       p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
 451 +       if (!p)
 452 +               return -ENOMEM;
 453 +
 454 +       p->dev = &pdev->dev;
 455 +       p->desc = &rt2880_pctrl_desc;
 456 +       p->groups = rt2880_pinmux_data;
 457 +       platform_set_drvdata(pdev, p);
 458 +
 459 +       /* init the device */
 460 +       if (rt2880_pinmux_index(p)) {
 461 +               dev_err(&pdev->dev, "failed to load index\n");
 462 +               return -EINVAL;
 463 +       }
 464 +       if (rt2880_pinmux_pins(p)) {
 465 +               dev_err(&pdev->dev, "failed to load pins\n");
 466 +               return -EINVAL;
 467 +       }
 468 +       dev = pinctrl_register(p->desc, &pdev->dev, p);
 469 +       if (IS_ERR(dev))
 470 +               return PTR_ERR(dev);
 471 +
 472 +       /* finalize by adding gpio ranges for enables gpio controllers */
 473 +       for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
 474 +               const __be32 *ngpio, *gpiobase;
 475 +               struct pinctrl_gpio_range *range;
 476 +               char *name;
 477 +
 478 +               if (!of_device_is_available(np))
 479 +                       continue;
 480 +
 481 +               ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 482 +               gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 483 +               if (!ngpio || !gpiobase) {
 484 +                       dev_err(&pdev->dev, "failed to load chip info\n");
 485 +                       return -EINVAL;
 486 +               }
 487 +
 488 +               range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
 489 +               range->name = name = (char *) &range[1];
 490 +               sprintf(name, "pio");
 491 +               range->npins = __be32_to_cpu(*ngpio);
 492 +               range->base = __be32_to_cpu(*gpiobase);
 493 +               range->pin_base = range->base;
 494 +               pinctrl_add_gpio_range(dev, range);
 495 +       }
 496 +
 497 +       return 0;
 498 +}
 499 +
 500 +static const struct of_device_id rt2880_pinmux_match[] = {
 501 +       { .compatible = "ralink,rt2880-pinmux" },
 502 +       {},
 503 +};
 504 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
 505 +
 506 +static struct platform_driver rt2880_pinmux_driver = {
 507 +       .probe = rt2880_pinmux_probe,
 508 +       .driver = {
 509 +               .name = "rt2880-pinmux",
 510 +               .owner = THIS_MODULE,
 511 +               .of_match_table = rt2880_pinmux_match,
 512 +       },
 513 +};
 514 +
 515 +int __init rt2880_pinmux_init(void)
 516 +{
 517 +       return platform_driver_register(&rt2880_pinmux_driver);
 518 +}
 519 +
 520 +core_initcall_sync(rt2880_pinmux_init);
 521 --- /dev/null
 522 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
 523 @@ -0,0 +1,53 @@
 524 +/*
 525 + *  This program is free software; you can redistribute it and/or modify
 526 + *  it under the terms of the GNU General Public License version 2 as
 527 + *  publishhed by the Free Software Foundation.
 528 + *
 529 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
 530 + */
 531 +
 532 +#ifndef _RT288X_PINMUX_H__
 533 +#define _RT288X_PINMUX_H__
 534 +
 535 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
 536 +#define GRP(_name, _func, _mask, _shift) \
 537 +       { .name = _name, .mask = _mask, .shift = _shift, \
 538 +         .func = _func, .gpio = _mask, \
 539 +         .func_count = ARRAY_SIZE(_func) }
 540 +
 541 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
 542 +       { .name = _name, .mask = _mask, .shift = _shift, \
 543 +         .func = _func, .gpio = _gpio, \
 544 +         .func_count = ARRAY_SIZE(_func) }
 545 +
 546 +struct rt2880_pmx_group;
 547 +
 548 +struct rt2880_pmx_func {
 549 +       const char *name;
 550 +       const char value;
 551 +
 552 +       int pin_first;
 553 +       int pin_count;
 554 +       int *pins;
 555 +
 556 +       int *groups;
 557 +       int group_count;
 558 +
 559 +       int enabled;
 560 +};
 561 +
 562 +struct rt2880_pmx_group {
 563 +       const char *name;
 564 +       int enabled;
 565 +
 566 +       const u32 shift;
 567 +       const char mask;
 568 +       const char gpio;
 569 +
 570 +       struct rt2880_pmx_func *func;
 571 +       int func_count;
 572 +};
 573 +
 574 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
 575 +
 576 +#endif
 577 --- a/arch/mips/ralink/mt7620.c
 578 +++ b/arch/mips/ralink/mt7620.c
 579 @@ -17,6 +17,7 @@
 580  #include <asm/mipsregs.h>
 581  #include <asm/mach-ralink/ralink_regs.h>
 582  #include <asm/mach-ralink/mt7620.h>
 583 +#include <asm/mach-ralink/pinmux.h>
 584
 585  #include "common.h"
 586
 587 @@ -48,118 +49,58 @@ static int dram_type;
 588  /* the pll dividers */
 589  static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
 590
 591 -static struct ralink_pinmux_grp mode_mux[] = {
 592 -       {
 593 -               .name = "i2c",
 594 -               .mask = MT7620_GPIO_MODE_I2C,
 595 -               .gpio_first = 1,
 596 -               .gpio_last = 2,
 597 -       }, {
 598 -               .name = "spi",
 599 -               .mask = MT7620_GPIO_MODE_SPI,
 600 -               .gpio_first = 3,
 601 -               .gpio_last = 6,
 602 -       }, {
 603 -               .name = "uartlite",
 604 -               .mask = MT7620_GPIO_MODE_UART1,
 605 -               .gpio_first = 15,
 606 -               .gpio_last = 16,
 607 -       }, {
 608 -               .name = "wdt",
 609 -               .mask = MT7620_GPIO_MODE_WDT,
 610 -               .gpio_first = 17,
 611 -               .gpio_last = 17,
 612 -       }, {
 613 -               .name = "mdio",
 614 -               .mask = MT7620_GPIO_MODE_MDIO,
 615 -               .gpio_first = 22,
 616 -               .gpio_last = 23,
 617 -       }, {
 618 -               .name = "rgmii1",
 619 -               .mask = MT7620_GPIO_MODE_RGMII1,
 620 -               .gpio_first = 24,
 621 -               .gpio_last = 35,
 622 -       }, {
 623 -               .name = "spi refclk",
 624 -               .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
 625 -               .gpio_first = 37,
 626 -               .gpio_last = 39,
 627 -       }, {
 628 -               .name = "jtag",
 629 -               .mask = MT7620_GPIO_MODE_JTAG,
 630 -               .gpio_first = 40,
 631 -               .gpio_last = 44,
 632 -       }, {
 633 -               /* shared lines with jtag */
 634 -               .name = "ephy",
 635 -               .mask = MT7620_GPIO_MODE_EPHY,
 636 -               .gpio_first = 40,
 637 -               .gpio_last = 44,
 638 -       }, {
 639 -               .name = "nand",
 640 -               .mask = MT7620_GPIO_MODE_JTAG,
 641 -               .gpio_first = 45,
 642 -               .gpio_last = 59,
 643 -       }, {
 644 -               .name = "rgmii2",
 645 -               .mask = MT7620_GPIO_MODE_RGMII2,
 646 -               .gpio_first = 60,
 647 -               .gpio_last = 71,
 648 -       }, {
 649 -               .name = "wled",
 650 -               .mask = MT7620_GPIO_MODE_WLED,
 651 -               .gpio_first = 72,
 652 -               .gpio_last = 72,
 653 -       }, {0}
 654 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
 655 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
 656 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
 657 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
 658 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
 659 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
 660 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
 661 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
 662 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
 663 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
 664 +static struct rt2880_pmx_func uartf_grp[] = {
 665 +       FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
 666 +       FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
 667 +       FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
 668 +       FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
 669 +       FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
 670 +       FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
 671 +       FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
 672  };
 673 -
 674 -static struct ralink_pinmux_grp uart_mux[] = {
 675 -       {
 676 -               .name = "uartf",
 677 -               .mask = MT7620_GPIO_MODE_UARTF,
 678 -               .gpio_first = 7,
 679 -               .gpio_last = 14,
 680 -       }, {
 681 -               .name = "pcm uartf",
 682 -               .mask = MT7620_GPIO_MODE_PCM_UARTF,
 683 -               .gpio_first = 7,
 684 -               .gpio_last = 14,
 685 -       }, {
 686 -               .name = "pcm i2s",
 687 -               .mask = MT7620_GPIO_MODE_PCM_I2S,
 688 -               .gpio_first = 7,
 689 -               .gpio_last = 14,
 690 -       }, {
 691 -               .name = "i2s uartf",
 692 -               .mask = MT7620_GPIO_MODE_I2S_UARTF,
 693 -               .gpio_first = 7,
 694 -               .gpio_last = 14,
 695 -       }, {
 696 -               .name = "pcm gpio",
 697 -               .mask = MT7620_GPIO_MODE_PCM_GPIO,
 698 -               .gpio_first = 11,
 699 -               .gpio_last = 14,
 700 -       }, {
 701 -               .name = "gpio uartf",
 702 -               .mask = MT7620_GPIO_MODE_GPIO_UARTF,
 703 -               .gpio_first = 7,
 704 -               .gpio_last = 10,
 705 -       }, {
 706 -               .name = "gpio i2s",
 707 -               .mask = MT7620_GPIO_MODE_GPIO_I2S,
 708 -               .gpio_first = 7,
 709 -               .gpio_last = 10,
 710 -       }, {
 711 -               .name = "gpio",
 712 -               .mask = MT7620_GPIO_MODE_GPIO,
 713 -       }, {0}
 714 +static struct rt2880_pmx_func wdt_grp[] = {
 715 +       FUNC("wdt rst", 0, 17, 1),
 716 +       FUNC("wdt refclk", 0, 17, 1),
 717 +       };
 718 +static struct rt2880_pmx_func pcie_rst_grp[] = {
 719 +       FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
 720 +       FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
 721 +};
 722 +static struct rt2880_pmx_func nd_sd_grp[] = {
 723 +       FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
 724 +       FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
 725  };
 726
 727 -struct ralink_pinmux rt_gpio_pinmux = {
 728 -       .mode = mode_mux,
 729 -       .uart = uart_mux,
 730 -       .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
 731 -       .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
 732 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
 733 +       GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
 734 +       GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
 735 +               MT7620_GPIO_MODE_UART0_SHIFT),
 736 +       GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
 737 +       GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
 738 +       GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
 739 +               MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
 740 +       GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
 741 +       GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
 742 +       GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
 743 +       GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
 744 +               MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
 745 +       GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
 746 +               MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
 747 +       GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
 748 +       GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
 749 +       GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
 750 +       GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
 751 +       { 0 }
 752  };
 753
 754  void __init ralink_clk_init(void)
 755 @@ -281,4 +222,6 @@ void prom_soc_init(struct ralink_soc_inf
 756                 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
 757         pr_info("Digital PMU set to %s control\n",
 758                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 759 +
 760 +       rt2880_pinmux_data = mt7620a_pinmux_data;
 761  }
 762 --- a/arch/mips/ralink/rt305x.c
 763 +++ b/arch/mips/ralink/rt305x.c
 764 @@ -17,90 +17,71 @@
 765  #include <asm/mipsregs.h>
 766  #include <asm/mach-ralink/ralink_regs.h>
 767  #include <asm/mach-ralink/rt305x.h>
 768 +#include <asm/mach-ralink/pinmux.h>
 769
 770  #include "common.h"
 771
 772  enum rt305x_soc_type rt305x_soc;
 773
 774 -static struct ralink_pinmux_grp mode_mux[] = {
 775 -       {
 776 -               .name = "i2c",
 777 -               .mask = RT305X_GPIO_MODE_I2C,
 778 -               .gpio_first = RT305X_GPIO_I2C_SD,
 779 -               .gpio_last = RT305X_GPIO_I2C_SCLK,
 780 -       }, {
 781 -               .name = "spi",
 782 -               .mask = RT305X_GPIO_MODE_SPI,
 783 -               .gpio_first = RT305X_GPIO_SPI_EN,
 784 -               .gpio_last = RT305X_GPIO_SPI_CLK,
 785 -       }, {
 786 -               .name = "uartlite",
 787 -               .mask = RT305X_GPIO_MODE_UART1,
 788 -               .gpio_first = RT305X_GPIO_UART1_TXD,
 789 -               .gpio_last = RT305X_GPIO_UART1_RXD,
 790 -       }, {
 791 -               .name = "jtag",
 792 -               .mask = RT305X_GPIO_MODE_JTAG,
 793 -               .gpio_first = RT305X_GPIO_JTAG_TDO,
 794 -               .gpio_last = RT305X_GPIO_JTAG_TDI,
 795 -       }, {
 796 -               .name = "mdio",
 797 -               .mask = RT305X_GPIO_MODE_MDIO,
 798 -               .gpio_first = RT305X_GPIO_MDIO_MDC,
 799 -               .gpio_last = RT305X_GPIO_MDIO_MDIO,
 800 -       }, {
 801 -               .name = "sdram",
 802 -               .mask = RT305X_GPIO_MODE_SDRAM,
 803 -               .gpio_first = RT305X_GPIO_SDRAM_MD16,
 804 -               .gpio_last = RT305X_GPIO_SDRAM_MD31,
 805 -       }, {
 806 -               .name = "rgmii",
 807 -               .mask = RT305X_GPIO_MODE_RGMII,
 808 -               .gpio_first = RT305X_GPIO_GE0_TXD0,
 809 -               .gpio_last = RT305X_GPIO_GE0_RXCLK,
 810 -       }, {0}
 811 +static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
 812 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
 813 +static struct rt2880_pmx_func uartf_func[] = {
 814 +       FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
 815 +       FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
 816 +       FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
 817 +       FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
 818 +       FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
 819 +       FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
 820 +       FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
 821 +};
 822 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
 823 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
 824 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
 825 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
 826 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
 827 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
 828 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
 829 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
 830 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
 831 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
 832 +
 833 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
 834 +       GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
 835 +       GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
 836 +       GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
 837 +               RT305X_GPIO_MODE_UART0_SHIFT),
 838 +       GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
 839 +       GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
 840 +       GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
 841 +       GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
 842 +       GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
 843 +       { 0 }
 844 +};
 845 +
 846 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
 847 +       GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
 848 +       GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
 849 +       GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
 850 +               RT305X_GPIO_MODE_UART0_SHIFT),
 851 +       GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
 852 +       GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
 853 +       GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
 854 +       GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
 855 +       GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
 856 +       GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
 857 +       GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
 858 +       { 0 }
 859  };
 860
 861 -static struct ralink_pinmux_grp uart_mux[] = {
 862 -       {
 863 -               .name = "uartf",
 864 -               .mask = RT305X_GPIO_MODE_UARTF,
 865 -               .gpio_first = RT305X_GPIO_7,
 866 -               .gpio_last = RT305X_GPIO_14,
 867 -       }, {
 868 -               .name = "pcm uartf",
 869 -               .mask = RT305X_GPIO_MODE_PCM_UARTF,
 870 -               .gpio_first = RT305X_GPIO_7,
 871 -               .gpio_last = RT305X_GPIO_14,
 872 -       }, {
 873 -               .name = "pcm i2s",
 874 -               .mask = RT305X_GPIO_MODE_PCM_I2S,
 875 -               .gpio_first = RT305X_GPIO_7,
 876 -               .gpio_last = RT305X_GPIO_14,
 877 -       }, {
 878 -               .name = "i2s uartf",
 879 -               .mask = RT305X_GPIO_MODE_I2S_UARTF,
 880 -               .gpio_first = RT305X_GPIO_7,
 881 -               .gpio_last = RT305X_GPIO_14,
 882 -       }, {
 883 -               .name = "pcm gpio",
 884 -               .mask = RT305X_GPIO_MODE_PCM_GPIO,
 885 -               .gpio_first = RT305X_GPIO_10,
 886 -               .gpio_last = RT305X_GPIO_14,
 887 -       }, {
 888 -               .name = "gpio uartf",
 889 -               .mask = RT305X_GPIO_MODE_GPIO_UARTF,
 890 -               .gpio_first = RT305X_GPIO_7,
 891 -               .gpio_last = RT305X_GPIO_10,
 892 -       }, {
 893 -               .name = "gpio i2s",
 894 -               .mask = RT305X_GPIO_MODE_GPIO_I2S,
 895 -               .gpio_first = RT305X_GPIO_7,
 896 -               .gpio_last = RT305X_GPIO_10,
 897 -       }, {
 898 -               .name = "gpio",
 899 -               .mask = RT305X_GPIO_MODE_GPIO,
 900 -       }, {0}
 901 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
 902 +       GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
 903 +       GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
 904 +       GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
 905 +               RT305X_GPIO_MODE_UART0_SHIFT),
 906 +       GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
 907 +       GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
 908 +       GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
 909 +       { 0 }
 910  };
 911
 912  static void rt305x_wdt_reset(void)
 913 @@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
 914         rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
 915  }
 916
 917 -struct ralink_pinmux rt_gpio_pinmux = {
 918 -       .mode = mode_mux,
 919 -       .uart = uart_mux,
 920 -       .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
 921 -       .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
 922 -       .wdt_reset = rt305x_wdt_reset,
 923 -};
 924 -
 925  static unsigned long rt5350_get_mem_size(void)
 926  {
 927         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 928 @@ -291,11 +264,14 @@ void prom_soc_init(struct ralink_soc_inf
 929         soc_info->mem_base = RT305X_SDRAM_BASE;
 930         if (soc_is_rt5350()) {
 931                 soc_info->mem_size = rt5350_get_mem_size();
 932 +               rt2880_pinmux_data = rt5350_pinmux_data;
 933         } else if (soc_is_rt305x() || soc_is_rt3350()) {
 934                 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
 935                 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
 936 +               rt2880_pinmux_data = rt3050_pinmux_data;
 937         } else if (soc_is_rt3352()) {
 938                 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
 939                 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
 940 +               rt2880_pinmux_data = rt3352_pinmux_data;
 941         }
 942  }
 943 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
 944 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
 945 @@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
 946  #define RT305X_GPIO_GE0_TXD0           40
 947  #define RT305X_GPIO_GE0_RXCLK          51
 948
 949 -#define RT305X_GPIO_MODE_I2C           BIT(0)
 950 -#define RT305X_GPIO_MODE_SPI           BIT(1)
 951  #define RT305X_GPIO_MODE_UART0_SHIFT   2
 952  #define RT305X_GPIO_MODE_UART0_MASK    0x7
 953  #define RT305X_GPIO_MODE_UART0(x)      ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
 954 -#define RT305X_GPIO_MODE_UARTF         0x0
 955 -#define RT305X_GPIO_MODE_PCM_UARTF     0x1
 956 -#define RT305X_GPIO_MODE_PCM_I2S       0x2
 957 -#define RT305X_GPIO_MODE_I2S_UARTF     0x3
 958 -#define RT305X_GPIO_MODE_PCM_GPIO      0x4
 959 -#define RT305X_GPIO_MODE_GPIO_UARTF    0x5
 960 -#define RT305X_GPIO_MODE_GPIO_I2S      0x6
 961 -#define RT305X_GPIO_MODE_GPIO          0x7
 962 -#define RT305X_GPIO_MODE_UART1         BIT(5)
 963 -#define RT305X_GPIO_MODE_JTAG          BIT(6)
 964 -#define RT305X_GPIO_MODE_MDIO          BIT(7)
 965 -#define RT305X_GPIO_MODE_SDRAM         BIT(8)
 966 -#define RT305X_GPIO_MODE_RGMII         BIT(9)
 967 +#define RT305X_GPIO_MODE_UARTF         0
 968 +#define RT305X_GPIO_MODE_PCM_UARTF     1
 969 +#define RT305X_GPIO_MODE_PCM_I2S       2
 970 +#define RT305X_GPIO_MODE_I2S_UARTF     3
 971 +#define RT305X_GPIO_MODE_PCM_GPIO      4
 972 +#define RT305X_GPIO_MODE_GPIO_UARTF    5
 973 +#define RT305X_GPIO_MODE_GPIO_I2S      6
 974 +#define RT305X_GPIO_MODE_GPIO          7
 975 +
 976 +#define RT305X_GPIO_MODE_I2C           0
 977 +#define RT305X_GPIO_MODE_SPI           1
 978 +#define RT305X_GPIO_MODE_UART1         5
 979 +#define RT305X_GPIO_MODE_JTAG          6
 980 +#define RT305X_GPIO_MODE_MDIO          7
 981 +#define RT305X_GPIO_MODE_SDRAM         8
 982 +#define RT305X_GPIO_MODE_RGMII         9
 983 +#define RT5350_GPIO_MODE_PHY_LED       14
 984 +#define RT3352_GPIO_MODE_LNA           18
 985 +#define RT3352_GPIO_MODE_PA            20
 986
 987  #define RT3352_SYSC_REG_SYSCFG0                0x010
 988  #define RT3352_SYSC_REG_SYSCFG1         0x014
 989 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
 990 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
 991 @@ -59,7 +59,6 @@
 992  #define MT7620_DDR2_SIZE_MIN           32
 993  #define MT7620_DDR2_SIZE_MAX           256
 994
 995 -#define MT7620_GPIO_MODE_I2C           BIT(0)
 996  #define MT7620_GPIO_MODE_UART0_SHIFT   2
 997  #define MT7620_GPIO_MODE_UART0_MASK    0x7
 998  #define MT7620_GPIO_MODE_UART0(x)      ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
 999 @@ -71,15 +70,35 @@
1000  #define MT7620_GPIO_MODE_GPIO_UARTF    0x5
1001  #define MT7620_GPIO_MODE_GPIO_I2S      0x6
1002  #define MT7620_GPIO_MODE_GPIO          0x7
1003 -#define MT7620_GPIO_MODE_UART1         BIT(5)
1004 -#define MT7620_GPIO_MODE_MDIO          BIT(8)
1005 -#define MT7620_GPIO_MODE_RGMII1                BIT(9)
1006 -#define MT7620_GPIO_MODE_RGMII2                BIT(10)
1007 -#define MT7620_GPIO_MODE_SPI           BIT(11)
1008 -#define MT7620_GPIO_MODE_SPI_REF_CLK   BIT(12)
1009 -#define MT7620_GPIO_MODE_WLED          BIT(13)
1010 -#define MT7620_GPIO_MODE_JTAG          BIT(15)
1011 -#define MT7620_GPIO_MODE_EPHY          BIT(15)
1012 -#define MT7620_GPIO_MODE_WDT           BIT(22)
1013 +
1014 +#define MT7620_GPIO_MODE_NAND          0
1015 +#define MT7620_GPIO_MODE_SD            1
1016 +#define MT7620_GPIO_MODE_ND_SD_GPIO    2
1017 +#define MT7620_GPIO_MODE_ND_SD_MASK    0x3
1018 +#define MT7620_GPIO_MODE_ND_SD_SHIFT   18
1019 +
1020 +#define MT7620_GPIO_MODE_PCIE_RST      0
1021 +#define MT7620_GPIO_MODE_PCIE_REF      1
1022 +#define MT7620_GPIO_MODE_PCIE_GPIO     2
1023 +#define MT7620_GPIO_MODE_PCIE_MASK     0x3
1024 +#define MT7620_GPIO_MODE_PCIE_SHIFT    16
1025 +
1026 +#define MT7620_GPIO_MODE_WDT_RST       0
1027 +#define MT7620_GPIO_MODE_WDT_REF       1
1028 +#define MT7620_GPIO_MODE_WDT_GPIO      2
1029 +#define MT7620_GPIO_MODE_WDT_MASK      0x3
1030 +#define MT7620_GPIO_MODE_WDT_SHIFT     21
1031 +
1032 +#define MT7620_GPIO_MODE_I2C           0
1033 +#define MT7620_GPIO_MODE_UART1         5
1034 +#define MT7620_GPIO_MODE_MDIO          8
1035 +#define MT7620_GPIO_MODE_RGMII1                9
1036 +#define MT7620_GPIO_MODE_RGMII2                10
1037 +#define MT7620_GPIO_MODE_SPI           11
1038 +#define MT7620_GPIO_MODE_SPI_REF_CLK   12
1039 +#define MT7620_GPIO_MODE_WLED          13
1040 +#define MT7620_GPIO_MODE_JTAG          15
1041 +#define MT7620_GPIO_MODE_EPHY          15
1042 +#define MT7620_GPIO_MODE_PA            20
1043
1044  #endif
1045 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
1046 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
1047 @@ -112,8 +112,6 @@
1048  #define RT3883_CLKCFG1_PCI_CLK_EN      BIT(19)
1049  #define RT3883_CLKCFG1_UPHY0_CLK_EN    BIT(18)
1050
1051 -#define RT3883_GPIO_MODE_I2C           BIT(0)
1052 -#define RT3883_GPIO_MODE_SPI           BIT(1)
1053  #define RT3883_GPIO_MODE_UART0_SHIFT   2
1054  #define RT3883_GPIO_MODE_UART0_MASK    0x7
1055  #define RT3883_GPIO_MODE_UART0(x)      ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
1056 @@ -125,11 +123,15 @@
1057  #define RT3883_GPIO_MODE_GPIO_UARTF    0x5
1058  #define RT3883_GPIO_MODE_GPIO_I2S      0x6
1059  #define RT3883_GPIO_MODE_GPIO          0x7
1060 -#define RT3883_GPIO_MODE_UART1         BIT(5)
1061 -#define RT3883_GPIO_MODE_JTAG          BIT(6)
1062 -#define RT3883_GPIO_MODE_MDIO          BIT(7)
1063 -#define RT3883_GPIO_MODE_GE1           BIT(9)
1064 -#define RT3883_GPIO_MODE_GE2           BIT(10)
1065 +
1066 +#define RT3883_GPIO_MODE_I2C           0
1067 +#define RT3883_GPIO_MODE_SPI           1
1068 +#define RT3883_GPIO_MODE_UART1         5
1069 +#define RT3883_GPIO_MODE_JTAG          6
1070 +#define RT3883_GPIO_MODE_MDIO          7
1071 +#define RT3883_GPIO_MODE_GE1           9
1072 +#define RT3883_GPIO_MODE_GE2           10
1073 +
1074  #define RT3883_GPIO_MODE_PCI_SHIFT     11
1075  #define RT3883_GPIO_MODE_PCI_MASK      0x7
1076  #define RT3883_GPIO_MODE_PCI           (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
1077 --- a/arch/mips/ralink/common.h
1078 +++ b/arch/mips/ralink/common.h
1079 @@ -11,25 +11,6 @@
1080
1081  #define RAMIPS_SYS_TYPE_LEN    32
1082
1083 -struct ralink_pinmux_grp {
1084 -       const char *name;
1085 -       u32 mask;
1086 -       int gpio_first;
1087 -       int gpio_last;
1088 -};
1089 -
1090 -struct ralink_pinmux {
1091 -       struct ralink_pinmux_grp *mode;
1092 -       struct ralink_pinmux_grp *uart;
1093 -       int uart_shift;
1094 -       u32 uart_mask;
1095 -       void (*wdt_reset)(void);
1096 -       struct ralink_pinmux_grp *pci;
1097 -       int pci_shift;
1098 -       u32 pci_mask;
1099 -};
1100 -extern struct ralink_pinmux rt_gpio_pinmux;
1101 -
1102  struct ralink_soc_info {
1103         unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
1104         unsigned char *compatible;
1105 --- a/arch/mips/ralink/rt3883.c
1106 +++ b/arch/mips/ralink/rt3883.c
1107 @@ -17,132 +17,50 @@
1108  #include <asm/mipsregs.h>
1109  #include <asm/mach-ralink/ralink_regs.h>
1110  #include <asm/mach-ralink/rt3883.h>
1111 +#include <asm/mach-ralink/pinmux.h>
1112
1113  #include "common.h"
1114
1115 -static struct ralink_pinmux_grp mode_mux[] = {
1116 -       {
1117 -               .name = "i2c",
1118 -               .mask = RT3883_GPIO_MODE_I2C,
1119 -               .gpio_first = RT3883_GPIO_I2C_SD,
1120 -               .gpio_last = RT3883_GPIO_I2C_SCLK,
1121 -       }, {
1122 -               .name = "spi",
1123 -               .mask = RT3883_GPIO_MODE_SPI,
1124 -               .gpio_first = RT3883_GPIO_SPI_CS0,
1125 -               .gpio_last = RT3883_GPIO_SPI_MISO,
1126 -       }, {
1127 -               .name = "uartlite",
1128 -               .mask = RT3883_GPIO_MODE_UART1,
1129 -               .gpio_first = RT3883_GPIO_UART1_TXD,
1130 -               .gpio_last = RT3883_GPIO_UART1_RXD,
1131 -       }, {
1132 -               .name = "jtag",
1133 -               .mask = RT3883_GPIO_MODE_JTAG,
1134 -               .gpio_first = RT3883_GPIO_JTAG_TDO,
1135 -               .gpio_last = RT3883_GPIO_JTAG_TCLK,
1136 -       }, {
1137 -               .name = "mdio",
1138 -               .mask = RT3883_GPIO_MODE_MDIO,
1139 -               .gpio_first = RT3883_GPIO_MDIO_MDC,
1140 -               .gpio_last = RT3883_GPIO_MDIO_MDIO,
1141 -       }, {
1142 -               .name = "ge1",
1143 -               .mask = RT3883_GPIO_MODE_GE1,
1144 -               .gpio_first = RT3883_GPIO_GE1_TXD0,
1145 -               .gpio_last = RT3883_GPIO_GE1_RXCLK,
1146 -       }, {
1147 -               .name = "ge2",
1148 -               .mask = RT3883_GPIO_MODE_GE2,
1149 -               .gpio_first = RT3883_GPIO_GE2_TXD0,
1150 -               .gpio_last = RT3883_GPIO_GE2_RXCLK,
1151 -       }, {
1152 -               .name = "pci",
1153 -               .mask = RT3883_GPIO_MODE_PCI,
1154 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1155 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1156 -       }, {
1157 -               .name = "lna a",
1158 -               .mask = RT3883_GPIO_MODE_LNA_A,
1159 -               .gpio_first = RT3883_GPIO_LNA_PE_A0,
1160 -               .gpio_last = RT3883_GPIO_LNA_PE_A2,
1161 -       }, {
1162 -               .name = "lna g",
1163 -               .mask = RT3883_GPIO_MODE_LNA_G,
1164 -               .gpio_first = RT3883_GPIO_LNA_PE_G0,
1165 -               .gpio_last = RT3883_GPIO_LNA_PE_G2,
1166 -       }, {0}
1167 +static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
1168 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
1169 +static struct rt2880_pmx_func uartf_func[] = {
1170 +       FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
1171 +       FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
1172 +       FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
1173 +       FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
1174 +       FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
1175 +       FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
1176 +       FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
1177  };
1178 -
1179 -static struct ralink_pinmux_grp uart_mux[] = {
1180 -       {
1181 -               .name = "uartf",
1182 -               .mask = RT3883_GPIO_MODE_UARTF,
1183 -               .gpio_first = RT3883_GPIO_7,
1184 -               .gpio_last = RT3883_GPIO_14,
1185 -       }, {
1186 -               .name = "pcm uartf",
1187 -               .mask = RT3883_GPIO_MODE_PCM_UARTF,
1188 -               .gpio_first = RT3883_GPIO_7,
1189 -               .gpio_last = RT3883_GPIO_14,
1190 -       }, {
1191 -               .name = "pcm i2s",
1192 -               .mask = RT3883_GPIO_MODE_PCM_I2S,
1193 -               .gpio_first = RT3883_GPIO_7,
1194 -               .gpio_last = RT3883_GPIO_14,
1195 -       }, {
1196 -               .name = "i2s uartf",
1197 -               .mask = RT3883_GPIO_MODE_I2S_UARTF,
1198 -               .gpio_first = RT3883_GPIO_7,
1199 -               .gpio_last = RT3883_GPIO_14,
1200 -       }, {
1201 -               .name = "pcm gpio",
1202 -               .mask = RT3883_GPIO_MODE_PCM_GPIO,
1203 -               .gpio_first = RT3883_GPIO_11,
1204 -               .gpio_last = RT3883_GPIO_14,
1205 -       }, {
1206 -               .name = "gpio uartf",
1207 -               .mask = RT3883_GPIO_MODE_GPIO_UARTF,
1208 -               .gpio_first = RT3883_GPIO_7,
1209 -               .gpio_last = RT3883_GPIO_10,
1210 -       }, {
1211 -               .name = "gpio i2s",
1212 -               .mask = RT3883_GPIO_MODE_GPIO_I2S,
1213 -               .gpio_first = RT3883_GPIO_7,
1214 -               .gpio_last = RT3883_GPIO_10,
1215 -       }, {
1216 -               .name = "gpio",
1217 -               .mask = RT3883_GPIO_MODE_GPIO,
1218 -       }, {0}
1219 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
1220 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
1221 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
1222 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
1223 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
1224 +static struct rt2880_pmx_func pci_func[] = {
1225 +       FUNC("pci-dev", 0, 40, 32),
1226 +       FUNC("pci-host2", 1, 40, 32),
1227 +       FUNC("pci-host1", 2, 40, 32),
1228 +       FUNC("pci-fnc", 3, 40, 32)
1229  };
1230 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
1231 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
1232
1233 -static struct ralink_pinmux_grp pci_mux[] = {
1234 -       {
1235 -               .name = "pci-dev",
1236 -               .mask = 0,
1237 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1238 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1239 -       }, {
1240 -               .name = "pci-host2",
1241 -               .mask = 1,
1242 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1243 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1244 -       }, {
1245 -               .name = "pci-host1",
1246 -               .mask = 2,
1247 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1248 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1249 -       }, {
1250 -               .name = "pci-fnc",
1251 -               .mask = 3,
1252 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1253 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1254 -       }, {
1255 -               .name = "pci-gpio",
1256 -               .mask = 7,
1257 -               .gpio_first = RT3883_GPIO_PCI_AD0,
1258 -               .gpio_last = RT3883_GPIO_PCI_AD31,
1259 -       }, {0}
1260 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
1261 +       GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
1262 +       GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
1263 +       GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
1264 +               RT3883_GPIO_MODE_UART0_SHIFT),
1265 +       GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
1266 +       GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
1267 +       GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
1268 +       GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
1269 +       GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
1270 +       GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
1271 +               RT3883_GPIO_MODE_PCI_SHIFT),
1272 +       GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
1273 +       GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
1274 +       { 0 }
1275  };
1276
1277  static void rt3883_wdt_reset(void)
1278 @@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
1279         rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
1280  }
1281
1282 -struct ralink_pinmux rt_gpio_pinmux = {
1283 -       .mode = mode_mux,
1284 -       .uart = uart_mux,
1285 -       .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
1286 -       .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
1287 -       .wdt_reset = rt3883_wdt_reset,
1288 -       .pci = pci_mux,
1289 -       .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
1290 -       .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
1291 -};
1292 -
1293  void __init ralink_clk_init(void)
1294  {
1295         unsigned long cpu_rate, sys_rate;
1296 @@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
1297         soc_info->mem_base = RT3883_SDRAM_BASE;
1298         soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
1299         soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
1300 +
1301 +       rt2880_pinmux_data = rt3883_pinmux_data;
1302  }