target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch

   1 From e19957560170d63c6a5f0b1d7ba63695e4d1f033 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 2 Dec 2013 16:14:28 +0100
   4 Subject: [PATCH 506/507] GPIO: ralink: add mt7621 gpio controller
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/Kconfig          |    1 +
   9  drivers/gpio/Kconfig       |    6 ++
  10  drivers/gpio/Makefile      |    1 +
  11  drivers/gpio/gpio-mt7621.c |  183 ++++++++++++++++++++++++++++++++++++++++++++
  12  4 files changed, 191 insertions(+)
  13  create mode 100644 drivers/gpio/gpio-mt7621.c
  14
  15 --- a/drivers/gpio/Kconfig
  16 +++ b/drivers/gpio/Kconfig
  17 @@ -710,6 +710,12 @@ config GPIO_MSIC
  18           Enable support for GPIO on intel MSIC controllers found in
  19           intel MID devices
  20
  21 +config GPIO_MT7621
  22 +       bool "Mediatek GPIO Support"
  23 +       depends on RALINK && SOC_MT7621
  24 +       help
  25 +         Say yes here to support the Mediatek SoC GPIO device
  26 +
  27  comment "USB GPIO expanders:"
  28
  29  config GPIO_VIPERBOARD
  30 --- a/drivers/gpio/Makefile
  31 +++ b/drivers/gpio/Makefile
  32 @@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X)     += gpio-wm831x
  33  obj-$(CONFIG_GPIO_WM8350)      += gpio-wm8350.o
  34  obj-$(CONFIG_GPIO_WM8994)      += gpio-wm8994.o
  35  obj-$(CONFIG_GPIO_XILINX)      += gpio-xilinx.o
  36 +obj-$(CONFIG_GPIO_MT7621)      += gpio-mt7621.o
  37 --- /dev/null
  38 +++ b/drivers/gpio/gpio-mt7621.c
  39 @@ -0,0 +1,183 @@
  40 +/*
  41 + * This program is free software; you can redistribute it and/or modify it
  42 + * under the terms of the GNU General Public License version 2 as published
  43 + * by the Free Software Foundation.
  44 + *
  45 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  46 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  47 + */
  48 +
  49 +#include <linux/io.h>
  50 +#include <linux/err.h>
  51 +#include <linux/gpio.h>
  52 +#include <linux/module.h>
  53 +#include <linux/of_irq.h>
  54 +#include <linux/spinlock.h>
  55 +#include <linux/irqdomain.h>
  56 +#include <linux/interrupt.h>
  57 +#include <linux/platform_device.h>
  58 +
  59 +#define MTK_BANK_WIDTH         32
  60 +
  61 +enum mediatek_gpio_reg {
  62 +       GPIO_REG_CTRL = 0,
  63 +       GPIO_REG_POL,
  64 +       GPIO_REG_DATA,
  65 +       GPIO_REG_DSET,
  66 +       GPIO_REG_DCLR,
  67 +};
  68 +
  69 +static void __iomem *mtk_gc_membase;
  70 +
  71 +struct mtk_gc {
  72 +       struct gpio_chip chip;
  73 +       spinlock_t lock;
  74 +       int bank;
  75 +};
  76 +
  77 +int
  78 +gpio_to_irq(unsigned gpio)
  79 +{
  80 +       return -1;
  81 +}
  82 +
  83 +static inline struct mtk_gc
  84 +*to_mediatek_gpio(struct gpio_chip *chip)
  85 +{
  86 +       struct mtk_gc *mgc;
  87 +
  88 +       mgc = container_of(chip, struct mtk_gc, chip);
  89 +
  90 +       return mgc;
  91 +}
  92 +
  93 +static inline void
  94 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
  95 +{
  96 +       iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
  97 +}
  98 +
  99 +static inline u32
 100 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
 101 +{
 102 +       return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
 103 +}
 104 +
 105 +static void
 106 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 107 +{
 108 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 109 +
 110 +       mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
 111 +}
 112 +
 113 +static int
 114 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
 115 +{
 116 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 117 +
 118 +       return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 119 +}
 120 +
 121 +static int
 122 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 123 +{
 124 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 125 +       unsigned long flags;
 126 +       u32 t;
 127 +
 128 +       spin_lock_irqsave(&rg->lock, flags);
 129 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 130 +       t &= ~BIT(offset);
 131 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 132 +       spin_unlock_irqrestore(&rg->lock, flags);
 133 +
 134 +       return 0;
 135 +}
 136 +
 137 +static int
 138 +mediatek_gpio_direction_output(struct gpio_chip *chip,
 139 +                                       unsigned offset, int value)
 140 +{
 141 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 142 +       unsigned long flags;
 143 +       u32 t;
 144 +
 145 +       spin_lock_irqsave(&rg->lock, flags);
 146 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 147 +       t |= BIT(offset);
 148 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 149 +       mediatek_gpio_set(chip, offset, value);
 150 +       spin_unlock_irqrestore(&rg->lock, flags);
 151 +
 152 +       return 0;
 153 +}
 154 +
 155 +static int
 156 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
 157 +{
 158 +       const __be32 *id = of_get_property(bank, "reg", NULL);
 159 +       struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
 160 +                               sizeof(struct mtk_gc), GFP_KERNEL);
 161 +       if (!rg || !id)
 162 +               return -ENOMEM;
 163 +
 164 +       spin_lock_init(&rg->lock);
 165 +
 166 +       rg->chip.dev = &pdev->dev;
 167 +       rg->chip.label = dev_name(&pdev->dev);
 168 +       rg->chip.of_node = bank;
 169 +       rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
 170 +       rg->chip.ngpio = MTK_BANK_WIDTH;
 171 +       rg->chip.direction_input = mediatek_gpio_direction_input;
 172 +       rg->chip.direction_output = mediatek_gpio_direction_output;
 173 +       rg->chip.get = mediatek_gpio_get;
 174 +       rg->chip.set = mediatek_gpio_set;
 175 +
 176 +       /* set polarity to low for all gpios */
 177 +       mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 178 +
 179 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 180 +
 181 +       return gpiochip_add(&rg->chip);
 182 +}
 183 +
 184 +static int
 185 +mediatek_gpio_probe(struct platform_device *pdev)
 186 +{
 187 +       struct device_node *bank, *np = pdev->dev.of_node;
 188 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 189 +
 190 +       mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
 191 +       if (IS_ERR(mtk_gc_membase))
 192 +               return PTR_ERR(mtk_gc_membase);
 193 +
 194 +       for_each_child_of_node(np, bank)
 195 +               if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
 196 +                       mediatek_gpio_bank_probe(pdev, bank);
 197 +
 198 +       return 0;
 199 +}
 200 +
 201 +static const struct of_device_id mediatek_gpio_match[] = {
 202 +       { .compatible = "mtk,mt7621-gpio" },
 203 +       {},
 204 +};
 205 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 206 +
 207 +static struct platform_driver mediatek_gpio_driver = {
 208 +       .probe = mediatek_gpio_probe,
 209 +       .driver = {
 210 +               .name = "mt7621_gpio",
 211 +               .owner = THIS_MODULE,
 212 +               .of_match_table = mediatek_gpio_match,
 213 +       },
 214 +};
 215 +
 216 +static int __init
 217 +mediatek_gpio_init(void)
 218 +{
 219 +       return platform_driver_register(&mediatek_gpio_driver);
 220 +}
 221 +
 222 +subsys_initcall(mediatek_gpio_init);