target/linux/ramips/patches-3.8/0110-MIPS-add-rt3883-dts-files.patch

   1 From 9d13fedc08f4e2cd9640983c2af8b9e9c64c094b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 18:37:00 +0100
   4 Subject: [PATCH 110/121] MIPS: add rt3883 dts files
   5
   6 Add a dtsi file for RT3883 SoC. This SoC is almost the same as RT3050 but has
   7 OHCI/EHCI in favour of the Synopsis DWC2 core. There is also a 3x3 802.11n
   8 wifi core.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 ---
  12  arch/mips/ralink/Kconfig             |    4 +
  13  arch/mips/ralink/dts/Makefile        |    1 +
  14  arch/mips/ralink/dts/rt3883.dtsi     |  186 ++++++++++++++++++++++++++++++++++
  15  arch/mips/ralink/dts/rt3883_eval.dts |   52 ++++++++++
  16  4 files changed, 243 insertions(+)
  17  create mode 100644 arch/mips/ralink/dts/rt3883.dtsi
  18  create mode 100644 arch/mips/ralink/dts/rt3883_eval.dts
  19
  20 --- a/arch/mips/ralink/Kconfig
  21 +++ b/arch/mips/ralink/Kconfig
  22 @@ -39,6 +39,10 @@ choice
  23                 bool "RT305x eval kit"
  24                 depends on SOC_RT305X
  25
  26 +       config DTB_RT3883_EVAL
  27 +               bool "RT3883 eval kit"
  28 +               depends on SOC_RT3883
  29 +
  30  endchoice
  31
  32  endif
  33 --- a/arch/mips/ralink/dts/Makefile
  34 +++ b/arch/mips/ralink/dts/Makefile
  35 @@ -1,2 +1,3 @@
  36  obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
  37  obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
  38 +obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
  39 --- /dev/null
  40 +++ b/arch/mips/ralink/dts/rt3883.dtsi
  41 @@ -0,0 +1,186 @@
  42 +/ {
  43 +       #address-cells = <1>;
  44 +       #size-cells = <1>;
  45 +       compatible = "ralink,rt3883-soc";
  46 +
  47 +       cpus {
  48 +               cpu@0 {
  49 +                       compatible = "mips,mips74Kc";
  50 +               };
  51 +       };
  52 +
  53 +       chosen {
  54 +               bootargs = "console=ttyS0,57600 init=/init";
  55 +       };
  56 +
  57 +       cpuintc: cpuintc@0 {
  58 +               #address-cells = <0>;
  59 +               #interrupt-cells = <1>;
  60 +               interrupt-controller;
  61 +               compatible = "mti,cpu-interrupt-controller";
  62 +       };
  63 +
  64 +       palmbus@10000000 {
  65 +               compatible = "palmbus";
  66 +               reg = <0x10000000 0x200000>;
  67 +               ranges = <0x0 0x10000000 0x1FFFFF>;
  68 +
  69 +               #address-cells = <1>;
  70 +               #size-cells = <1>;
  71 +
  72 +               sysc@0 {
  73 +                       compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
  74 +                       reg = <0x0 0x100>;
  75 +               };
  76 +
  77 +               timer@100 {
  78 +                       compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
  79 +                       reg = <0x100 0x20>;
  80 +
  81 +                       interrupt-parent = <&intc>;
  82 +                       interrupts = <1>;
  83 +
  84 +                       status = "disabled";
  85 +               };
  86 +
  87 +               watchdog@120 {
  88 +                       compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
  89 +                       reg = <0x120 0x10>;
  90 +               };
  91 +
  92 +               intc: intc@200 {
  93 +                       compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
  94 +                       reg = <0x200 0x100>;
  95 +
  96 +                       interrupt-controller;
  97 +                       #interrupt-cells = <1>;
  98 +
  99 +                       interrupt-parent = <&cpuintc>;
 100 +                       interrupts = <2>;
 101 +               };
 102 +
 103 +               memc@300 {
 104 +                       compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
 105 +                       reg = <0x300 0x100>;
 106 +               };
 107 +
 108 +               gpio0: gpio@600 {
 109 +                       compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
 110 +                       reg = <0x600 0x34>;
 111 +
 112 +                       gpio-controller;
 113 +                       #gpio-cells = <2>;
 114 +
 115 +                       ralink,num-gpios = <24>;
 116 +                       ralink,register-map = [ 00 04 08 0c
 117 +                                               20 24 28 2c
 118 +                                               30 34 ];
 119 +
 120 +                       status = "disabled";
 121 +               };
 122 +
 123 +               gpio1: gpio@638 {
 124 +                       compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
 125 +                       reg = <0x638 0x24>;
 126 +
 127 +                       gpio-controller;
 128 +                       #gpio-cells = <2>;
 129 +
 130 +                       ralink,num-gpios = <16>;
 131 +                       ralink,register-map = [ 00 04 08 0c
 132 +                                               10 14 18 1c
 133 +                                               20 24 ];
 134 +
 135 +                       status = "disabled";
 136 +               };
 137 +
 138 +               gpio2: gpio@660 {
 139 +                       compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
 140 +                       reg = <0x660 0x24>;
 141 +
 142 +                       gpio-controller;
 143 +                       #gpio-cells = <2>;
 144 +
 145 +                       ralink,num-gpios = <32>;
 146 +                       ralink,register-map = [ 00 04 08 0c
 147 +                                               10 14 18 1c
 148 +                                               20 24 ];
 149 +
 150 +                       status = "disabled";
 151 +               };
 152 +
 153 +               gpio3: gpio@688 {
 154 +                       compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
 155 +                       reg = <0x688 0x24>;
 156 +
 157 +                       gpio-controller;
 158 +                       #gpio-cells = <2>;
 159 +
 160 +                       ralink,num-gpios = <24>;
 161 +                       ralink,register-map = [ 00 04 08 0c
 162 +                                               10 14 18 1c
 163 +                                               20 24 ];
 164 +
 165 +                       status = "disabled";
 166 +               };
 167 +
 168 +               spi@b00 {
 169 +                       compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
 170 +                       reg = <0xb00 0x100>;
 171 +                       #address-cells = <1>;
 172 +                       #size-cells = <0>;
 173 +
 174 +                       status = "disabled";
 175 +               };
 176 +
 177 +               uartlite@c00 {
 178 +                       compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
 179 +                       reg = <0xc00 0x100>;
 180 +
 181 +                       interrupt-parent = <&intc>;
 182 +                       interrupts = <12>;
 183 +
 184 +                       reg-shift = <2>;
 185 +               };
 186 +       };
 187 +
 188 +       ethernet@10100000 {
 189 +               compatible = "ralink,rt3883-eth";
 190 +               reg = <0x10100000 10000>;
 191 +
 192 +               interrupt-parent = <&cpuintc>;
 193 +               interrupts = <5>;
 194 +
 195 +               status = "disabled";
 196 +       };
 197 +
 198 +       wmac@10180000 {
 199 +               compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
 200 +               reg = <0x10180000 40000>;
 201 +
 202 +               interrupt-parent = <&cpuintc>;
 203 +               interrupts = <6>;
 204 +
 205 +               status = "disabled";
 206 +       };
 207 +
 208 +       ehci@101c0000 {
 209 +               compatible = "ralink,rt3883-ehci", "ehci-platform";
 210 +               reg = <0x101c0000 0x1000>;
 211 +
 212 +               interrupt-parent = <&intc>;
 213 +               interrupts = <18>;
 214 +
 215 +               status = "disabled";
 216 +       };
 217 +
 218 +       ohci@101c1000 {
 219 +               compatible = "ralink,rt3883-ohci", "ohci-platform";
 220 +               reg = <0x101c1000 0x1000>;
 221 +
 222 +               interrupt-parent = <&intc>;
 223 +               interrupts = <18>;
 224 +
 225 +               status = "disabled";
 226 +       };
 227 +};
 228 --- /dev/null
 229 +++ b/arch/mips/ralink/dts/rt3883_eval.dts
 230 @@ -0,0 +1,52 @@
 231 +/dts-v1/;
 232 +
 233 +/include/ "rt3883.dtsi"
 234 +
 235 +/ {
 236 +       #address-cells = <1>;
 237 +       #size-cells = <1>;
 238 +       compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
 239 +       model = "Ralink RT3883 evaluation board";
 240 +
 241 +       memory@0 {
 242 +               reg = <0x0 0x4000000>;
 243 +       };
 244 +
 245 +       palmbus@10000000 {
 246 +               sysc@0 {
 247 +                       ralink,pinmmux = "uartlite", "spi";
 248 +                       ralink,uartmux = "gpio";
 249 +                       ralink,wdtmux = <0>;
 250 +               };
 251 +       };
 252 +
 253 +       cfi@1f000000 {
 254 +               compatible = "cfi-flash";
 255 +               reg = <0x1f000000 0x800000>;
 256 +
 257 +               bank-width = <2>;
 258 +               device-width = <2>;
 259 +               #address-cells = <1>;
 260 +               #size-cells = <1>;
 261 +
 262 +               partition@0 {
 263 +                       label = "uboot";
 264 +                       reg = <0x0 0x30000>;
 265 +                       read-only;
 266 +               };
 267 +               partition@30000 {
 268 +                       label = "uboot-env";
 269 +                       reg = <0x30000 0x10000>;
 270 +                       read-only;
 271 +               };
 272 +               partition@40000 {
 273 +                       label = "calibration";
 274 +                       reg = <0x40000 0x10000>;
 275 +                       read-only;
 276 +               };
 277 +               partition@50000 {
 278 +                       label = "linux";
 279 +                       reg = <0x50000 0x7b0000>;
 280 +               };
 281 +       };
 282 +};