target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch

   1 From 550fabd71d7fcdfe099bbf41e00e28719737161e Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Tue, 10 Mar 2020 12:34:59 +0100
   4 Subject: [PATCH] staging: mt7621-pci: enable clock bit for each port
   5
   6 The clock related code concerns me from the very beginning because
   7 there are some set ups got from legacy driver that are not documented
   8 anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1'
   9 register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed
  10 at all and the proper thing to do is just enable the clock bit for each
  11 pcie port. Hence remove useless code and do the right thing which is
  12 setting up the clock bit for each port enabled.
  13
  14 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  15 Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com
  16 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  17 ---
  18  drivers/staging/mt7621-pci/pci-mt7621.c | 17 ++++++-----------
  19  1 file changed, 6 insertions(+), 11 deletions(-)
  20
  21 --- a/drivers/staging/mt7621-pci/pci-mt7621.c
  22 +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
  23 @@ -45,8 +45,6 @@
  24
  25  /* rt_sysc_membase relative registers */
  26  #define RALINK_CLKCFG1                 0x30
  27 -#define RALINK_PCIE_CLK_GEN            0x7c
  28 -#define RALINK_PCIE_CLK_GEN1           0x80
  29
  30  /* Host-PCI bridge registers */
  31  #define RALINK_PCI_PCICFG_ADDR         0x0000
  32 @@ -85,10 +83,6 @@
  33  #define PCIE_PORT_CLK_EN(x)            BIT(24 + (x))
  34  #define PCIE_PORT_LINKUP               BIT(0)
  35
  36 -#define PCIE_CLK_GEN_EN                        BIT(31)
  37 -#define PCIE_CLK_GEN_DIS               0
  38 -#define PCIE_CLK_GEN1_DIS              GENMASK(30, 24)
  39 -#define PCIE_CLK_GEN1_EN               (BIT(27) | BIT(25))
  40  #define MEMORY_BASE                    0x0
  41  #define PERST_MODE_MASK                        GENMASK(11, 10)
  42  #define PERST_MODE_GPIO                        BIT(10)
  43 @@ -233,6 +227,11 @@ static inline bool mt7621_pcie_port_is_l
  44         return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
  45  }
  46
  47 +static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
  48 +{
  49 +       rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
  50 +}
  51 +
  52  static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
  53  {
  54         rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
  55 @@ -501,11 +500,6 @@ static void mt7621_pcie_init_ports(struc
  56                 }
  57         }
  58
  59 -       rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
  60 -       rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
  61 -       rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
  62 -       rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
  63 -       msleep(50);
  64         reset_control_deassert(pcie->rst);
  65  }
  66
  67 @@ -542,6 +536,7 @@ static void mt7621_pcie_enable_ports(str
  68
  69         list_for_each_entry(port, &pcie->ports, list) {
  70                 if (port->enabled) {
  71 +                       mt7621_pcie_port_clk_enable(port);
  72                         mt7621_pcie_enable_port(port);
  73                         dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
  74                         num_slots_enabled++;