target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <linux/debugfs.h>
   4 #include <linux/kernel.h>
   5
   6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
   7 #include "rtl83xx.h"
   8
   9 #define RTL838X_DRIVER_NAME "rtl838x"
  10
  11 #define RTL8380_LED_GLB_CTRL                    (0xA000)
  12 #define RTL8380_LED_MODE_SEL                    (0x1004)
  13 #define RTL8380_LED_MODE_CTRL                   (0xA004)
  14 #define RTL8380_LED_P_EN_CTRL                   (0xA008)
  15 #define RTL8380_LED_SW_CTRL                     (0xA00C)
  16 #define RTL8380_LED0_SW_P_EN_CTRL               (0xA010)
  17 #define RTL8380_LED1_SW_P_EN_CTRL               (0xA014)
  18 #define RTL8380_LED2_SW_P_EN_CTRL               (0xA018)
  19 #define RTL8380_LED_SW_P_CTRL(p)                (0xA01C + (((p) << 2)))
  20
  21 #define RTL8390_LED_GLB_CTRL                    (0x00E4)
  22 #define RTL8390_LED_SET_2_3_CTRL                (0x00E8)
  23 #define RTL8390_LED_SET_0_1_CTRL                (0x00EC)
  24 #define RTL8390_LED_COPR_SET_SEL_CTRL(p)        (0x00F0 + (((p >> 4) << 2)))
  25 #define RTL8390_LED_FIB_SET_SEL_CTRL(p)         (0x0100 + (((p >> 4) << 2)))
  26 #define RTL8390_LED_COPR_PMASK_CTRL(p)          (0x0110 + (((p >> 5) << 2)))
  27 #define RTL8390_LED_FIB_PMASK_CTRL(p)           (0x00118 + (((p >> 5) << 2)))
  28 #define RTL8390_LED_COMBO_CTRL(p)               (0x0120 + (((p >> 5) << 2)))
  29 #define RTL8390_LED_SW_CTRL                     (0x0128)
  30 #define RTL8390_LED_SW_P_EN_CTRL(p)             (0x012C + (((p / 10) << 2)))
  31 #define RTL8390_LED_SW_P_CTRL(p)                (0x0144 + (((p) << 2)))
  32
  33 #define RTL838X_MIR_QID_CTRL(grp)               (0xAD44 + (((grp) << 2)))
  34 #define RTL838X_MIR_RSPAN_VLAN_CTRL(grp)        (0xA340 + (((grp) << 2)))
  35 #define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp)    (0xAA70 + (((grp) << 2)))
  36 #define RTL838X_MIR_RSPAN_TX_CTRL               (0xA350)
  37 #define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL        (0xAA80)
  38 #define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL        (0xAA84)
  39 #define RTL839X_MIR_RSPAN_VLAN_CTRL(grp)        (0xA340 + (((grp) << 2)))
  40 #define RTL839X_MIR_RSPAN_TX_CTRL               (0x69b0)
  41 #define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL        (0x2550)
  42 #define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL        (0x2554)
  43 #define RTL839X_MIR_SAMPLE_RATE_CTRL            (0x2558)
  44
  45 #define RTL838X_STAT_PRVTE_DROP_COUNTERS        (0x6A00)
  46 #define RTL839X_STAT_PRVTE_DROP_COUNTERS        (0x3E00)
  47 #define RTL930X_STAT_PRVTE_DROP_COUNTERS        (0xB5B8)
  48 #define RTL931X_STAT_PRVTE_DROP_COUNTERS        (0xd800)
  49
  50 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
  51 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
  52 void rtl83xx_fast_age(struct dsa_switch *ds, int port);
  53 u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
  54 u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
  55 int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
  56 int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
  57
  58
  59 const char *rtl838x_drop_cntr[] = {
  60     "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP",
  61     "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP",
  62     "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP",
  63     "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP",
  64     "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP",
  65     "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP",
  66     "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP",
  67     "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP",
  68     "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP",
  69     "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards"
  70 };
  71
  72 const char *rtl839x_drop_cntr[] = {
  73     "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
  74     "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
  75     "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
  76     "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
  77     "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
  78     "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING",
  79     "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP",
  80     "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE",
  81     "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL",
  82     "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR",
  83     "LINK_STATUS_BEFORE_MIRROR",
  84     "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR",
  85     "LINK_STATUS_AFTER_MIRROR",
  86     "WRED_AFTER_MIRROR"
  87 };
  88
  89 const char *rtl930x_drop_cntr[] = {
  90         "OAM_PARSER", "UC_RPF", "DEI_CFI", "MAC_IP_SUBNET_BASED_VLAN", "VLAN_IGR_FILTER",
  91         "L2_UC_MC", "IPV_IP6_MC_BRIDGE", "PTP", "USER_DEF_0_3", "RESERVED",
  92         "RESERVED1", "RESERVED2", "BPDU_RMA", "LACP", "LLDP",
  93         "EAPOL", "XX_RMA", "L3_IPUC_NON_IP", "IP4_IP6_HEADER_ERROR", "L3_BAD_IP",
  94         "L3_DIP_DMAC_MISMATCH", "IP4_IP_OPTION", "IP_UC_MC_ROUTING_LOOK_UP_MISS", "L3_DST_NULL_INTF",
  95         "L3_PBR_NULL_INTF",
  96         "HOST_NULL_INTF", "ROUTE_NULL_INTF", "BRIDGING_ACTION", "ROUTING_ACTION", "IPMC_RPF",
  97         "L2_NEXTHOP_AGE_OUT", "L3_UC_TTL_FAIL", "L3_MC_TTL_FAIL", "L3_UC_MTU_FAIL", "L3_MC_MTU_FAIL",
  98         "L3_UC_ICMP_REDIR", "IP6_MLD_OTHER_ACT", "ND", "IP_MC_RESERVED", "IP6_HBH",
  99         "INVALID_SA", "L2_HASH_FULL", "NEW_SA", "PORT_MOVE_FORBID", "STATIC_PORT_MOVING",
 100         "DYNMIC_PORT_MOVING", "L3_CRC", "MAC_LIMIT", "ATTACK_PREVENT", "ACL_FWD_ACTION",
 101         "OAMPDU", "OAM_MUX", "TRUNK_FILTER", "ACL_DROP", "IGR_BW",
 102         "ACL_METER", "VLAN_ACCEPT_FRAME_TYPE", "MSTP_SRC_DROP_DISABLED_BLOCKING", "SA_BLOCK", "DA_BLOCK",
 103         "STORM_CONTROL", "VLAN_EGR_FILTER", "MSTP_DESTINATION_DROP", "SRC_PORT_FILTER", "PORT_ISOLATION",
 104         "TX_MAX_FRAME_SIZE", "EGR_LINK_STATUS", "MAC_TX_DISABLE", "MAC_PAUSE_FRAME", "MAC_RX_DROP",
 105         "MIRROR_ISOLATE", "RX_FC", "EGR_QUEUE", "HSM_RUNOUT", "ROUTING_DISABLE", "INVALID_L2_NEXTHOP_ENTRY",
 106         "L3_MC_SRC_FLT", "CPUTAG_FLT", "FWD_PMSK_NULL", "IPUC_ROUTING_LOOKUP_MISS", "MY_DEV_DROP",
 107         "STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER"
 108 };
 109
 110 const char *rtl931x_drop_cntr[] = {
 111         "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS",
 112         "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10
 113         "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET",
 114         "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20
 115         "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK",
 116         "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30,
 117         "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN",
 118         "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40
 119         "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA",
 120         "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50
 121         "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH",
 122         "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60
 123         "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER",
 124         "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70
 125         "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM",
 126         "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80,
 127 };
 128
 129 static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
 130                                         loff_t *ppos, unsigned int value)
 131 {
 132         char *buf;
 133         ssize_t len;
 134
 135         if (*ppos != 0)
 136                 return 0;
 137
 138         buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
 139         if (!buf)
 140                 return -ENOMEM;
 141
 142         if (count < strlen(buf)) {
 143                 kfree(buf);
 144                 return -ENOSPC;
 145         }
 146
 147         len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
 148         kfree(buf);
 149
 150         return len;
 151 }
 152
 153 static ssize_t rtl838x_common_write(const char __user *buffer, size_t count,
 154                                  loff_t *ppos, unsigned int *value)
 155 {
 156         char b[32];
 157         ssize_t len;
 158         int ret;
 159
 160         if (*ppos != 0)
 161                 return -EINVAL;
 162
 163         if (count >= sizeof(b))
 164                 return -ENOSPC;
 165
 166         len = simple_write_to_buffer(b, sizeof(b) - 1, ppos,
 167                                      buffer, count);
 168         if (len < 0)
 169                 return len;
 170
 171         b[len] = '\0';
 172         ret = kstrtouint(b, 16, value);
 173         if (ret)
 174                 return -EIO;
 175
 176         return len;
 177 }
 178
 179 static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,
 180                              loff_t *ppos)
 181 {
 182         struct rtl838x_port *p = filp->private_data;
 183         struct dsa_switch *ds = p->dp->ds;
 184         int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index);
 185
 186         if (value < 0)
 187                 return -EINVAL;
 188
 189         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 190 }
 191
 192 static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
 193                                 size_t count, loff_t *ppos)
 194 {
 195         struct rtl838x_port *p = filp->private_data;
 196         u32 value;
 197         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 198         if (res < 0)
 199                 return res;
 200
 201         rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value);
 202
 203         return res;
 204 }
 205
 206 static const struct file_operations stp_state_fops = {
 207         .owner = THIS_MODULE,
 208         .open = simple_open,
 209         .read = stp_state_read,
 210         .write = stp_state_write,
 211 };
 212
 213 static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count,
 214                              loff_t *ppos)
 215 {
 216         struct rtl838x_switch_priv *priv = filp->private_data;
 217         int i;
 218         const char **d;
 219         u32 v;
 220         char *buf;
 221         int n = 0, len, offset;
 222         int num;
 223
 224         switch (priv->family_id) {
 225         case RTL8380_FAMILY_ID:
 226                 d = rtl838x_drop_cntr;
 227                 offset = RTL838X_STAT_PRVTE_DROP_COUNTERS;
 228                 num = 40;
 229                 break;
 230         case RTL8390_FAMILY_ID:
 231                 d = rtl839x_drop_cntr;
 232                 offset = RTL839X_STAT_PRVTE_DROP_COUNTERS;
 233                 num = 45;
 234                 break;
 235         case RTL9300_FAMILY_ID:
 236                 d = rtl930x_drop_cntr;
 237                 offset = RTL930X_STAT_PRVTE_DROP_COUNTERS;
 238                 num = 85;
 239                 break;
 240         case RTL9310_FAMILY_ID:
 241                 d = rtl931x_drop_cntr;
 242                 offset = RTL931X_STAT_PRVTE_DROP_COUNTERS;
 243                 num = 81;
 244                 break;
 245         }
 246
 247         buf = kmalloc(30 * num, GFP_KERNEL);
 248         if (!buf)
 249                 return -ENOMEM;
 250
 251         for (i = 0; i < num; i++) {
 252                 v = sw_r32(offset + (i << 2)) & 0xffff;
 253                 n += sprintf(buf + n, "%s: %d\n", d[i], v);
 254         }
 255
 256         if (count < strlen(buf)) {
 257                 kfree(buf);
 258                 return -ENOSPC;
 259         }
 260
 261         len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
 262         kfree(buf);
 263
 264         return len;
 265 }
 266
 267 static const struct file_operations drop_counter_fops = {
 268         .owner = THIS_MODULE,
 269         .open = simple_open,
 270         .read = drop_counter_read,
 271 };
 272
 273 static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv *priv,
 274                                  struct rtl838x_l2_entry *e)
 275 {
 276         u64 portmask;
 277         int i;
 278
 279         if (e->type == L2_UNICAST) {
 280                 seq_puts(m, "L2_UNICAST\n");
 281
 282                 seq_printf(m, "  mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
 283                         e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
 284                         e->vid, e->rvid);
 285
 286                 seq_printf(m, "  port %d age %d", e->port, e->age);
 287                 if (e->is_static)
 288                         seq_puts(m, " static");
 289                 if (e->block_da)
 290                         seq_puts(m, " block_da");
 291                 if (e->block_sa)
 292                         seq_puts(m, " block_sa");
 293                 if (e->suspended)
 294                         seq_puts(m, " suspended");
 295                 if (e->next_hop)
 296                         seq_printf(m, " next_hop route_id %u", e->nh_route_id);
 297                 seq_puts(m, "\n");
 298
 299         } else {
 300                 if (e->type == L2_MULTICAST) {
 301                         seq_puts(m, "L2_MULTICAST\n");
 302
 303                         seq_printf(m, "  mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
 304                                 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
 305                                 e->vid, e->rvid);
 306                 }
 307
 308                 if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) {
 309                         seq_puts(m, (e->type == IP4_MULTICAST) ?
 310                                     "IP4_MULTICAST\n" : "IP6_MULTICAST\n");
 311
 312                         seq_printf(m, "  gip %08x sip %08x vid %u rvid %u\n",
 313                                 e->mc_gip, e->mc_sip, e->vid, e->rvid);
 314                 }
 315
 316                 portmask = priv->r->read_mcast_pmask(e->mc_portmask_index);
 317                 seq_printf(m, "  index %u ports", e->mc_portmask_index);
 318                 for (i = 0; i < 64; i++) {
 319                         if (portmask & BIT_ULL(i))
 320                                 seq_printf(m, " %d", i);
 321                 }
 322                 seq_puts(m, "\n");
 323         }
 324
 325         seq_puts(m, "\n");
 326 }
 327
 328 static int l2_table_show(struct seq_file *m, void *v)
 329 {
 330         struct rtl838x_switch_priv *priv = m->private;
 331         struct rtl838x_l2_entry e;
 332         int i, bucket, index;
 333
 334         mutex_lock(&priv->reg_mutex);
 335
 336         for (i = 0; i < priv->fib_entries; i++) {
 337                 bucket = i >> 2;
 338                 index = i & 0x3;
 339                 priv->r->read_l2_entry_using_hash(bucket, index, &e);
 340
 341                 if (!e.valid)
 342                         continue;
 343
 344                 seq_printf(m, "Hash table bucket %d index %d ", bucket, index);
 345                 l2_table_print_entry(m, priv, &e);
 346
 347                 if (!((i + 1) % 64))
 348                         cond_resched();
 349         }
 350
 351         for (i = 0; i < 64; i++) {
 352                 priv->r->read_cam(i, &e);
 353
 354                 if (!e.valid)
 355                         continue;
 356
 357                 seq_printf(m, "CAM index %d ", i);
 358                 l2_table_print_entry(m, priv, &e);
 359         }
 360
 361         mutex_unlock(&priv->reg_mutex);
 362
 363         return 0;
 364 }
 365
 366 static int l2_table_open(struct inode *inode, struct file *filp)
 367 {
 368         return single_open(filp, l2_table_show, inode->i_private);
 369 }
 370
 371 static const struct file_operations l2_table_fops = {
 372         .owner = THIS_MODULE,
 373         .open = l2_table_open,
 374         .read = seq_read,
 375         .llseek = seq_lseek,
 376         .release = single_release,
 377 };
 378
 379 static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,
 380                              loff_t *ppos)
 381 {
 382         struct rtl838x_port *p = filp->private_data;
 383         struct dsa_switch *ds = p->dp->ds;
 384         struct rtl838x_switch_priv *priv = ds->priv;
 385         int value = sw_r32(priv->r->l2_port_aging_out);
 386
 387         if (value < 0)
 388                 return -EINVAL;
 389
 390         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 391 }
 392
 393 static ssize_t age_out_write(struct file *filp, const char __user *buffer,
 394                                 size_t count, loff_t *ppos)
 395 {
 396         struct rtl838x_port *p = filp->private_data;
 397         u32 value;
 398         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 399         if (res < 0)
 400                 return res;
 401
 402         rtl83xx_fast_age(p->dp->ds, p->dp->index);
 403
 404         return res;
 405 }
 406
 407 static const struct file_operations age_out_fops = {
 408         .owner = THIS_MODULE,
 409         .open = simple_open,
 410         .read = age_out_read,
 411         .write = age_out_write,
 412 };
 413
 414 static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,
 415                                 loff_t *ppos)
 416 {
 417         struct rtl838x_port *p = filp->private_data;
 418         struct dsa_switch *ds = p->dp->ds;
 419         struct rtl838x_switch_priv *priv = ds->priv;
 420         int value;
 421         if (priv->family_id == RTL8380_FAMILY_ID)
 422                 value = rtl838x_get_egress_rate(priv, p->dp->index);
 423         else
 424                 value = rtl839x_get_egress_rate(priv, p->dp->index);
 425
 426         if (value < 0)
 427                 return -EINVAL;
 428
 429         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 430 }
 431
 432 static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,
 433                                 size_t count, loff_t *ppos)
 434 {
 435         struct rtl838x_port *p = filp->private_data;
 436         struct dsa_switch *ds = p->dp->ds;
 437         struct rtl838x_switch_priv *priv = ds->priv;
 438         u32 value;
 439         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 440         if (res < 0)
 441                 return res;
 442
 443         if (priv->family_id == RTL8380_FAMILY_ID)
 444                 rtl838x_set_egress_rate(priv, p->dp->index, value);
 445         else
 446                 rtl839x_set_egress_rate(priv, p->dp->index, value);
 447
 448         return res;
 449 }
 450
 451 static const struct file_operations port_egress_fops = {
 452         .owner = THIS_MODULE,
 453         .open = simple_open,
 454         .read = port_egress_rate_read,
 455         .write = port_egress_rate_write,
 456 };
 457
 458
 459 static const struct debugfs_reg32 port_ctrl_regs[] = {
 460         { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
 461         { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
 462 };
 463
 464 void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
 465 {
 466         debugfs_remove_recursive(priv->dbgfs_dir);
 467
 468 //      kfree(priv->dbgfs_entries);
 469 }
 470
 471 static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
 472                                    int port)
 473 {
 474         struct dentry *port_dir;
 475         struct debugfs_regset32 *port_ctrl_regset;
 476
 477         port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
 478
 479         if (priv->family_id == RTL8380_FAMILY_ID) {
 480                 debugfs_create_x32("storm_rate_uc", 0644, port_dir,
 481                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
 482
 483                 debugfs_create_x32("storm_rate_mc", 0644, port_dir,
 484                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
 485
 486                 debugfs_create_x32("storm_rate_bc", 0644, port_dir,
 487                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
 488         } else {
 489                 debugfs_create_x32("storm_rate_uc", 0644, port_dir,
 490                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
 491
 492                 debugfs_create_x32("storm_rate_mc", 0644, port_dir,
 493                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
 494
 495                 debugfs_create_x32("storm_rate_bc", 0644, port_dir,
 496                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
 497         }
 498
 499         debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);
 500
 501         port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 502         if (!port_ctrl_regset)
 503                 return -ENOMEM;
 504
 505         port_ctrl_regset->regs = port_ctrl_regs;
 506         port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 507         port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2));
 508         debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 509
 510         debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops);
 511         debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops);
 512         debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port],
 513                             &port_egress_fops);
 514         return 0;
 515 }
 516
 517 static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv)
 518 {
 519         struct dentry *led_dir;
 520         int p;
 521         char led_sw_p_ctrl_name[20];
 522         char port_led_name[20];
 523
 524         led_dir = debugfs_create_dir("led", parent);
 525
 526         if (priv->family_id == RTL8380_FAMILY_ID) {
 527                 debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 528                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL));
 529                 debugfs_create_x32("led_mode_sel", 0644, led_dir,
 530                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL));
 531                 debugfs_create_x32("led_mode_ctrl", 0644, led_dir,
 532                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL));
 533                 debugfs_create_x32("led_p_en_ctrl", 0644, led_dir,
 534                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL));
 535                 debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 536                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL));
 537                 debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir,
 538                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL));
 539                 debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir,
 540                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL));
 541                 debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir,
 542                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL));
 543                 for (p = 0; p < 28; p++) {
 544                         snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),
 545                                  "led_sw_p_ctrl.%02d", p);
 546                         debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,
 547                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p)));
 548                 }
 549         } else if (priv->family_id == RTL8390_FAMILY_ID) {
 550                 debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 551                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
 552                 debugfs_create_x32("led_set_2_3", 0644, led_dir,
 553                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
 554                 debugfs_create_x32("led_set_0_1", 0644, led_dir,
 555                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
 556                 for (p = 0; p < 4; p++) {
 557                         snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p);
 558                         debugfs_create_x32(port_led_name, 0644, led_dir,
 559                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
 560                         snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p);
 561                         debugfs_create_x32(port_led_name, 0644, led_dir,
 562                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
 563                 }
 564                 debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir,
 565                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
 566                 debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir,
 567                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
 568                 debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir,
 569                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
 570                 debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir,
 571                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
 572                 debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir,
 573                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
 574                 debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir,
 575                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
 576                 debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 577                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
 578                 for (p = 0; p < 5; p++) {
 579                         snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p);
 580                         debugfs_create_x32(port_led_name, 0644, led_dir,
 581                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
 582                 }
 583                 for (p = 0; p < 28; p++) {
 584                         snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p);
 585                         debugfs_create_x32(port_led_name, 0644, led_dir,
 586                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
 587                 }
 588         }
 589         return 0;
 590 }
 591
 592 void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
 593 {
 594         struct dentry *rtl838x_dir;
 595         struct dentry *port_dir;
 596         struct dentry *mirror_dir;
 597         struct debugfs_regset32 *port_ctrl_regset;
 598         int ret, i;
 599         char lag_name[10];
 600         char mirror_name[10];
 601
 602         pr_info("%s called\n", __func__);
 603         rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
 604         if (!rtl838x_dir)
 605                 rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
 606
 607         priv->dbgfs_dir = rtl838x_dir;
 608
 609         debugfs_create_u32("soc", 0444, rtl838x_dir,
 610                            (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
 611
 612         /* Create one directory per port */
 613         for (i = 0; i < priv->cpu_port; i++) {
 614                 if (priv->ports[i].phy) {
 615                         ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
 616                         if (ret)
 617                                 goto err;
 618                 }
 619         }
 620
 621         /* Create directory for CPU-port */
 622         port_dir = debugfs_create_dir("cpu_port", rtl838x_dir);
 623         port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 624         if (!port_ctrl_regset) {
 625                 ret = -ENOMEM;
 626                 goto err;
 627         }
 628
 629         port_ctrl_regset->regs = port_ctrl_regs;
 630         port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 631         port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));
 632         debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 633         debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
 634
 635         /* Create entries for LAGs */
 636         for (i = 0; i < priv->n_lags; i++) {
 637                 snprintf(lag_name, sizeof(lag_name), "lag.%02d", i);
 638                 if (priv->family_id == RTL8380_FAMILY_ID)
 639                         debugfs_create_x32(lag_name, 0644, rtl838x_dir,
 640                                 (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 641                 else
 642                         debugfs_create_x64(lag_name, 0644, rtl838x_dir,
 643                                 (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 644         }
 645
 646         /* Create directories for mirror groups */
 647         for (i = 0; i < 4; i++) {
 648                 snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i);
 649                 mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);
 650                 if (priv->family_id == RTL8380_FAMILY_ID) {
 651                         debugfs_create_x32("ctrl", 0644, mirror_dir,
 652                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
 653                         debugfs_create_x32("ingress_pm", 0644, mirror_dir,
 654                                 (u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4));
 655                         debugfs_create_x32("egress_pm", 0644, mirror_dir,
 656                                 (u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4));
 657                         debugfs_create_x32("qid", 0644, mirror_dir,
 658                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
 659                         debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 660                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
 661                         debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir,
 662                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
 663                         debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 664                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
 665                         debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 666                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
 667                         debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 668                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
 669                 } else {
 670                         debugfs_create_x32("ctrl", 0644, mirror_dir,
 671                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
 672                         debugfs_create_x64("ingress_pm", 0644, mirror_dir,
 673                                 (u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8));
 674                         debugfs_create_x64("egress_pm", 0644, mirror_dir,
 675                                 (u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8));
 676                         debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 677                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
 678                         debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 679                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
 680                         debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 681                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
 682                         debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 683                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
 684                         debugfs_create_x64("sample_rate", 0644, mirror_dir,
 685                                 (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
 686                 }
 687         }
 688
 689         if (priv->family_id == RTL8380_FAMILY_ID)
 690                 debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir,
 691                                 (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 692         else
 693                 debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir,
 694                                 (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 695
 696         if (priv->family_id == RTL8380_FAMILY_ID)
 697                 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 698                                 (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
 699         else
 700                 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 701                                 (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
 702
 703         ret = rtl838x_dbgfs_leds(rtl838x_dir, priv);
 704         if (ret)
 705                 goto err;
 706
 707         debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops);
 708
 709         debugfs_create_file("l2_table", 0400, rtl838x_dir, priv, &l2_table_fops);
 710
 711         return;
 712 err:
 713         rtl838x_dbgfs_cleanup(priv);
 714 }
 715
 716 void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv)
 717 {
 718         struct dentry *dbg_dir;
 719
 720         pr_info("%s called\n", __func__);
 721         dbg_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
 722         if (!dbg_dir)
 723                 dbg_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
 724
 725         priv->dbgfs_dir = dbg_dir;
 726
 727         debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops);
 728
 729         debugfs_create_file("l2_table", 0400, dbg_dir, priv, &l2_table_fops);
 730 }