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realtek: add cond_resched to loops accessing the FDB table
[openwrt/staging/wigyori.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
166 int port, bool enable)
167 {
168 int shift = SALRN_PORT_SHIFT(port);
169 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
170
171 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
172 priv->r->l2_port_new_salrn(port));
173 }
174
175 static int rtl83xx_setup(struct dsa_switch *ds)
176 {
177 int i;
178 struct rtl838x_switch_priv *priv = ds->priv;
179 u64 port_bitmap = BIT_ULL(priv->cpu_port);
180
181 pr_debug("%s called\n", __func__);
182
183 /* Disable MAC polling the PHY so that we can start configuration */
184 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
185
186 for (i = 0; i < ds->num_ports; i++)
187 priv->ports[i].enable = false;
188 priv->ports[priv->cpu_port].enable = true;
189
190 /* Isolate ports from each other: traffic only CPU <-> port */
191 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
192 * traffic from source port i to destination port j
193 */
194 for (i = 0; i < priv->cpu_port; i++) {
195 if (priv->ports[i].phy) {
196 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
197 priv->r->port_iso_ctrl(i));
198 port_bitmap |= BIT_ULL(i);
199 }
200 }
201 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
202
203 if (priv->family_id == RTL8380_FAMILY_ID)
204 rtl838x_print_matrix();
205 else
206 rtl839x_print_matrix();
207
208 rtl83xx_init_stats(priv);
209
210 rtl83xx_vlan_setup(priv);
211
212 rtl83xx_setup_bpdu_traps(priv);
213
214 ds->configure_vlan_while_not_filtering = true;
215
216 priv->r->l2_learning_setup();
217
218 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
219 ds->assisted_learning_on_cpu_port = true;
220
221 /*
222 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
223 * 0: FWD, 1: DROP, 2: TRAP2CPU
224 */
225 if (priv->family_id == RTL8380_FAMILY_ID)
226 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
227 else
228 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
229
230 /* Enable MAC Polling PHY again */
231 rtl83xx_enable_phy_polling(priv);
232 pr_debug("Please wait until PHY is settled\n");
233 msleep(1000);
234 priv->r->pie_init(priv);
235
236 return 0;
237 }
238
239 static int rtl93xx_setup(struct dsa_switch *ds)
240 {
241 int i;
242 struct rtl838x_switch_priv *priv = ds->priv;
243 u32 port_bitmap = BIT(priv->cpu_port);
244
245 pr_info("%s called\n", __func__);
246
247 /* Disable MAC polling the PHY so that we can start configuration */
248 if (priv->family_id == RTL9300_FAMILY_ID)
249 sw_w32(0, RTL930X_SMI_POLL_CTRL);
250
251 if (priv->family_id == RTL9310_FAMILY_ID) {
252 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
253 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
254 }
255
256 // Disable all ports except CPU port
257 for (i = 0; i < ds->num_ports; i++)
258 priv->ports[i].enable = false;
259 priv->ports[priv->cpu_port].enable = true;
260
261 for (i = 0; i < priv->cpu_port; i++) {
262 if (priv->ports[i].phy) {
263 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
264 port_bitmap |= BIT_ULL(i);
265 }
266 }
267 priv->r->traffic_set(priv->cpu_port, port_bitmap);
268
269 rtl930x_print_matrix();
270
271 // TODO: Initialize statistics
272
273 rtl83xx_vlan_setup(priv);
274
275 ds->configure_vlan_while_not_filtering = true;
276
277 priv->r->l2_learning_setup();
278
279 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
280 ds->assisted_learning_on_cpu_port = true;
281
282 rtl83xx_enable_phy_polling(priv);
283
284 priv->r->pie_init(priv);
285
286 priv->r->led_init(priv);
287
288 return 0;
289 }
290
291 static int rtl93xx_get_sds(struct phy_device *phydev)
292 {
293 struct device *dev = &phydev->mdio.dev;
294 struct device_node *dn;
295 u32 sds_num;
296
297 if (!dev)
298 return -1;
299 if (dev->of_node) {
300 dn = dev->of_node;
301 if (of_property_read_u32(dn, "sds", &sds_num))
302 sds_num = -1;
303 } else {
304 dev_err(dev, "No DT node.\n");
305 return -1;
306 }
307
308 return sds_num;
309 }
310
311 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
312 unsigned long *supported,
313 struct phylink_link_state *state)
314 {
315 struct rtl838x_switch_priv *priv = ds->priv;
316 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
317
318 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
319
320 if (!phy_interface_mode_is_rgmii(state->interface) &&
321 state->interface != PHY_INTERFACE_MODE_NA &&
322 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
323 state->interface != PHY_INTERFACE_MODE_MII &&
324 state->interface != PHY_INTERFACE_MODE_REVMII &&
325 state->interface != PHY_INTERFACE_MODE_GMII &&
326 state->interface != PHY_INTERFACE_MODE_QSGMII &&
327 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
328 state->interface != PHY_INTERFACE_MODE_SGMII) {
329 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
330 dev_err(ds->dev,
331 "Unsupported interface: %d for port %d\n",
332 state->interface, port);
333 return;
334 }
335
336 /* Allow all the expected bits */
337 phylink_set(mask, Autoneg);
338 phylink_set_port_modes(mask);
339 phylink_set(mask, Pause);
340 phylink_set(mask, Asym_Pause);
341
342 /* With the exclusion of MII and Reverse MII, we support Gigabit,
343 * including Half duplex
344 */
345 if (state->interface != PHY_INTERFACE_MODE_MII &&
346 state->interface != PHY_INTERFACE_MODE_REVMII) {
347 phylink_set(mask, 1000baseT_Full);
348 phylink_set(mask, 1000baseT_Half);
349 }
350
351 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
352 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
353 phylink_set(mask, 1000baseX_Full);
354
355 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
356 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
357 phylink_set(mask, 1000baseX_Full);
358
359 phylink_set(mask, 10baseT_Half);
360 phylink_set(mask, 10baseT_Full);
361 phylink_set(mask, 100baseT_Half);
362 phylink_set(mask, 100baseT_Full);
363
364 bitmap_and(supported, supported, mask,
365 __ETHTOOL_LINK_MODE_MASK_NBITS);
366 bitmap_and(state->advertising, state->advertising, mask,
367 __ETHTOOL_LINK_MODE_MASK_NBITS);
368 }
369
370 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
371 unsigned long *supported,
372 struct phylink_link_state *state)
373 {
374 struct rtl838x_switch_priv *priv = ds->priv;
375 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
376
377 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
378 phy_modes(state->interface));
379
380 if (!phy_interface_mode_is_rgmii(state->interface) &&
381 state->interface != PHY_INTERFACE_MODE_NA &&
382 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
383 state->interface != PHY_INTERFACE_MODE_MII &&
384 state->interface != PHY_INTERFACE_MODE_REVMII &&
385 state->interface != PHY_INTERFACE_MODE_GMII &&
386 state->interface != PHY_INTERFACE_MODE_QSGMII &&
387 state->interface != PHY_INTERFACE_MODE_XGMII &&
388 state->interface != PHY_INTERFACE_MODE_HSGMII &&
389 state->interface != PHY_INTERFACE_MODE_10GBASER &&
390 state->interface != PHY_INTERFACE_MODE_10GKR &&
391 state->interface != PHY_INTERFACE_MODE_USXGMII &&
392 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
393 state->interface != PHY_INTERFACE_MODE_SGMII) {
394 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
395 dev_err(ds->dev,
396 "Unsupported interface: %d for port %d\n",
397 state->interface, port);
398 return;
399 }
400
401 /* Allow all the expected bits */
402 phylink_set(mask, Autoneg);
403 phylink_set_port_modes(mask);
404 phylink_set(mask, Pause);
405 phylink_set(mask, Asym_Pause);
406
407 /* With the exclusion of MII and Reverse MII, we support Gigabit,
408 * including Half duplex
409 */
410 if (state->interface != PHY_INTERFACE_MODE_MII &&
411 state->interface != PHY_INTERFACE_MODE_REVMII) {
412 phylink_set(mask, 1000baseT_Full);
413 phylink_set(mask, 1000baseT_Half);
414 }
415
416 // Internal phys of the RTL93xx family provide 10G
417 if (priv->ports[port].phy_is_integrated
418 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
419 phylink_set(mask, 1000baseX_Full);
420 } else if (priv->ports[port].phy_is_integrated) {
421 phylink_set(mask, 1000baseX_Full);
422 phylink_set(mask, 10000baseKR_Full);
423 phylink_set(mask, 10000baseSR_Full);
424 phylink_set(mask, 10000baseCR_Full);
425 }
426 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
427 phylink_set(mask, 1000baseX_Full);
428 phylink_set(mask, 1000baseT_Full);
429 phylink_set(mask, 10000baseKR_Full);
430 phylink_set(mask, 10000baseT_Full);
431 phylink_set(mask, 10000baseSR_Full);
432 phylink_set(mask, 10000baseCR_Full);
433 }
434
435 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
436 phylink_set(mask, 10000baseT_Full);
437
438 phylink_set(mask, 10baseT_Half);
439 phylink_set(mask, 10baseT_Full);
440 phylink_set(mask, 100baseT_Half);
441 phylink_set(mask, 100baseT_Full);
442
443 bitmap_and(supported, supported, mask,
444 __ETHTOOL_LINK_MODE_MASK_NBITS);
445 bitmap_and(state->advertising, state->advertising, mask,
446 __ETHTOOL_LINK_MODE_MASK_NBITS);
447 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
448 }
449
450 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
451 struct phylink_link_state *state)
452 {
453 struct rtl838x_switch_priv *priv = ds->priv;
454 u64 speed;
455 u64 link;
456
457 if (port < 0 || port > priv->cpu_port)
458 return -EINVAL;
459
460 state->link = 0;
461 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
462 if (link & BIT_ULL(port))
463 state->link = 1;
464 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
465
466 state->duplex = 0;
467 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
468 state->duplex = 1;
469
470 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
471 speed >>= (port % 16) << 1;
472 switch (speed & 0x3) {
473 case 0:
474 state->speed = SPEED_10;
475 break;
476 case 1:
477 state->speed = SPEED_100;
478 break;
479 case 2:
480 state->speed = SPEED_1000;
481 break;
482 case 3:
483 if (priv->family_id == RTL9300_FAMILY_ID
484 && (port == 24 || port == 26)) /* Internal serdes */
485 state->speed = SPEED_2500;
486 else
487 state->speed = SPEED_100; /* Is in fact 500Mbit */
488 }
489
490 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
491 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
492 state->pause |= MLO_PAUSE_RX;
493 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
494 state->pause |= MLO_PAUSE_TX;
495 return 1;
496 }
497
498 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
499 struct phylink_link_state *state)
500 {
501 struct rtl838x_switch_priv *priv = ds->priv;
502 u64 speed;
503 u64 link;
504 u64 media;
505
506 if (port < 0 || port > priv->cpu_port)
507 return -EINVAL;
508
509 /*
510 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
511 * state needs to be read twice in order to read a correct result.
512 * This would not be necessary for ports connected e.g. to RTL8218D
513 * PHYs.
514 */
515 state->link = 0;
516 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
517 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
518 if (link & BIT_ULL(port))
519 state->link = 1;
520
521 if (priv->family_id == RTL9310_FAMILY_ID)
522 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
523
524 if (priv->family_id == RTL9300_FAMILY_ID)
525 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
526
527 if (media & BIT_ULL(port))
528 state->link = 1;
529
530 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
531 link & BIT_ULL(port), media);
532
533 state->duplex = 0;
534 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
535 state->duplex = 1;
536
537 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
538 speed >>= (port % 8) << 2;
539 switch (speed & 0xf) {
540 case 0:
541 state->speed = SPEED_10;
542 break;
543 case 1:
544 state->speed = SPEED_100;
545 break;
546 case 2:
547 case 7:
548 state->speed = SPEED_1000;
549 break;
550 case 4:
551 state->speed = SPEED_10000;
552 break;
553 case 5:
554 case 8:
555 state->speed = SPEED_2500;
556 break;
557 case 6:
558 state->speed = SPEED_5000;
559 break;
560 default:
561 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
562 }
563
564 if (priv->family_id == RTL9310_FAMILY_ID
565 && (port >= 52 || port <= 55)) { /* Internal serdes */
566 state->speed = SPEED_10000;
567 state->link = 1;
568 state->duplex = 1;
569 }
570
571 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
572 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
573 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
574 state->pause |= MLO_PAUSE_RX;
575 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
576 state->pause |= MLO_PAUSE_TX;
577 return 1;
578 }
579
580 static void rtl83xx_config_interface(int port, phy_interface_t interface)
581 {
582 u32 old, int_shift, sds_shift;
583
584 switch (port) {
585 case 24:
586 int_shift = 0;
587 sds_shift = 5;
588 break;
589 case 26:
590 int_shift = 3;
591 sds_shift = 0;
592 break;
593 default:
594 return;
595 }
596
597 old = sw_r32(RTL838X_SDS_MODE_SEL);
598 switch (interface) {
599 case PHY_INTERFACE_MODE_1000BASEX:
600 if ((old >> sds_shift & 0x1f) == 4)
601 return;
602 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
603 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
604 break;
605 case PHY_INTERFACE_MODE_SGMII:
606 if ((old >> sds_shift & 0x1f) == 2)
607 return;
608 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
609 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
610 break;
611 default:
612 return;
613 }
614 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
615 }
616
617 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
618 unsigned int mode,
619 const struct phylink_link_state *state)
620 {
621 struct rtl838x_switch_priv *priv = ds->priv;
622 u32 reg;
623 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
624
625 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
626
627 if (port == priv->cpu_port) {
628 /* Set Speed, duplex, flow control
629 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
630 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
631 * | MEDIA_SEL
632 */
633 if (priv->family_id == RTL8380_FAMILY_ID) {
634 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
635 /* allow CRC errors on CPU-port */
636 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
637 } else {
638 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
639 }
640 return;
641 }
642
643 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
644 /* Auto-Negotiation does not work for MAC in RTL8390 */
645 if (priv->family_id == RTL8380_FAMILY_ID) {
646 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
647 pr_debug("PHY autonegotiates\n");
648 reg |= RTL838X_NWAY_EN;
649 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
650 rtl83xx_config_interface(port, state->interface);
651 return;
652 }
653 }
654
655 if (mode != MLO_AN_FIXED)
656 pr_debug("Fixed state.\n");
657
658 /* Clear id_mode_dis bit, and the existing port mode, let
659 * RGMII_MODE_EN bet set by mac_link_{up,down} */
660 if (priv->family_id == RTL8380_FAMILY_ID) {
661 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
662 if (state->pause & MLO_PAUSE_TXRX_MASK) {
663 if (state->pause & MLO_PAUSE_TX)
664 reg |= RTL838X_TX_PAUSE_EN;
665 reg |= RTL838X_RX_PAUSE_EN;
666 }
667 } else if (priv->family_id == RTL8390_FAMILY_ID) {
668 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
669 if (state->pause & MLO_PAUSE_TXRX_MASK) {
670 if (state->pause & MLO_PAUSE_TX)
671 reg |= RTL839X_TX_PAUSE_EN;
672 reg |= RTL839X_RX_PAUSE_EN;
673 }
674 }
675
676
677 reg &= ~(3 << speed_bit);
678 switch (state->speed) {
679 case SPEED_1000:
680 reg |= 2 << speed_bit;
681 break;
682 case SPEED_100:
683 reg |= 1 << speed_bit;
684 break;
685 default:
686 break; // Ignore, including 10MBit which has a speed value of 0
687 }
688
689 if (priv->family_id == RTL8380_FAMILY_ID) {
690 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
691 if (state->link)
692 reg |= RTL838X_FORCE_LINK_EN;
693 if (state->duplex == RTL838X_DUPLEX_MODE)
694 reg |= RTL838X_DUPLEX_MODE;
695 } else if (priv->family_id == RTL8390_FAMILY_ID) {
696 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
697 if (state->link)
698 reg |= RTL839X_FORCE_LINK_EN;
699 if (state->duplex == RTL839X_DUPLEX_MODE)
700 reg |= RTL839X_DUPLEX_MODE;
701 }
702
703 // LAG members must use DUPLEX and we need to enable the link
704 if (priv->lagmembers & BIT_ULL(port)) {
705 switch(priv->family_id) {
706 case RTL8380_FAMILY_ID:
707 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
708 break;
709 case RTL8390_FAMILY_ID:
710 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
711 break;
712 }
713 }
714
715 // Disable AN
716 if (priv->family_id == RTL8380_FAMILY_ID)
717 reg &= ~RTL838X_NWAY_EN;
718 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
719 }
720
721 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
722 unsigned int mode,
723 const struct phylink_link_state *state)
724 {
725 struct rtl838x_switch_priv *priv = ds->priv;
726 int sds_num;
727 u32 reg, band;
728
729 sds_num = priv->ports[port].sds_num;
730 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
731
732 switch (state->interface) {
733 case PHY_INTERFACE_MODE_HSGMII:
734 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
735 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
736 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
737 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
738 break;
739 case PHY_INTERFACE_MODE_1000BASEX:
740 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
741 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
742 break;
743 case PHY_INTERFACE_MODE_XGMII:
744 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
745 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
746 break;
747 case PHY_INTERFACE_MODE_10GBASER:
748 case PHY_INTERFACE_MODE_10GKR:
749 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
750 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
751 break;
752 case PHY_INTERFACE_MODE_USXGMII:
753 // Translates to MII_USXGMII_10GSXGMII
754 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
755 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
756 break;
757 case PHY_INTERFACE_MODE_SGMII:
758 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
759 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
760 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
761 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
762 break;
763 case PHY_INTERFACE_MODE_QSGMII:
764 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
765 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
766 break;
767 default:
768 pr_err("%s: unknown serdes mode: %s\n",
769 __func__, phy_modes(state->interface));
770 return;
771 }
772
773 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
774 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
775
776 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
777
778 reg &= ~(0xf << 12);
779 reg |= 0x2 << 12; // Set SMI speed to 0x2
780
781 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
782
783 if (priv->lagmembers & BIT_ULL(port))
784 reg |= RTL931X_DUPLEX_MODE;
785
786 if (state->duplex == DUPLEX_FULL)
787 reg |= RTL931X_DUPLEX_MODE;
788
789 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
790
791 }
792
793 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
794 unsigned int mode,
795 const struct phylink_link_state *state)
796 {
797 struct rtl838x_switch_priv *priv = ds->priv;
798 int sds_num, sds_mode;
799 u32 reg;
800
801 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
802 port, mode, phy_modes(state->interface), state->speed, state->link);
803
804 // Nothing to be done for the CPU-port
805 if (port == priv->cpu_port)
806 return;
807
808 if (priv->family_id == RTL9310_FAMILY_ID)
809 return rtl931x_phylink_mac_config(ds, port, mode, state);
810
811 sds_num = priv->ports[port].sds_num;
812 pr_info("%s SDS is %d\n", __func__, sds_num);
813 if (sds_num >= 0) {
814 switch (state->interface) {
815 case PHY_INTERFACE_MODE_HSGMII:
816 sds_mode = 0x12;
817 break;
818 case PHY_INTERFACE_MODE_1000BASEX:
819 sds_mode = 0x04;
820 break;
821 case PHY_INTERFACE_MODE_XGMII:
822 sds_mode = 0x10;
823 break;
824 case PHY_INTERFACE_MODE_10GBASER:
825 case PHY_INTERFACE_MODE_10GKR:
826 sds_mode = 0x1b; // 10G 1000X Auto
827 break;
828 case PHY_INTERFACE_MODE_USXGMII:
829 sds_mode = 0x0d;
830 break;
831 default:
832 pr_err("%s: unknown serdes mode: %s\n",
833 __func__, phy_modes(state->interface));
834 return;
835 }
836 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
837 rtl9300_serdes_setup(sds_num, state->interface);
838 }
839
840 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
841 reg &= ~(0xf << 3);
842
843 switch (state->speed) {
844 case SPEED_10000:
845 reg |= 4 << 3;
846 break;
847 case SPEED_5000:
848 reg |= 6 << 3;
849 break;
850 case SPEED_2500:
851 reg |= 5 << 3;
852 break;
853 case SPEED_1000:
854 reg |= 2 << 3;
855 break;
856 default:
857 reg |= 2 << 3;
858 break;
859 }
860
861 if (state->link)
862 reg |= RTL930X_FORCE_LINK_EN;
863
864 if (priv->lagmembers & BIT_ULL(port))
865 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
866
867 if (state->duplex == DUPLEX_FULL)
868 reg |= RTL930X_DUPLEX_MODE;
869
870 if (priv->ports[port].phy_is_integrated)
871 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
872 else
873 reg |= RTL930X_FORCE_EN;
874
875 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
876 }
877
878 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
879 unsigned int mode,
880 phy_interface_t interface)
881 {
882 struct rtl838x_switch_priv *priv = ds->priv;
883
884 /* Stop TX/RX to port */
885 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
886
887 // No longer force link
888 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
889 }
890
891 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
892 unsigned int mode,
893 phy_interface_t interface)
894 {
895 struct rtl838x_switch_priv *priv = ds->priv;
896 u32 v = 0;
897
898 /* Stop TX/RX to port */
899 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
900
901 // No longer force link
902 if (priv->family_id == RTL9300_FAMILY_ID)
903 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
904 else if (priv->family_id == RTL9310_FAMILY_ID)
905 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
906 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
907 }
908
909 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
910 unsigned int mode,
911 phy_interface_t interface,
912 struct phy_device *phydev,
913 int speed, int duplex,
914 bool tx_pause, bool rx_pause)
915 {
916 struct rtl838x_switch_priv *priv = ds->priv;
917 /* Restart TX/RX to port */
918 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
919 // TODO: Set speed/duplex/pauses
920 }
921
922 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
923 unsigned int mode,
924 phy_interface_t interface,
925 struct phy_device *phydev,
926 int speed, int duplex,
927 bool tx_pause, bool rx_pause)
928 {
929 struct rtl838x_switch_priv *priv = ds->priv;
930
931 /* Restart TX/RX to port */
932 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
933 // TODO: Set speed/duplex/pauses
934 }
935
936 static void rtl83xx_get_strings(struct dsa_switch *ds,
937 int port, u32 stringset, u8 *data)
938 {
939 int i;
940
941 if (stringset != ETH_SS_STATS)
942 return;
943
944 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
945 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
946 ETH_GSTRING_LEN);
947 }
948
949 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
950 uint64_t *data)
951 {
952 struct rtl838x_switch_priv *priv = ds->priv;
953 const struct rtl83xx_mib_desc *mib;
954 int i;
955 u64 h;
956
957 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
958 mib = &rtl83xx_mib[i];
959
960 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
961 if (mib->size == 2) {
962 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
963 data[i] |= h << 32;
964 }
965 }
966 }
967
968 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
969 {
970 if (sset != ETH_SS_STATS)
971 return 0;
972
973 return ARRAY_SIZE(rtl83xx_mib);
974 }
975
976 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
977 {
978 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
979 u64 portmask;
980
981 if (mc_group >= MAX_MC_GROUPS - 1)
982 return -1;
983
984 if (priv->is_lagmember[port]) {
985 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
986 return 0;
987 }
988
989 set_bit(mc_group, priv->mc_group_bm);
990 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
991 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
992 priv->r->write_mcast_pmask(mc_group, portmask);
993
994 return mc_group;
995 }
996
997 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
998 {
999 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1000
1001 pr_debug("%s: %d\n", __func__, port);
1002 if (priv->is_lagmember[port]) {
1003 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1004 return portmask;
1005 }
1006 portmask |= BIT_ULL(port);
1007 priv->r->write_mcast_pmask(mc_group, portmask);
1008
1009 return portmask;
1010 }
1011
1012 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1013 {
1014 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1015
1016 pr_debug("%s: %d\n", __func__, port);
1017 if (priv->is_lagmember[port]) {
1018 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1019 return portmask;
1020 }
1021 priv->r->write_mcast_pmask(mc_group, portmask);
1022 if (portmask == BIT_ULL(priv->cpu_port)) {
1023 portmask &= ~BIT_ULL(priv->cpu_port);
1024 priv->r->write_mcast_pmask(mc_group, portmask);
1025 clear_bit(mc_group, priv->mc_group_bm);
1026 }
1027
1028 return portmask;
1029 }
1030
1031 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1032 {
1033 int mc_group;
1034
1035 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1036 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1037 if (portmask & BIT_ULL(port)) {
1038 priv->mc_group_saves[mc_group] = port;
1039 rtl83xx_mc_group_del_port(priv, mc_group, port);
1040 }
1041 }
1042 }
1043
1044 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1045 {
1046 int mc_group;
1047
1048 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1049 if (priv->mc_group_saves[mc_group] == port) {
1050 rtl83xx_mc_group_add_port(priv, mc_group, port);
1051 priv->mc_group_saves[mc_group] = -1;
1052 }
1053 }
1054 }
1055
1056 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1057 struct phy_device *phydev)
1058 {
1059 struct rtl838x_switch_priv *priv = ds->priv;
1060 u64 v;
1061
1062 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1063 priv->ports[port].enable = true;
1064
1065 /* enable inner tagging on egress, do not keep any tags */
1066 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1067
1068 if (dsa_is_cpu_port(ds, port))
1069 return 0;
1070
1071 /* add port to switch mask of CPU_PORT */
1072 priv->r->traffic_enable(priv->cpu_port, port);
1073
1074 load_mcgroups(priv, port);
1075
1076 if (priv->is_lagmember[port]) {
1077 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1078 return 0;
1079 }
1080
1081 /* add all other ports in the same bridge to switch mask of port */
1082 v = priv->r->traffic_get(port);
1083 v |= priv->ports[port].pm;
1084 priv->r->traffic_set(port, v);
1085
1086 // TODO: Figure out if this is necessary
1087 if (priv->family_id == RTL9300_FAMILY_ID) {
1088 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1089 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1090 }
1091
1092 if (priv->ports[port].sds_num < 0)
1093 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1094
1095 return 0;
1096 }
1097
1098 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1099 {
1100 struct rtl838x_switch_priv *priv = ds->priv;
1101 u64 v;
1102
1103 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1104 /* you can only disable user ports */
1105 if (!dsa_is_user_port(ds, port))
1106 return;
1107
1108 // BUG: This does not work on RTL931X
1109 /* remove port from switch mask of CPU_PORT */
1110 priv->r->traffic_disable(priv->cpu_port, port);
1111 store_mcgroups(priv, port);
1112
1113 /* remove all other ports in the same bridge from switch mask of port */
1114 v = priv->r->traffic_get(port);
1115 v &= ~priv->ports[port].pm;
1116 priv->r->traffic_set(port, v);
1117
1118 priv->ports[port].enable = false;
1119 }
1120
1121 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1122 struct ethtool_eee *e)
1123 {
1124 struct rtl838x_switch_priv *priv = ds->priv;
1125
1126 if (e->eee_enabled && !priv->eee_enabled) {
1127 pr_info("Globally enabling EEE\n");
1128 priv->r->init_eee(priv, true);
1129 }
1130
1131 priv->r->port_eee_set(priv, port, e->eee_enabled);
1132
1133 if (e->eee_enabled)
1134 pr_info("Enabled EEE for port %d\n", port);
1135 else
1136 pr_info("Disabled EEE for port %d\n", port);
1137 return 0;
1138 }
1139
1140 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1141 struct ethtool_eee *e)
1142 {
1143 struct rtl838x_switch_priv *priv = ds->priv;
1144
1145 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1146
1147 priv->r->eee_port_ability(priv, e, port);
1148
1149 e->eee_enabled = priv->ports[port].eee_enabled;
1150
1151 e->eee_active = !!(e->advertised & e->lp_advertised);
1152
1153 return 0;
1154 }
1155
1156 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1157 struct ethtool_eee *e)
1158 {
1159 struct rtl838x_switch_priv *priv = ds->priv;
1160
1161 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1162 | SUPPORTED_2500baseX_Full;
1163
1164 priv->r->eee_port_ability(priv, e, port);
1165
1166 e->eee_enabled = priv->ports[port].eee_enabled;
1167
1168 e->eee_active = !!(e->advertised & e->lp_advertised);
1169
1170 return 0;
1171 }
1172
1173 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1174 {
1175 struct rtl838x_switch_priv *priv = ds->priv;
1176
1177 priv->r->set_ageing_time(msec);
1178 return 0;
1179 }
1180
1181 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1182 struct net_device *bridge)
1183 {
1184 struct rtl838x_switch_priv *priv = ds->priv;
1185 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1186 int i;
1187
1188 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1189
1190 if (priv->is_lagmember[port]) {
1191 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1192 return 0;
1193 }
1194
1195 mutex_lock(&priv->reg_mutex);
1196 for (i = 0; i < ds->num_ports; i++) {
1197 /* Add this port to the port matrix of the other ports in the
1198 * same bridge. If the port is disabled, port matrix is kept
1199 * and not being setup until the port becomes enabled.
1200 */
1201 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1202 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1203 continue;
1204 if (priv->ports[i].enable)
1205 priv->r->traffic_enable(i, port);
1206
1207 priv->ports[i].pm |= BIT_ULL(port);
1208 port_bitmap |= BIT_ULL(i);
1209 }
1210 }
1211 load_mcgroups(priv, port);
1212
1213 /* Add all other ports to this port matrix. */
1214 if (priv->ports[port].enable) {
1215 priv->r->traffic_enable(priv->cpu_port, port);
1216 v = priv->r->traffic_get(port);
1217 v |= port_bitmap;
1218 priv->r->traffic_set(port, v);
1219 }
1220 priv->ports[port].pm |= port_bitmap;
1221 mutex_unlock(&priv->reg_mutex);
1222
1223 return 0;
1224 }
1225
1226 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1227 struct net_device *bridge)
1228 {
1229 struct rtl838x_switch_priv *priv = ds->priv;
1230 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1231 int i;
1232
1233 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1234 mutex_lock(&priv->reg_mutex);
1235 for (i = 0; i < ds->num_ports; i++) {
1236 /* Remove this port from the port matrix of the other ports
1237 * in the same bridge. If the port is disabled, port matrix
1238 * is kept and not being setup until the port becomes enabled.
1239 * And the other port's port matrix cannot be broken when the
1240 * other port is still a VLAN-aware port.
1241 */
1242 if (dsa_is_user_port(ds, i) && i != port) {
1243 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1244 continue;
1245 if (priv->ports[i].enable)
1246 priv->r->traffic_disable(i, port);
1247
1248 priv->ports[i].pm |= BIT_ULL(port);
1249 port_bitmap &= ~BIT_ULL(i);
1250 }
1251 }
1252 store_mcgroups(priv, port);
1253
1254 /* Add all other ports to this port matrix. */
1255 if (priv->ports[port].enable) {
1256 v = priv->r->traffic_get(port);
1257 v |= port_bitmap;
1258 priv->r->traffic_set(port, v);
1259 }
1260 priv->ports[port].pm &= ~port_bitmap;
1261
1262 mutex_unlock(&priv->reg_mutex);
1263 }
1264
1265 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1266 {
1267 u32 msti = 0;
1268 u32 port_state[4];
1269 int index, bit;
1270 int pos = port;
1271 struct rtl838x_switch_priv *priv = ds->priv;
1272 int n = priv->port_width << 1;
1273
1274 /* Ports above or equal CPU port can never be configured */
1275 if (port >= priv->cpu_port)
1276 return;
1277
1278 mutex_lock(&priv->reg_mutex);
1279
1280 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1281 * have 64 bit fields, 839x and 931x have 128 bit fields
1282 */
1283 if (priv->family_id == RTL8390_FAMILY_ID)
1284 pos += 12;
1285 if (priv->family_id == RTL9300_FAMILY_ID)
1286 pos += 3;
1287 if (priv->family_id == RTL9310_FAMILY_ID)
1288 pos += 8;
1289
1290 index = n - (pos >> 4) - 1;
1291 bit = (pos << 1) % 32;
1292
1293 priv->r->stp_get(priv, msti, port_state);
1294
1295 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1296 port_state[index] &= ~(3 << bit);
1297
1298 switch (state) {
1299 case BR_STATE_DISABLED: /* 0 */
1300 port_state[index] |= (0 << bit);
1301 break;
1302 case BR_STATE_BLOCKING: /* 4 */
1303 case BR_STATE_LISTENING: /* 1 */
1304 port_state[index] |= (1 << bit);
1305 break;
1306 case BR_STATE_LEARNING: /* 2 */
1307 port_state[index] |= (2 << bit);
1308 break;
1309 case BR_STATE_FORWARDING: /* 3*/
1310 port_state[index] |= (3 << bit);
1311 default:
1312 break;
1313 }
1314
1315 priv->r->stp_set(priv, msti, port_state);
1316
1317 mutex_unlock(&priv->reg_mutex);
1318 }
1319
1320 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1321 {
1322 struct rtl838x_switch_priv *priv = ds->priv;
1323 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1324
1325 pr_debug("FAST AGE port %d\n", port);
1326 mutex_lock(&priv->reg_mutex);
1327 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1328 * port fields:
1329 * 0-4: Replacing port
1330 * 5-9: Flushed/replaced port
1331 * 10-21: FVID
1332 * 22: Entry types: 1: dynamic, 0: also static
1333 * 23: Match flush port
1334 * 24: Match FVID
1335 * 25: Flush (0) or replace (1) L2 entries
1336 * 26: Status of action (1: Start, 0: Done)
1337 */
1338 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1339
1340 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1341
1342 mutex_unlock(&priv->reg_mutex);
1343 }
1344
1345 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1346 {
1347 struct rtl838x_switch_priv *priv = ds->priv;
1348
1349 pr_info("%s port %d\n", __func__, port);
1350 mutex_lock(&priv->reg_mutex);
1351 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1352
1353 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1354
1355 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1356
1357 mutex_unlock(&priv->reg_mutex);
1358 }
1359
1360 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1361 {
1362 struct rtl838x_switch_priv *priv = ds->priv;
1363
1364 if (priv->family_id == RTL9310_FAMILY_ID)
1365 return rtl931x_fast_age(ds, port);
1366
1367 pr_debug("FAST AGE port %d\n", port);
1368 mutex_lock(&priv->reg_mutex);
1369 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1370
1371 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1372
1373 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1374
1375 mutex_unlock(&priv->reg_mutex);
1376 }
1377
1378 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1379 bool vlan_filtering,
1380 struct switchdev_trans *trans)
1381 {
1382 struct rtl838x_switch_priv *priv = ds->priv;
1383
1384 pr_debug("%s: port %d\n", __func__, port);
1385 mutex_lock(&priv->reg_mutex);
1386
1387 if (vlan_filtering) {
1388 /* Enable ingress and egress filtering
1389 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1390 * the filter action:
1391 * 0: Always Forward
1392 * 1: Drop packet
1393 * 2: Trap packet to CPU port
1394 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1395 */
1396 if (port != priv->cpu_port)
1397 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1398
1399 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1400 } else {
1401 /* Disable ingress and egress filtering */
1402 if (port != priv->cpu_port)
1403 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1404
1405 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1406 }
1407
1408 /* Do we need to do something to the CPU-Port, too? */
1409 mutex_unlock(&priv->reg_mutex);
1410
1411 return 0;
1412 }
1413
1414 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1415 const struct switchdev_obj_port_vlan *vlan)
1416 {
1417 struct rtl838x_vlan_info info;
1418 struct rtl838x_switch_priv *priv = ds->priv;
1419
1420 priv->r->vlan_tables_read(0, &info);
1421
1422 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1423 info.tagged_ports, info.untagged_ports, info.profile_id,
1424 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1425
1426 priv->r->vlan_tables_read(1, &info);
1427 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1428 info.tagged_ports, info.untagged_ports, info.profile_id,
1429 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1430 priv->r->vlan_set_untagged(1, info.untagged_ports);
1431 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1432
1433 priv->r->vlan_set_tagged(1, &info);
1434 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1435
1436 return 0;
1437 }
1438
1439 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1440 const struct switchdev_obj_port_vlan *vlan)
1441 {
1442 struct rtl838x_vlan_info info;
1443 struct rtl838x_switch_priv *priv = ds->priv;
1444 int v;
1445
1446 pr_debug("%s port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1447 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1448
1449 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1450 dev_err(priv->dev, "VLAN out of range: %d - %d",
1451 vlan->vid_begin, vlan->vid_end);
1452 return;
1453 }
1454
1455 mutex_lock(&priv->reg_mutex);
1456
1457 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1458 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1459 if (!v)
1460 continue;
1461 /* Set both inner and outer PVID of the port */
1462 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1463 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1464 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1465 PBVLAN_MODE_UNTAG_AND_PRITAG);
1466 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1467 PBVLAN_MODE_UNTAG_AND_PRITAG);
1468
1469 priv->ports[port].pvid = vlan->vid_end;
1470 }
1471 }
1472
1473 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1474 /* Get port memberships of this vlan */
1475 priv->r->vlan_tables_read(v, &info);
1476
1477 /* new VLAN? */
1478 if (!info.tagged_ports) {
1479 info.fid = 0;
1480 info.hash_mc_fid = false;
1481 info.hash_uc_fid = false;
1482 info.profile_id = 0;
1483 }
1484
1485 /* sanitize untagged_ports - must be a subset */
1486 if (info.untagged_ports & ~info.tagged_ports)
1487 info.untagged_ports = 0;
1488
1489 info.tagged_ports |= BIT_ULL(port);
1490 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1491 info.untagged_ports |= BIT_ULL(port);
1492
1493 priv->r->vlan_set_untagged(v, info.untagged_ports);
1494 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1495
1496 priv->r->vlan_set_tagged(v, &info);
1497 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1498 }
1499
1500 mutex_unlock(&priv->reg_mutex);
1501 }
1502
1503 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1504 const struct switchdev_obj_port_vlan *vlan)
1505 {
1506 struct rtl838x_vlan_info info;
1507 struct rtl838x_switch_priv *priv = ds->priv;
1508 int v;
1509 u16 pvid;
1510
1511 pr_debug("%s: port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1512 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1513
1514 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1515 dev_err(priv->dev, "VLAN out of range: %d - %d",
1516 vlan->vid_begin, vlan->vid_end);
1517 return -ENOTSUPP;
1518 }
1519
1520 mutex_lock(&priv->reg_mutex);
1521 pvid = priv->ports[port].pvid;
1522
1523 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1524 /* Reset to default if removing the current PVID */
1525 if (v == pvid) {
1526 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1527 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1528 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1529 PBVLAN_MODE_UNTAG_AND_PRITAG);
1530 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1531 PBVLAN_MODE_UNTAG_AND_PRITAG);
1532 }
1533 /* Get port memberships of this vlan */
1534 priv->r->vlan_tables_read(v, &info);
1535
1536 /* remove port from both tables */
1537 info.untagged_ports &= (~BIT_ULL(port));
1538 info.tagged_ports &= (~BIT_ULL(port));
1539
1540 priv->r->vlan_set_untagged(v, info.untagged_ports);
1541 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1542
1543 priv->r->vlan_set_tagged(v, &info);
1544 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1545 }
1546 mutex_unlock(&priv->reg_mutex);
1547
1548 return 0;
1549 }
1550
1551 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1552 {
1553 memset(e, 0, sizeof(*e));
1554
1555 e->type = L2_UNICAST;
1556 e->valid = true;
1557
1558 e->age = 3;
1559 e->is_static = true;
1560
1561 e->port = port;
1562
1563 e->rvid = e->vid = vid;
1564 e->is_ip_mc = e->is_ipv6_mc = false;
1565 u64_to_ether_addr(mac, e->mac);
1566 }
1567
1568 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1569 {
1570 memset(e, 0, sizeof(*e));
1571
1572 e->type = L2_MULTICAST;
1573 e->valid = true;
1574
1575 e->mc_portmask_index = mc_group;
1576
1577 e->rvid = e->vid = vid;
1578 e->is_ip_mc = e->is_ipv6_mc = false;
1579 u64_to_ether_addr(mac, e->mac);
1580 }
1581
1582 /*
1583 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1584 * over the entries in the bucket until either a matching entry is found or an empty slot
1585 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1586 * when an empty slot was found and must exist is false, the index of the slot is returned
1587 * when no slots are available returns -1
1588 */
1589 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1590 bool must_exist, struct rtl838x_l2_entry *e)
1591 {
1592 int i, idx = -1;
1593 u32 key = priv->r->l2_hash_key(priv, seed);
1594 u64 entry;
1595
1596 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1597 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1598 for (i = 0; i < priv->l2_bucket_size; i++) {
1599 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1600 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1601 if (must_exist && !e->valid)
1602 continue;
1603 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1604 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1605 break;
1606 }
1607 }
1608
1609 return idx;
1610 }
1611
1612 /*
1613 * Uses the seed to identify an entry in the CAM by looping over all its entries
1614 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1615 * when an empty slot was found the index of the slot is returned
1616 * when no slots are available returns -1
1617 */
1618 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1619 bool must_exist, struct rtl838x_l2_entry *e)
1620 {
1621 int i, idx = -1;
1622 u64 entry;
1623
1624 for (i = 0; i < 64; i++) {
1625 entry = priv->r->read_cam(i, e);
1626 if (!must_exist && !e->valid) {
1627 if (idx < 0) /* First empty entry? */
1628 idx = i;
1629 break;
1630 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1631 pr_debug("Found entry in CAM\n");
1632 idx = i;
1633 break;
1634 }
1635 }
1636 return idx;
1637 }
1638
1639 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1640 const unsigned char *addr, u16 vid)
1641 {
1642 struct rtl838x_switch_priv *priv = ds->priv;
1643 u64 mac = ether_addr_to_u64(addr);
1644 struct rtl838x_l2_entry e;
1645 int err = 0, idx;
1646 u64 seed = priv->r->l2_hash_seed(mac, vid);
1647
1648 if (priv->is_lagmember[port]) {
1649 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1650 return 0;
1651 }
1652
1653 mutex_lock(&priv->reg_mutex);
1654
1655 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1656
1657 // Found an existing or empty entry
1658 if (idx >= 0) {
1659 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1660 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1661 goto out;
1662 }
1663
1664 // Hash buckets full, try CAM
1665 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1666
1667 if (idx >= 0) {
1668 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1669 priv->r->write_cam(idx, &e);
1670 goto out;
1671 }
1672
1673 err = -ENOTSUPP;
1674 out:
1675 mutex_unlock(&priv->reg_mutex);
1676 return err;
1677 }
1678
1679 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1680 const unsigned char *addr, u16 vid)
1681 {
1682 struct rtl838x_switch_priv *priv = ds->priv;
1683 u64 mac = ether_addr_to_u64(addr);
1684 struct rtl838x_l2_entry e;
1685 int err = 0, idx;
1686 u64 seed = priv->r->l2_hash_seed(mac, vid);
1687
1688 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1689 mutex_lock(&priv->reg_mutex);
1690
1691 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1692
1693 if (idx >= 0) {
1694 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1695 e.valid = false;
1696 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1697 goto out;
1698 }
1699
1700 /* Check CAM for spillover from hash buckets */
1701 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1702
1703 if (idx >= 0) {
1704 e.valid = false;
1705 priv->r->write_cam(idx, &e);
1706 goto out;
1707 }
1708 err = -ENOENT;
1709 out:
1710 mutex_unlock(&priv->reg_mutex);
1711 return err;
1712 }
1713
1714 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1715 dsa_fdb_dump_cb_t *cb, void *data)
1716 {
1717 struct rtl838x_l2_entry e;
1718 struct rtl838x_switch_priv *priv = ds->priv;
1719 int i;
1720
1721 mutex_lock(&priv->reg_mutex);
1722
1723 for (i = 0; i < priv->fib_entries; i++) {
1724 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1725
1726 if (!e.valid)
1727 continue;
1728
1729 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1730 cb(e.mac, e.vid, e.is_static, data);
1731
1732 if (!((i + 1) % 64))
1733 cond_resched();
1734 }
1735
1736 for (i = 0; i < 64; i++) {
1737 priv->r->read_cam(i, &e);
1738
1739 if (!e.valid)
1740 continue;
1741
1742 if (e.port == port)
1743 cb(e.mac, e.vid, e.is_static, data);
1744 }
1745
1746 mutex_unlock(&priv->reg_mutex);
1747 return 0;
1748 }
1749
1750 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1751 const struct switchdev_obj_port_mdb *mdb)
1752 {
1753 struct rtl838x_switch_priv *priv = ds->priv;
1754
1755 if (priv->id >= 0x9300)
1756 return -EOPNOTSUPP;
1757
1758 return 0;
1759 }
1760
1761 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1762 const struct switchdev_obj_port_mdb *mdb)
1763 {
1764 struct rtl838x_switch_priv *priv = ds->priv;
1765 u64 mac = ether_addr_to_u64(mdb->addr);
1766 struct rtl838x_l2_entry e;
1767 int err = 0, idx;
1768 int vid = mdb->vid;
1769 u64 seed = priv->r->l2_hash_seed(mac, vid);
1770 int mc_group;
1771
1772 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1773
1774 if (priv->is_lagmember[port]) {
1775 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1776 return;
1777 }
1778
1779 mutex_lock(&priv->reg_mutex);
1780
1781 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1782
1783 // Found an existing or empty entry
1784 if (idx >= 0) {
1785 if (e.valid) {
1786 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1787 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1788 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1789 } else {
1790 pr_debug("New entry for seed %016llx\n", seed);
1791 mc_group = rtl83xx_mc_group_alloc(priv, port);
1792 if (mc_group < 0) {
1793 err = -ENOTSUPP;
1794 goto out;
1795 }
1796 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1797 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1798 }
1799 goto out;
1800 }
1801
1802 // Hash buckets full, try CAM
1803 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1804
1805 if (idx >= 0) {
1806 if (e.valid) {
1807 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1808 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1809 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1810 } else {
1811 pr_debug("New entry\n");
1812 mc_group = rtl83xx_mc_group_alloc(priv, port);
1813 if (mc_group < 0) {
1814 err = -ENOTSUPP;
1815 goto out;
1816 }
1817 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1818 priv->r->write_cam(idx, &e);
1819 }
1820 goto out;
1821 }
1822
1823 err = -ENOTSUPP;
1824 out:
1825 mutex_unlock(&priv->reg_mutex);
1826 if (err)
1827 dev_err(ds->dev, "failed to add MDB entry\n");
1828 }
1829
1830 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1831 const struct switchdev_obj_port_mdb *mdb)
1832 {
1833 struct rtl838x_switch_priv *priv = ds->priv;
1834 u64 mac = ether_addr_to_u64(mdb->addr);
1835 struct rtl838x_l2_entry e;
1836 int err = 0, idx;
1837 int vid = mdb->vid;
1838 u64 seed = priv->r->l2_hash_seed(mac, vid);
1839 u64 portmask;
1840
1841 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1842
1843 if (priv->is_lagmember[port]) {
1844 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1845 return 0;
1846 }
1847
1848 mutex_lock(&priv->reg_mutex);
1849
1850 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1851
1852 if (idx >= 0) {
1853 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1854 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1855 if (!portmask) {
1856 e.valid = false;
1857 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1858 }
1859 goto out;
1860 }
1861
1862 /* Check CAM for spillover from hash buckets */
1863 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1864
1865 if (idx >= 0) {
1866 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1867 if (!portmask) {
1868 e.valid = false;
1869 priv->r->write_cam(idx, &e);
1870 }
1871 goto out;
1872 }
1873 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1874 out:
1875 mutex_unlock(&priv->reg_mutex);
1876 return err;
1877 }
1878
1879 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1880 struct dsa_mall_mirror_tc_entry *mirror,
1881 bool ingress)
1882 {
1883 /* We support 4 mirror groups, one destination port per group */
1884 int group;
1885 struct rtl838x_switch_priv *priv = ds->priv;
1886 int ctrl_reg, dpm_reg, spm_reg;
1887
1888 pr_debug("In %s\n", __func__);
1889
1890 for (group = 0; group < 4; group++) {
1891 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1892 break;
1893 }
1894 if (group >= 4) {
1895 for (group = 0; group < 4; group++) {
1896 if (priv->mirror_group_ports[group] < 0)
1897 break;
1898 }
1899 }
1900
1901 if (group >= 4)
1902 return -ENOSPC;
1903
1904 ctrl_reg = priv->r->mir_ctrl + group * 4;
1905 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1906 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1907
1908 pr_debug("Using group %d\n", group);
1909 mutex_lock(&priv->reg_mutex);
1910
1911 if (priv->family_id == RTL8380_FAMILY_ID) {
1912 /* Enable mirroring to port across VLANs (bit 11) */
1913 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1914 } else {
1915 /* Enable mirroring to destination port */
1916 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1917 }
1918
1919 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1920 mutex_unlock(&priv->reg_mutex);
1921 return -EEXIST;
1922 }
1923 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1924 mutex_unlock(&priv->reg_mutex);
1925 return -EEXIST;
1926 }
1927
1928 if (ingress)
1929 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1930 else
1931 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1932
1933 priv->mirror_group_ports[group] = mirror->to_local_port;
1934 mutex_unlock(&priv->reg_mutex);
1935 return 0;
1936 }
1937
1938 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1939 struct dsa_mall_mirror_tc_entry *mirror)
1940 {
1941 int group = 0;
1942 struct rtl838x_switch_priv *priv = ds->priv;
1943 int ctrl_reg, dpm_reg, spm_reg;
1944
1945 pr_debug("In %s\n", __func__);
1946 for (group = 0; group < 4; group++) {
1947 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1948 break;
1949 }
1950 if (group >= 4)
1951 return;
1952
1953 ctrl_reg = priv->r->mir_ctrl + group * 4;
1954 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1955 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1956
1957 mutex_lock(&priv->reg_mutex);
1958 if (mirror->ingress) {
1959 /* Ingress, clear source port matrix */
1960 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1961 } else {
1962 /* Egress, clear destination port matrix */
1963 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1964 }
1965
1966 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1967 priv->mirror_group_ports[group] = -1;
1968 sw_w32(0, ctrl_reg);
1969 }
1970
1971 mutex_unlock(&priv->reg_mutex);
1972 }
1973
1974 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1975 {
1976 struct rtl838x_switch_priv *priv = ds->priv;
1977 unsigned long features = 0;
1978 pr_debug("%s: %d %lX\n", __func__, port, flags);
1979 if (priv->r->enable_learning)
1980 features |= BR_LEARNING;
1981 if (priv->r->enable_flood)
1982 features |= BR_FLOOD;
1983 if (priv->r->enable_mcast_flood)
1984 features |= BR_MCAST_FLOOD;
1985 if (priv->r->enable_bcast_flood)
1986 features |= BR_BCAST_FLOOD;
1987 if (flags & ~(features))
1988 return -EINVAL;
1989
1990 return 0;
1991 }
1992
1993 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1994 {
1995 struct rtl838x_switch_priv *priv = ds->priv;
1996
1997 pr_debug("%s: %d %lX\n", __func__, port, flags);
1998 if (priv->r->enable_learning)
1999 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
2000
2001 if (priv->r->enable_flood)
2002 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
2003
2004 if (priv->r->enable_mcast_flood)
2005 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
2006
2007 if (priv->r->enable_bcast_flood)
2008 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
2009
2010 return 0;
2011 }
2012
2013 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2014 struct net_device *lag,
2015 struct netdev_lag_upper_info *info)
2016 {
2017 int id;
2018
2019 id = dsa_lag_id(ds->dst, lag);
2020 if (id < 0 || id >= ds->num_lag_ids)
2021 return false;
2022
2023 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2024 return false;
2025 }
2026 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2027 return false;
2028
2029 return true;
2030 }
2031
2032 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2033 {
2034 struct rtl838x_switch_priv *priv = ds->priv;
2035
2036 pr_debug("%s: %d\n", __func__, port);
2037 // Nothing to be done...
2038
2039 return 0;
2040 }
2041
2042 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2043 struct net_device *lag,
2044 struct netdev_lag_upper_info *info)
2045 {
2046 struct rtl838x_switch_priv *priv = ds->priv;
2047 int i, err = 0;
2048
2049 if (!rtl83xx_lag_can_offload(ds, lag, info))
2050 return -EOPNOTSUPP;
2051
2052 mutex_lock(&priv->reg_mutex);
2053
2054 for (i = 0; i < priv->n_lags; i++) {
2055 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2056 break;
2057 }
2058 if (port >= priv->cpu_port) {
2059 err = -EINVAL;
2060 goto out;
2061 }
2062 pr_info("port_lag_join: group %d, port %d\n",i, port);
2063 if (!priv->lag_devs[i])
2064 priv->lag_devs[i] = lag;
2065
2066 if (priv->lag_primary[i]==-1) {
2067 priv->lag_primary[i]=port;
2068 } else
2069 priv->is_lagmember[port] = 1;
2070
2071 priv->lagmembers |= (1ULL << port);
2072
2073 pr_debug("lag_members = %llX\n", priv->lagmembers);
2074 err = rtl83xx_lag_add(priv->ds, i, port, info);
2075 if (err) {
2076 err = -EINVAL;
2077 goto out;
2078 }
2079
2080 out:
2081 mutex_unlock(&priv->reg_mutex);
2082 return err;
2083
2084 }
2085
2086 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2087 struct net_device *lag)
2088 {
2089 int i, group = -1, err;
2090 struct rtl838x_switch_priv *priv = ds->priv;
2091
2092 mutex_lock(&priv->reg_mutex);
2093 for (i=0;i<priv->n_lags;i++) {
2094 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2095 group = i;
2096 break;
2097 }
2098 }
2099
2100 if (group == -1) {
2101 pr_info("port_lag_leave: port %d is not a member\n", port);
2102 err = -EINVAL;
2103 goto out;
2104 }
2105
2106 if (port >= priv->cpu_port) {
2107 err = -EINVAL;
2108 goto out;
2109 }
2110 pr_info("port_lag_del: group %d, port %d\n",group, port);
2111 priv->lagmembers &=~ (1ULL << port);
2112 priv->lag_primary[i] = -1;
2113 priv->is_lagmember[port] = 0;
2114 pr_debug("lag_members = %llX\n", priv->lagmembers);
2115 err = rtl83xx_lag_del(priv->ds, group, port);
2116 if (err) {
2117 err = -EINVAL;
2118 goto out;
2119 }
2120 if (!priv->lags_port_members[i])
2121 priv->lag_devs[i] = NULL;
2122
2123 out:
2124 mutex_unlock(&priv->reg_mutex);
2125 return 0;
2126 }
2127
2128 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2129 {
2130 u32 val;
2131 u32 offset = 0;
2132 struct rtl838x_switch_priv *priv = ds->priv;
2133
2134 if (phy_addr >= 24 && phy_addr <= 27
2135 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2136 if (phy_addr == 26)
2137 offset = 0x100;
2138 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2139 return val;
2140 }
2141
2142 read_phy(phy_addr, 0, phy_reg, &val);
2143 return val;
2144 }
2145
2146 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2147 {
2148 u32 offset = 0;
2149 struct rtl838x_switch_priv *priv = ds->priv;
2150
2151 if (phy_addr >= 24 && phy_addr <= 27
2152 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2153 if (phy_addr == 26)
2154 offset = 0x100;
2155 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2156 return 0;
2157 }
2158 return write_phy(phy_addr, 0, phy_reg, val);
2159 }
2160
2161 const struct dsa_switch_ops rtl83xx_switch_ops = {
2162 .get_tag_protocol = rtl83xx_get_tag_protocol,
2163 .setup = rtl83xx_setup,
2164
2165 .phy_read = dsa_phy_read,
2166 .phy_write = dsa_phy_write,
2167
2168 .phylink_validate = rtl83xx_phylink_validate,
2169 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2170 .phylink_mac_config = rtl83xx_phylink_mac_config,
2171 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2172 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2173
2174 .get_strings = rtl83xx_get_strings,
2175 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2176 .get_sset_count = rtl83xx_get_sset_count,
2177
2178 .port_enable = rtl83xx_port_enable,
2179 .port_disable = rtl83xx_port_disable,
2180
2181 .get_mac_eee = rtl83xx_get_mac_eee,
2182 .set_mac_eee = rtl83xx_set_mac_eee,
2183
2184 .set_ageing_time = rtl83xx_set_ageing_time,
2185 .port_bridge_join = rtl83xx_port_bridge_join,
2186 .port_bridge_leave = rtl83xx_port_bridge_leave,
2187 .port_stp_state_set = rtl83xx_port_stp_state_set,
2188 .port_fast_age = rtl83xx_fast_age,
2189
2190 .port_vlan_filtering = rtl83xx_vlan_filtering,
2191 .port_vlan_prepare = rtl83xx_vlan_prepare,
2192 .port_vlan_add = rtl83xx_vlan_add,
2193 .port_vlan_del = rtl83xx_vlan_del,
2194
2195 .port_fdb_add = rtl83xx_port_fdb_add,
2196 .port_fdb_del = rtl83xx_port_fdb_del,
2197 .port_fdb_dump = rtl83xx_port_fdb_dump,
2198
2199 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2200 .port_mdb_add = rtl83xx_port_mdb_add,
2201 .port_mdb_del = rtl83xx_port_mdb_del,
2202
2203 .port_mirror_add = rtl83xx_port_mirror_add,
2204 .port_mirror_del = rtl83xx_port_mirror_del,
2205
2206 .port_lag_change = rtl83xx_port_lag_change,
2207 .port_lag_join = rtl83xx_port_lag_join,
2208 .port_lag_leave = rtl83xx_port_lag_leave,
2209
2210 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2211 .port_bridge_flags = rtl83xx_port_bridge_flags,
2212 };
2213
2214 const struct dsa_switch_ops rtl930x_switch_ops = {
2215 .get_tag_protocol = rtl83xx_get_tag_protocol,
2216 .setup = rtl93xx_setup,
2217
2218 .phy_read = dsa_phy_read,
2219 .phy_write = dsa_phy_write,
2220
2221 .phylink_validate = rtl93xx_phylink_validate,
2222 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2223 .phylink_mac_config = rtl93xx_phylink_mac_config,
2224 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2225 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2226
2227 .get_strings = rtl83xx_get_strings,
2228 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2229 .get_sset_count = rtl83xx_get_sset_count,
2230
2231 .port_enable = rtl83xx_port_enable,
2232 .port_disable = rtl83xx_port_disable,
2233
2234 .get_mac_eee = rtl93xx_get_mac_eee,
2235 .set_mac_eee = rtl83xx_set_mac_eee,
2236
2237 .set_ageing_time = rtl83xx_set_ageing_time,
2238 .port_bridge_join = rtl83xx_port_bridge_join,
2239 .port_bridge_leave = rtl83xx_port_bridge_leave,
2240 .port_stp_state_set = rtl83xx_port_stp_state_set,
2241 .port_fast_age = rtl930x_fast_age,
2242
2243 .port_vlan_filtering = rtl83xx_vlan_filtering,
2244 .port_vlan_prepare = rtl83xx_vlan_prepare,
2245 .port_vlan_add = rtl83xx_vlan_add,
2246 .port_vlan_del = rtl83xx_vlan_del,
2247
2248 .port_fdb_add = rtl83xx_port_fdb_add,
2249 .port_fdb_del = rtl83xx_port_fdb_del,
2250 .port_fdb_dump = rtl83xx_port_fdb_dump,
2251
2252 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2253 .port_mdb_add = rtl83xx_port_mdb_add,
2254 .port_mdb_del = rtl83xx_port_mdb_del,
2255
2256 .port_lag_change = rtl83xx_port_lag_change,
2257 .port_lag_join = rtl83xx_port_lag_join,
2258 .port_lag_leave = rtl83xx_port_lag_leave,
2259
2260 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2261 .port_bridge_flags = rtl83xx_port_bridge_flags,
2262 };
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