target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch

   1 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
   2 index 581d23287333..487899d4cc3f 100644
   3 --- a/drivers/pwm/pwm-sun4i.c
   4 +++ b/drivers/pwm/pwm-sun4i.c
   5 @@ -16,6 +16,7 @@
   6  #include <linux/of_device.h>
   7  #include <linux/platform_device.h>
   8  #include <linux/pwm.h>
   9 +#include <linux/reset.h>
  10  #include <linux/slab.h>
  11  #include <linux/spinlock.h>
  12  #include <linux/time.h>
  13 @@ -78,6 +79,7 @@ struct sun4i_pwm_data {
  14  struct sun4i_pwm_chip {
  15         struct pwm_chip chip;
  16         struct clk *clk;
  17 +       struct reset_control *rst;
  18         void __iomem *base;
  19         spinlock_t ctrl_lock;
  20         const struct sun4i_pwm_data *data;
  21 @@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
  22         if (IS_ERR(pwm->clk))
  23                 return PTR_ERR(pwm->clk);
  24
  25 +       pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  26 +       if (IS_ERR(pwm->rst)) {
  27 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
  28 +                       dev_err(&pdev->dev, "get reset failed %pe\n",
  29 +                               pwm->rst);
  30 +               return PTR_ERR(pwm->rst);
  31 +       }
  32 +
  33 +       /* Deassert reset */
  34 +       ret = reset_control_deassert(pwm->rst);
  35 +       if (ret) {
  36 +               dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
  37 +                       ERR_PTR(ret));
  38 +               return ret;
  39 +       }
  40 +
  41         pwm->chip.dev = &pdev->dev;
  42         pwm->chip.ops = &sun4i_pwm_ops;
  43         pwm->chip.base = -1;
  44 @@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
  45         ret = pwmchip_add(&pwm->chip);
  46         if (ret < 0) {
  47                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  48 -               return ret;
  49 +               goto err_pwm_add;
  50         }
  51
  52         platform_set_drvdata(pdev, pwm);
  53
  54         return 0;
  55 +
  56 +err_pwm_add:
  57 +       reset_control_assert(pwm->rst);
  58 +
  59 +       return ret;
  60  }
  61
  62  static int sun4i_pwm_remove(struct platform_device *pdev)
  63  {
  64         struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
  65 +       int ret;
  66 +
  67 +       ret = pwmchip_remove(&pwm->chip);
  68 +       if (ret)
  69 +               return ret;
  70 +
  71 +       reset_control_assert(pwm->rst);
  72
  73 -       return pwmchip_remove(&pwm->chip);
  74 +       return 0;
  75  }
  76
  77  static struct platform_driver sun4i_pwm_driver = {
  78
  79 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
  80 index 487899d4cc3f..80026167044b 100644
  81 --- a/drivers/pwm/pwm-sun4i.c
  82 +++ b/drivers/pwm/pwm-sun4i.c
  83 @@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
  84         if (IS_ERR(pwm->base))
  85                 return PTR_ERR(pwm->base);
  86
  87 -       pwm->clk = devm_clk_get(&pdev->dev, NULL);
  88 -       if (IS_ERR(pwm->clk))
  89 +       /*
  90 +        * All hardware variants need a source clock that is divided and
  91 +        * then feeds the counter that defines the output wave form. In the
  92 +        * device tree this clock is either unnamed or called "mod".
  93 +        * Some variants (e.g. H6) need another clock to access the
  94 +        * hardware registers; this is called "bus".
  95 +        * So we request "mod" first (and ignore the corner case that a
  96 +        * parent provides a "mod" clock while the right one would be the
  97 +        * unnamed one of the PWM device) and if this is not found we fall
  98 +        * back to the first clock of the PWM.
  99 +        */
 100 +       pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
 101 +       if (IS_ERR(pwm->clk)) {
 102 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 103 +                       dev_err(&pdev->dev, "get mod clock failed %pe\n",
 104 +                               pwm->clk);
 105                 return PTR_ERR(pwm->clk);
 106 +       }
 107 +
 108 +       if (!pwm->clk) {
 109 +               pwm->clk = devm_clk_get(&pdev->dev, NULL);
 110 +               if (IS_ERR(pwm->clk)) {
 111 +                       if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 112 +                               dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
 113 +                                       pwm->clk);
 114 +                       return PTR_ERR(pwm->clk);
 115 +               }
 116 +       }
 117
 118         pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 119         if (IS_ERR(pwm->rst)) {
 120
 121 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
 122 index 80026167044b..a6727dd89e28 100644
 123 --- a/drivers/pwm/pwm-sun4i.c
 124 +++ b/drivers/pwm/pwm-sun4i.c
 125 @@ -78,6 +78,7 @@ struct sun4i_pwm_data {
 126
 127  struct sun4i_pwm_chip {
 128         struct pwm_chip chip;
 129 +       struct clk *bus_clk;
 130         struct clk *clk;
 131         struct reset_control *rst;
 132         void __iomem *base;
 133 @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 134                 }
 135         }
 136
 137 +       pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
 138 +       if (IS_ERR(pwm->bus_clk)) {
 139 +               if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 140 +                       dev_err(&pdev->dev, "get bus clock failed %pe\n",
 141 +                               pwm->bus_clk);
 142 +               return PTR_ERR(pwm->bus_clk);
 143 +       }
 144 +
 145         pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 146         if (IS_ERR(pwm->rst)) {
 147                 if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 148 @@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 149                 return ret;
 150         }
 151
 152 +       /*
 153 +        * We're keeping the bus clock on for the sake of simplicity.
 154 +        * Actually it only needs to be on for hardware register accesses.
 155 +        */
 156 +       ret = clk_prepare_enable(pwm->bus_clk);
 157 +       if (ret) {
 158 +               dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
 159 +                       ERR_PTR(ret));
 160 +               goto err_bus;
 161 +       }
 162 +
 163         pwm->chip.dev = &pdev->dev;
 164         pwm->chip.ops = &sun4i_pwm_ops;
 165         pwm->chip.base = -1;
 166 @@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 167         return 0;
 168
 169  err_pwm_add:
 170 +       clk_disable_unprepare(pwm->bus_clk);
 171 +err_bus:
 172         reset_control_assert(pwm->rst);
 173
 174         return ret;
 175 @@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
 176         if (ret)
 177                 return ret;
 178
 179 +       clk_disable_unprepare(pwm->bus_clk);
 180         reset_control_assert(pwm->rst);
 181
 182         return 0;
 183
 184 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
 185 index a6727dd89e28..e369b5a398f4 100644
 186 --- a/drivers/pwm/pwm-sun4i.c
 187 +++ b/drivers/pwm/pwm-sun4i.c
 188 @@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 189  {
 190         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 191         struct pwm_state cstate;
 192 -       u32 ctrl;
 193 +       u32 ctrl, duty, period, val;
 194         int ret;
 195 -       unsigned int delay_us;
 196 +       unsigned int delay_us, prescaler;
 197         unsigned long now;
 198
 199         pwm_get_state(pwm, &cstate);
 200 @@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 201         spin_lock(&sun4i_pwm->ctrl_lock);
 202         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 203
 204 -       if ((cstate.period != state->period) ||
 205 -           (cstate.duty_cycle != state->duty_cycle)) {
 206 -               u32 period, duty, val;
 207 -               unsigned int prescaler;
 208 -
 209 -               ret = sun4i_pwm_calculate(sun4i_pwm, state,
 210 -                                         &duty, &period, &prescaler);
 211 -               if (ret) {
 212 -                       dev_err(chip->dev, "period exceeds the maximum value\n");
 213 -                       spin_unlock(&sun4i_pwm->ctrl_lock);
 214 -                       if (!cstate.enabled)
 215 -                               clk_disable_unprepare(sun4i_pwm->clk);
 216 -                       return ret;
 217 -               }
 218 -
 219 -               if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 220 -                       /* Prescaler changed, the clock has to be gated */
 221 -                       ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 222 -                       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 223 +       ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
 224 +       if (ret) {
 225 +               dev_err(chip->dev, "period exceeds the maximum value\n");
 226 +               spin_unlock(&sun4i_pwm->ctrl_lock);
 227 +               if (!cstate.enabled)
 228 +                       clk_disable_unprepare(sun4i_pwm->clk);
 229 +               return ret;
 230 +       }
 231
 232 -                       ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 233 -                       ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 234 -               }
 235 +       if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 236 +               /* Prescaler changed, the clock has to be gated */
 237 +               ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 238 +               sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 239
 240 -               val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 241 -               sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 242 -               sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 243 -                       usecs_to_jiffies(cstate.period / 1000 + 1);
 244 -               sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 245 +               ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 246 +               ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 247         }
 248
 249 +       val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 250 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 251 +       sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 252 +               usecs_to_jiffies(cstate.period / 1000 + 1);
 253 +       sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 254 +
 255         if (state->polarity != PWM_POLARITY_NORMAL)
 256                 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 257         else
 258                 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 259
 260         ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 261 +
 262         if (state->enabled) {
 263                 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 264         } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 265
 266 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
 267 index e369b5a398f4..07bf7be6074b 100644
 268 --- a/drivers/pwm/pwm-sun4i.c
 269 +++ b/drivers/pwm/pwm-sun4i.c
 270 @@ -3,6 +3,10 @@
 271   * Driver for Allwinner sun4i Pulse Width Modulation Controller
 272   *
 273   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
 274 + *
 275 + * Limitations:
 276 + * - When outputing the source clock directly, the PWM logic will be bypassed
 277 + *   and the currently running period is not guaranteed to be completed
 278   */
 279
 280  #include <linux/bitops.h>
 281 @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
 282
 283  struct sun4i_pwm_data {
 284         bool has_prescaler_bypass;
 285 +       bool has_direct_mod_clk_output;
 286         unsigned int npwm;
 287  };
 288
 289 @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 290
 291         val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 292
 293 +       /*
 294 +        * PWM chapter in H6 manual has a diagram which explains that if bypass
 295 +        * bit is set, no other setting has any meaning. Even more, experiment
 296 +        * proved that also enable bit is ignored in this case.
 297 +        */
 298 +       if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
 299 +           sun4i_pwm->data->has_direct_mod_clk_output) {
 300 +               state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
 301 +               state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
 302 +               state->polarity = PWM_POLARITY_NORMAL;
 303 +               state->enabled = true;
 304 +               return;
 305 +       }
 306 +
 307         if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
 308             sun4i_pwm->data->has_prescaler_bypass)
 309                 prescaler = 1;
 310 @@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 311
 312  static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
 313                                const struct pwm_state *state,
 314 -                              u32 *dty, u32 *prd, unsigned int *prsclr)
 315 +                              u32 *dty, u32 *prd, unsigned int *prsclr,
 316 +                              bool *bypass)
 317  {
 318         u64 clk_rate, div = 0;
 319         unsigned int pval, prescaler = 0;
 320
 321         clk_rate = clk_get_rate(sun4i_pwm->clk);
 322
 323 +       *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
 324 +                 state->enabled &&
 325 +                 (state->period * clk_rate >= NSEC_PER_SEC) &&
 326 +                 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
 327 +                 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
 328 +
 329 +       /* Skip calculation of other parameters if we bypass them */
 330 +       if (*bypass)
 331 +               return 0;
 332 +
 333         if (sun4i_pwm->data->has_prescaler_bypass) {
 334                 /* First, test without any prescaler when available */
 335                 prescaler = PWM_PRESCAL_MASK;
 336 @@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 337         int ret;
 338         unsigned int delay_us, prescaler;
 339         unsigned long now;
 340 +       bool bypass;
 341
 342         pwm_get_state(pwm, &cstate);
 343
 344 @@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 345         spin_lock(&sun4i_pwm->ctrl_lock);
 346         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 347
 348 -       ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
 349 +       ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
 350 +                                 &bypass);
 351         if (ret) {
 352                 dev_err(chip->dev, "period exceeds the maximum value\n");
 353                 spin_unlock(&sun4i_pwm->ctrl_lock);
 354 @@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 355                 return ret;
 356         }
 357
 358 +       if (sun4i_pwm->data->has_direct_mod_clk_output) {
 359 +               if (bypass) {
 360 +                       ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
 361 +                       /* We can skip other parameter */
 362 +                       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 363 +                       spin_unlock(&sun4i_pwm->ctrl_lock);
 364 +                       return 0;
 365 +               } else {
 366 +                       ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
 367 +               }
 368 +       }
 369 +
 370         if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 371                 /* Prescaler changed, the clock has to be gated */
 372                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 373
 374 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
 375 index 07bf7be6074b..c394878c7e5d 100644
 376 --- a/drivers/pwm/pwm-sun4i.c
 377 +++ b/drivers/pwm/pwm-sun4i.c
 378 @@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
 379         .npwm = 1,
 380  };
 381
 382 +static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
 383 +       .has_prescaler_bypass = true,
 384 +       .has_direct_mod_clk_output = true,
 385 +       .npwm = 2,
 386 +};
 387 +
 388  static const struct of_device_id sun4i_pwm_dt_ids[] = {
 389         {
 390                 .compatible = "allwinner,sun4i-a10-pwm",
 391 @@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
 392         }, {
 393                 .compatible = "allwinner,sun8i-h3-pwm",
 394                 .data = &sun4i_pwm_single_bypass,
 395 +       }, {
 396 +               .compatible = "allwinner,sun50i-h6-pwm",
 397 +               .data = &sun50i_h6_pwm_data,
 398         }, {
 399                 /* sentinel */
 400         },