ramips: Fix amount of MT7621 pins controlled by spi group

The PINS conntrolled by the SPI bits in the GPIO_MODE register is always
7 and not 8 for nand mode.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 46644

diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
index f08ecb032623e9056919e303d402d041378795ba..7c29fbeedb35e7e4690b9eec098b31b20de9e872 100644 (file)
--- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
+++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
@@ -593,7 +593,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
 +static struct rt2880_pmx_func spi_grp[] = {
 +      FUNC("spi", 0, 34, 7),
-+      FUNC("nand", 2, 34, 8),
++      FUNC("nand", 2, 34, 7),
 +};
 +static struct rt2880_pmx_func sdhci_grp[] = {
 +      FUNC("sdhci", 0, 41, 8),