--- /dev/null
+diff -ruN a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+--- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts 1970-01-01 01:00:00.000000000 +0100
++++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts 2021-05-19 15:37:54.621241935 +0200
+@@ -0,0 +1,152 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for Gateway 7001 AP
++ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Gateway 7001 AP";
++ compatible = "gateway,7001", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /* 32 MB SDRAM */
++ device_type = "memory";
++ reg = <0x00000000 0x2000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ serial0 = &uart1;
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ button-power {
++ wakeup-source;
++ linux,code = <KEY_POWER>;
++ label = "power";
++ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
++ };
++ button-reset {
++ wakeup-source;
++ linux,code = <KEY_ESC>;
++ label = "reset";
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtc@6f {
++ compatible = "xicor,x1205";
++ reg = <0x6f>;
++ };
++ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
++ timeout-ms = <5000>;
++ };
++
++ /* The first 16MB region on the expansion bus */
++ flash@50000000 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /*
++ * 8 MB of Flash in 0x20000 byte blocks
++ * mapped in at 0x50000000
++ */
++ reg = <0x50000000 0x800000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x7e0000 */
++ fis-index-block = <0x3f>;
++ };
++ };
++
++ soc {
++ pci@c0000000 {
++ status = "ok";
++
++ /*
++ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
++ * We have slots (IDSEL) 1, 2 and 3.
++ */
++ interrupt-map =
++ /* IDSEL 1 */
++ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
++ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
++ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
++ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
++ /* IDSEL 2 */
++ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
++ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
++ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
++ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
++ /* IDSEL 3 */
++ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
++ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
++ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
++ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
++ };
++ };
++
++ soc {
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy2>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ };
++ };
++ };
++};
++
++&uart0 {
++ status = "disabled";
++};
+diff -ruN a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+--- a/arch/arm/boot/dts/Makefile 2021-05-17 13:36:56.001312909 +0200
++++ b/arch/arm/boot/dts/Makefile 2021-05-17 13:36:14.141559230 +0200
+@@ -244,6 +244,7 @@
+ integratorap-im-pd1.dtb \
+ integratorcp.dtb
+ dtb-$(CONFIG_ARCH_IXP4XX) += \
++ intel-ixp42x-gateway-7001.dtb \
+ intel-ixp42x-linksys-nslu2.dtb \
+ intel-ixp43x-gateworks-gw2358.dtb
+ dtb-$(CONFIG_ARCH_KEYSTONE) += \
--- /dev/null
+diff -ruN a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts
+--- a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 1970-01-01 01:00:00.000000000 +0100
++++ b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 2021-05-17 17:33:40.427244073 +0200
+@@ -0,0 +1,175 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for ADI Engineering Pronghorn Metro
++ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "ADI Engineering Pronghorn Metro";
++ compatible = "adi,pronghornmetro", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /* 64 MB SDRAM */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ serial0 = &uart1;
++ serial1 = &uart0;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ led-status {
++ label = "nslu2:red:status";
++ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ led-ready {
++ label = "nslu2:green:ready";
++ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++ led-disk-1 {
++ label = "nslu2:green:disk-1";
++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ led-disk-2 {
++ label = "nslu2:green:disk-2";
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ button-power {
++ wakeup-source;
++ linux,code = <KEY_POWER>;
++ label = "power";
++ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
++ };
++ button-reset {
++ wakeup-source;
++ linux,code = <KEY_ESC>;
++ label = "reset";
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtc@6f {
++ compatible = "xicor,x1205";
++ reg = <0x6f>;
++ };
++ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
++ timeout-ms = <5000>;
++ };
++
++ /* The first 16MB region on the expansion bus */
++ flash@50000000 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /*
++ * 8 MB of Flash in 0x20000 byte blocks
++ * mapped in at 0x50000000
++ */
++ reg = <0x50000000 0x800000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x7e0000 */
++ fis-index-block = <0x3f>;
++ };
++ };
++
++ soc {
++ pci@c0000000 {
++ status = "ok";
++
++ /*
++ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
++ * We have slots (IDSEL) 1, 2 and 3.
++ */
++ interrupt-map =
++ /* IDSEL 1 */
++ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
++ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
++ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
++ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
++ /* IDSEL 2 */
++ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
++ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
++ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
++ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
++ /* IDSEL 3 */
++ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
++ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
++ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
++ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
++ };
++ };
++
++ soc {
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy2>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ };
++ };
++
++ };
++};
+diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+--- a/arch/arm/boot/dts/Makefile 2021-05-17 17:34:23.627055651 +0200
++++ b/arch/arm/boot/dts/Makefile 2021-05-17 17:33:51.703194925 +0200
+@@ -244,6 +244,7 @@
+ integratorap-im-pd1.dtb \
+ integratorcp.dtb
+ dtb-$(CONFIG_ARCH_IXP4XX) += \
++ intel-ixp42x-adi-pronghorn-metro.dtb \
+ intel-ixp42x-gateway-7001.dtb \
+ intel-ixp42x-linksys-nslu2.dtb \
+ intel-ixp43x-gateworks-gw2358.dtb
projects / openwrt / staging / wigyori.git / commitdiff