PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
reg = <0x19000000 0x200
0x18070000 0x4>;
pll-data = <0x1a000000 0x13000a44 0x00441099>;
reg = <0x19000000 0x200
0x18070000 0x4>;
pll-data = <0x1a000000 0x13000a44 0x00441099>;
- pll-reg = <0x4 0x10 17>;
+ pll-reg = <0x4 0x14 20>;
pll-handle = <&pll>;
resets = <&rst 9>;
reset-names = "mac";
pll-handle = <&pll>;
resets = <&rst 9>;
reset-names = "mac";