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kernel: bump 5.4 to 5.4.31
[openwrt/staging/ynezz.git] / target / linux / mediatek / patches-5.4 / 0999-hnat.patch
1 --- a/drivers/net/ethernet/mediatek/Kconfig
2 +++ b/drivers/net/ethernet/mediatek/Kconfig
3 @@ -14,4 +14,8 @@ config NET_MEDIATEK_SOC
4 This driver supports the gigabit ethernet MACs in the
5 MediaTek SoC family.
6
7 +config NET_MEDIATEK_OFFLOAD
8 + def_bool NET_MEDIATEK_SOC
9 + depends on NET_MEDIATEK_SOC
10 +
11 endif #NET_VENDOR_MEDIATEK
12 --- a/drivers/net/ethernet/mediatek/Makefile
13 +++ b/drivers/net/ethernet/mediatek/Makefile
14 @@ -5,3 +5,4 @@
15
16 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
17 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
18 +mtk_eth-$(CONFIG_NET_MEDIATEK_OFFLOAD) += mtk_offload.o mtk_debugfs.o
19 --- /dev/null
20 +++ b/drivers/net/ethernet/mediatek/mtk_debugfs.c
21 @@ -0,0 +1,117 @@
22 +/* This program is free software; you can redistribute it and/or modify
23 + * it under the terms of the GNU General Public License as published by
24 + * the Free Software Foundation; version 2 of the License
25 + *
26 + * This program is distributed in the hope that it will be useful,
27 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 + * GNU General Public License for more details.
30 + *
31 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
32 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include "mtk_offload.h"
36 +
37 +static const char *mtk_foe_entry_state_str[] = {
38 + "INVALID",
39 + "UNBIND",
40 + "BIND",
41 + "FIN"
42 +};
43 +
44 +static const char *mtk_foe_packet_type_str[] = {
45 + "IPV4_HNAPT",
46 + "IPV4_HNAT",
47 + "IPV6_1T_ROUTE",
48 + "IPV4_DSLITE",
49 + "IPV6_3T_ROUTE",
50 + "IPV6_5T_ROUTE",
51 + "IPV6_6RD",
52 +};
53 +
54 +#define IPV4_HNAPT 0
55 +#define IPV4_HNAT 1
56 +#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0)
57 +struct mtk_eth *_eth;
58 +#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state])
59 +//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry))
60 +#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry))
61 +#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type])
62 +
63 +static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private)
64 +{
65 + struct mtk_eth *eth = _eth;
66 + struct mtk_foe_entry *entry, *end;
67 + int i = 0;
68 +
69 + entry = eth->foe_table;
70 + end = eth->foe_table + MTK_PPE_ENTRY_CNT;
71 +
72 + while (entry < end) {
73 + if (!entry->bfib1.state) {
74 +
75 + } else if (IS_IPV4_HNAPT(entry)) {
76 + __be32 saddr = htonl(entry->ipv4_hnapt.sip);
77 + __be32 daddr = htonl(entry->ipv4_hnapt.dip);
78 + __be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip);
79 + __be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip);
80 + unsigned char h_dest[ETH_ALEN];
81 + unsigned char h_source[ETH_ALEN];
82 +
83 + *((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi);
84 + *((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo);
85 + *((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
86 + *((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo);
87 + seq_printf(m,
88 + "(%x)0x%05x|state=%s|type=%s|"
89 + "%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|"
90 + "etype=0x%04x|info1=0x%x|info2=0x%x|"
91 + "vlan1=%d|vlan2=%d\n",
92 + i,
93 + ei(entry, end), es(entry), pt(entry),
94 + &saddr, entry->ipv4_hnapt.sport,
95 + &daddr, entry->ipv4_hnapt.dport,
96 + &nsaddr, entry->ipv4_hnapt.new_sport,
97 + &ndaddr, entry->ipv4_hnapt.new_dport, h_source,
98 + h_dest, ntohs(entry->ipv4_hnapt.etype),
99 + entry->ipv4_hnapt.info_blk1,
100 + entry->ipv4_hnapt.info_blk2,
101 + entry->ipv4_hnapt.vlan1,
102 + entry->ipv4_hnapt.vlan2);
103 + } else
104 + seq_printf(m, "0x%05x state=%s\n",
105 + ei(entry, end), es(entry));
106 + entry++;
107 + i++;
108 + }
109 +
110 + return 0;
111 +}
112 +
113 +static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file)
114 +{
115 + return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data);
116 +}
117 +
118 +static const struct file_operations mtk_ppe_debugfs_foe_fops = {
119 + .open = mtk_ppe_debugfs_foe_open,
120 + .read = seq_read,
121 + .llseek = seq_lseek,
122 + .release = single_release,
123 +};
124 +
125 +int mtk_ppe_debugfs_init(struct mtk_eth *eth)
126 +{
127 + struct dentry *root;
128 +
129 + _eth = eth;
130 +
131 + root = debugfs_create_dir("mtk_ppe", NULL);
132 + if (!root)
133 + return -ENOMEM;
134 +
135 + debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops);
136 +
137 + return 0;
138 +}
139 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
140 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
141 @@ -19,6 +19,8 @@
142 #include <linux/interrupt.h>
143 #include <linux/pinctrl/devinfo.h>
144 #include <linux/phylink.h>
145 +#include <linux/netfilter.h>
146 +#include <net/netfilter/nf_flow_table.h>
147
148 #include "mtk_eth_soc.h"
149
150 @@ -65,6 +67,18 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
151 return __raw_readl(eth->base + reg);
152 }
153
154 +void mtk_m32(struct mtk_eth *eth, u32 clear, u32 set, unsigned reg)
155 +{
156 + u32 val;
157 +
158 + spin_lock(&eth->page_lock);
159 + val = __raw_readl(eth->base + reg);
160 + val &= ~clear;
161 + val |= set;
162 + __raw_writel(val, eth->base + reg);
163 + spin_unlock(&eth->page_lock);
164 +}
165 +
166 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
167 {
168 unsigned long t_start = jiffies;
169 @@ -1276,8 +1290,16 @@ static int mtk_poll_rx(struct napi_struc
170 (trxd.rxd2 & RX_DMA_VTAG))
171 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
172 RX_DMA_VID(trxd.rxd3));
173 - skb_record_rx_queue(skb, 0);
174 - napi_gro_receive(napi, skb);
175 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
176 + if (mtk_offload_check_rx(eth, skb, trxd.rxd4) == 0) {
177 +#endif
178 + skb_record_rx_queue(skb, 0);
179 + napi_gro_receive(napi, skb);
180 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
181 + } else {
182 + dev_kfree_skb(skb);
183 + }
184 +#endif
185
186 ring->data[idx] = new_data;
187 rxd->rxd1 = (unsigned int)dma_addr;
188 @@ -2194,6 +2216,9 @@ static int mtk_open(struct net_device *d
189 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
190 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
191 refcount_set(&eth->dma_refcnt, 1);
192 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
193 + mtk_ppe_probe(eth);
194 +#endif
195 }
196 else
197 refcount_inc(&eth->dma_refcnt);
198 @@ -2252,6 +2277,9 @@ static int mtk_stop(struct net_device *d
199
200 mtk_dma_free(eth);
201
202 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
203 + mtk_ppe_remove(eth);
204 +#endif
205 return 0;
206 }
207
208 @@ -2711,6 +2739,27 @@ static int mtk_set_rxnfc(struct net_devi
209 return ret;
210 }
211
212 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
213 +static int
214 +mtk_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
215 + struct flow_offload_hw_path *src,
216 + struct flow_offload_hw_path *dest)
217 +{
218 + struct mtk_mac *mac = netdev_priv(src->dev);
219 + struct mtk_eth *eth = mac->hw;
220 +
221 + if (!eth->soc->offload_version)
222 + return -EINVAL;
223 +
224 + if (src->dev->base_addr != dest->dev->base_addr)
225 + return -EINVAL;
226 +
227 + mac = netdev_priv(src->dev);
228 +
229 + return mtk_flow_offload_add(eth, type, flow, src, dest);
230 +}
231 +#endif
232 +
233 static const struct ethtool_ops mtk_ethtool_ops = {
234 .get_link_ksettings = mtk_get_link_ksettings,
235 .set_link_ksettings = mtk_set_link_ksettings,
236 @@ -2742,6 +2791,9 @@ static const struct net_device_ops mtk_n
237 #ifdef CONFIG_NET_POLL_CONTROLLER
238 .ndo_poll_controller = mtk_poll_controller,
239 #endif
240 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
241 + .ndo_flow_offload = mtk_flow_offload,
242 +#endif
243 };
244
245 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
246 @@ -3075,6 +3127,7 @@ static const struct mtk_soc_data mt7622_
247 .hw_features = MTK_HW_FEATURES,
248 .required_clks = MT7622_CLKS_BITMAP,
249 .required_pctl = false,
250 + .offload_version = MTK_OFFLOAD_V2,
251 };
252
253 static const struct mtk_soc_data mt7623_data = {
254 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
255 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
256 @@ -771,6 +771,13 @@ enum mkt_eth_capabilities {
257 MTK_MUX_U3_GMAC2_TO_QPHY | \
258 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
259
260 +enum mtk_flow_offload_version {
261 + MTK_OFFLOAD_NONE = 0,
262 + MTK_OFFLOAD_V1,
263 + MTK_OFFLOAD_V2,
264 + MTK_OFFLOAD_V3,
265 +};
266 +
267 /* struct mtk_eth_data - This is the structure holding all differences
268 * among various plaforms
269 * @ana_rgc3: The offset for register ANA_RGC3 related to
270 @@ -788,6 +795,7 @@ struct mtk_soc_data {
271 u32 required_clks;
272 bool required_pctl;
273 netdev_features_t hw_features;
274 + enum mtk_flow_offload_version offload_version;
275 };
276
277 /* currently no SoC has more than 2 macs */
278 @@ -813,6 +821,23 @@ struct mtk_sgmii {
279 u32 ana_rgc3;
280 };
281
282 +
283 +struct mib_entry {
284 + u32 byt_cnt_l;
285 + u16 byt_cnt_h;
286 + u32 pkt_cnt_l;
287 + u8 pkt_cnt_h;
288 + u8 resv0;
289 + u32 resv1;
290 +} __packed __aligned(4);
291 +
292 +struct hnat_accounting {
293 + u64 bytes;
294 + u64 packets;
295 +};
296 +
297 +
298 +
299 /* struct mtk_eth - This is the main datasructure for holding the state
300 * of the driver
301 * @dev: The device pointer
302 @@ -886,6 +911,16 @@ struct mtk_eth {
303 u32 tx_int_status_reg;
304 u32 rx_dma_l4_valid;
305 int ip_align;
306 +
307 + struct reset_control *rst_ppe;
308 + struct mtk_foe_entry *foe_table;
309 + dma_addr_t foe_table_phys;
310 + struct flow_offload __rcu **foe_flow_table;
311 +
312 + struct mib_entry *foe_mib_cpu;
313 + dma_addr_t foe_mib_dev;
314 + struct hnat_accounting *acct;
315 + bool per_flow_accounting;
316 };
317
318 /* struct mtk_mac - the structure that holds the info about the MACs of the
319 @@ -918,6 +953,7 @@ void mtk_stats_update_mac(struct mtk_mac
320
321 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
322 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
323 +void mtk_m32(struct mtk_eth *eth, u32 clear, u32 set, unsigned reg);
324
325 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
326 u32 ana_rgc3);
327 @@ -930,4 +966,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
328 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
329 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
330
331 +int mtk_ppe_probe(struct mtk_eth *eth);
332 +void mtk_ppe_remove(struct mtk_eth *eth);
333 +int mtk_flow_offload_add(struct mtk_eth *eth,
334 + enum flow_offload_type type,
335 + struct flow_offload *flow,
336 + struct flow_offload_hw_path *src,
337 + struct flow_offload_hw_path *dest);
338 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4);
339 +
340 #endif /* MTK_ETH_H */
341 --- /dev/null
342 +++ b/drivers/net/ethernet/mediatek/mtk_offload.c
343 @@ -0,0 +1,593 @@
344 +/* This program is free software; you can redistribute it and/or modify
345 + * it under the terms of the GNU General Public License as published by
346 + * the Free Software Foundation; version 2 of the License
347 + *
348 + * This program is distributed in the hope that it will be useful,
349 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
350 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
351 + * GNU General Public License for more details.
352 + *
353 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
354 + */
355 +
356 +#include "mtk_offload.h"
357 +
358 +#define INVALID 0
359 +#define UNBIND 1
360 +#define BIND 2
361 +#define FIN 3
362 +
363 +#define IPV4_HNAPT 0
364 +#define IPV4_HNAT 1
365 +
366 +static u32
367 +mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
368 +{
369 + u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
370 + u32 src = ntohl(tuple->dst_v4.s_addr);
371 + u32 dst = ntohl(tuple->src_v4.s_addr);
372 + u32 hash = (ports & src) | ((~ports) & dst);
373 + u32 hash_23_0 = hash & 0xffffff;
374 + u32 hash_31_24 = hash & 0xff000000;
375 +
376 + hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
377 + hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
378 + hash &= 0x7ff;
379 + hash *= 2;;
380 +
381 + return hash;
382 +}
383 +
384 +static int
385 +mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
386 + struct flow_offload_tuple *tuple,
387 + struct flow_offload_tuple *dest_tuple,
388 + struct flow_offload_hw_path *src,
389 + struct flow_offload_hw_path *dest)
390 +{
391 + int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
392 +
393 + if (tuple->l4proto == IPPROTO_UDP)
394 + entry->ipv4_hnapt.bfib1.udp = 1;
395 +
396 + entry->ipv4_hnapt.etype = htons(ETH_P_IP);
397 + entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
398 + entry->ipv4_hnapt.iblk2.fqos = 0;
399 + entry->ipv4_hnapt.bfib1.ttl = 1;
400 + entry->ipv4_hnapt.bfib1.cah = 1;
401 + entry->ipv4_hnapt.bfib1.ka = 1;
402 + entry->ipv4_hnapt.iblk2.mcast = is_mcast;
403 + entry->ipv4_hnapt.iblk2.dscp = 0;
404 + entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
405 + entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
406 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
407 + entry->ipv4_hnapt.iblk2.qid = 1;
408 + entry->ipv4_hnapt.iblk2.fqos = 1;
409 +#endif
410 +#ifdef CONFIG_RALINK
411 + entry->ipv4_hnapt.iblk2.dp = 1;
412 + if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
413 + entry->ipv4_hnapt.iblk2.qid += 8;
414 +#else
415 + entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
416 +#endif
417 +
418 + entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
419 + entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
420 + entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
421 + entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
422 +
423 + entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
424 + entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
425 + entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
426 + entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
427 +
428 + entry->bfib1.state = BIND;
429 +
430 + if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
431 + entry->bfib1.psn = 1;
432 + entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
433 + entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
434 + }
435 +
436 + if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
437 + entry->ipv4_hnapt.vlan1 = dest->vlan_id;
438 + entry->bfib1.vlan_layer = 1;
439 +
440 + switch (dest->vlan_proto) {
441 + case htons(ETH_P_8021Q):
442 + entry->ipv4_hnapt.bfib1.vpm = 1;
443 + break;
444 + case htons(ETH_P_8021AD):
445 + entry->ipv4_hnapt.bfib1.vpm = 2;
446 + break;
447 + default:
448 + return -EINVAL;
449 + }
450 + }
451 +
452 + return 0;
453 +}
454 +
455 +static void
456 +mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
457 +{
458 + entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
459 + entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
460 + entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
461 + entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
462 +}
463 +
464 +static int
465 +mtk_check_entry_available(struct mtk_eth *eth, u32 hash)
466 +{
467 + struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash];
468 +
469 + return (entry.bfib1.state == BIND)? 0:1;
470 +}
471 +
472 +static void
473 +mtk_foe_write(struct mtk_eth *eth, u32 hash,
474 + struct mtk_foe_entry *entry)
475 +{
476 + struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
477 +
478 + memcpy(&table[hash], entry, sizeof(*entry));
479 +}
480 +
481 +int mtk_flow_offload_add(struct mtk_eth *eth,
482 + enum flow_offload_type type,
483 + struct flow_offload *flow,
484 + struct flow_offload_hw_path *src,
485 + struct flow_offload_hw_path *dest)
486 +{
487 + struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
488 + struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
489 + u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
490 + u32 ohash, rhash;
491 + struct mtk_foe_entry orig = {
492 + .bfib1.time_stamp = time_stamp,
493 + .bfib1.psn = 0,
494 + };
495 + struct mtk_foe_entry reply = {
496 + .bfib1.time_stamp = time_stamp,
497 + .bfib1.psn = 0,
498 + };
499 +
500 + if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
501 + return -EINVAL;
502 +
503 + if (type == FLOW_OFFLOAD_DEL) {
504 + flow = NULL;
505 + synchronize_rcu();
506 + return 0;
507 + }
508 +
509 + switch (otuple->l3proto) {
510 + case AF_INET:
511 + if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
512 + mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
513 + return -EINVAL;
514 +
515 + ohash = mtk_flow_hash_v4(otuple);
516 + rhash = mtk_flow_hash_v4(rtuple);
517 + break;
518 +
519 + case AF_INET6:
520 + return -EINVAL;
521 +
522 + default:
523 + return -EINVAL;
524 + }
525 +
526 + /* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */
527 + if (!mtk_check_entry_available(eth, ohash)){
528 + if (!mtk_check_entry_available(eth, ohash + 1))
529 + return -EINVAL;
530 + ohash += 1;
531 + }
532 + if (!mtk_check_entry_available(eth, rhash)){
533 + if (!mtk_check_entry_available(eth, rhash + 1))
534 + return -EINVAL;
535 + rhash += 1;
536 + }
537 +
538 + mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
539 + mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
540 + mtk_foe_write(eth, ohash, &orig);
541 + mtk_foe_write(eth, rhash, &reply);
542 + rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
543 + rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
544 +
545 + return 0;
546 +}
547 +
548 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
549 +
550 +#define QDMA_TX_SCH_TX 0x1a14
551 +
552 +static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
553 +{
554 + int exp = 0, shift = 0;
555 + u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
556 + u32 val = 0;
557 +
558 + if (rate)
559 + val = BIT(11);
560 +
561 + while (rate > 127) {
562 + rate /= 10;
563 + exp++;
564 + }
565 +
566 + val |= (rate & 0x7f) << 4;
567 + val |= exp & 0xf;
568 + if (id)
569 + shift = 16;
570 + reg &= ~(0xffff << shift);
571 + reg |= val << shift;
572 + mtk_w32(eth, val, QDMA_TX_SCH_TX);
573 +}
574 +
575 +#define QTX_CFG(x) (0x1800 + (x * 0x10))
576 +#define QTX_SCH(x) (0x1804 + (x * 0x10))
577 +
578 +static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
579 +{
580 + int max_exp = 0, min_exp = 0;
581 + u32 reg;
582 +
583 + if (id >= 16)
584 + return;
585 +
586 + reg = mtk_r32(eth, QTX_SCH(id));
587 + reg &= 0x70000000;
588 +
589 + if (sched)
590 + reg |= BIT(31);
591 +
592 + if (min_rate)
593 + reg |= BIT(27);
594 +
595 + if (max_rate)
596 + reg |= BIT(11);
597 +
598 + while (max_rate > 127) {
599 + max_rate /= 10;
600 + max_exp++;
601 + }
602 +
603 + while (min_rate > 127) {
604 + min_rate /= 10;
605 + min_exp++;
606 + }
607 +
608 + reg |= (min_rate & 0x7f) << 20;
609 + reg |= (min_exp & 0xf) << 16;
610 + reg |= (weight & 0xf) << 12;
611 + reg |= (max_rate & 0x7f) << 4;
612 + reg |= max_exp & 0xf;
613 + mtk_w32(eth, reg, QTX_SCH(id));
614 +
615 + resv &= 0xff;
616 + reg = mtk_r32(eth, QTX_CFG(id));
617 + reg &= 0xffff0000;
618 + reg |= (resv << 8) | resv;
619 + mtk_w32(eth, reg, QTX_CFG(id));
620 +}
621 +#endif
622 +
623 +static int mtk_init_foe_table(struct mtk_eth *eth)
624 +{
625 + if (eth->foe_table)
626 + return 0;
627 +
628 + eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
629 + sizeof(*eth->foe_flow_table),
630 + GFP_KERNEL);
631 + if (!eth->foe_flow_table)
632 + return -EINVAL;
633 +
634 + /* map the FOE table */
635 + eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
636 + &eth->foe_table_phys, GFP_KERNEL);
637 + if (!eth->foe_table) {
638 + dev_err(eth->dev, "failed to allocate foe table\n");
639 + kfree(eth->foe_flow_table);
640 + return -ENOMEM;
641 + }
642 +
643 +
644 + return 0;
645 +}
646 +
647 +static int mtk_ppe_start(struct mtk_eth *eth)
648 +{
649 + u32 foe_mib_tb_sz;
650 + u32 foe_etry_num = MTK_PPE_ENTRY_CNT;
651 +
652 + int ret;
653 +
654 + ret = mtk_init_foe_table(eth);
655 + if (ret)
656 + return ret;
657 +
658 + /* tell the PPE about the tables base address */
659 + mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
660 +
661 + /* flush the table */
662 + memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
663 +
664 + eth->per_flow_accounting = false; //true;
665 +
666 + if (eth->per_flow_accounting) {
667 + foe_mib_tb_sz = foe_etry_num * sizeof(struct mib_entry);
668 + eth->foe_mib_cpu = dma_alloc_coherent(eth->dev, foe_mib_tb_sz,
669 + &eth->foe_mib_dev, GFP_KERNEL);
670 + if (!eth->foe_mib_cpu)
671 + return -1;
672 + mtk_w32(eth, eth->foe_mib_dev, MTK_REG_PPE_MIB_TB_BASE);
673 + memset(eth->foe_mib_cpu, 0, foe_mib_tb_sz);
674 +
675 + eth->acct =
676 + kzalloc(foe_etry_num * sizeof(struct hnat_accounting),
677 + GFP_KERNEL);
678 + if (!eth->acct)
679 + return -1;
680 + }
681 +
682 + /* setup hashing */
683 + mtk_m32(eth,
684 + MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
685 + MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
686 + MTK_REG_PPE_TB_CFG);
687 +
688 + /* set the default hashing seed */
689 + mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
690 +
691 + /* each foe entry is 80bytes and is setup by cpu forwarding*/
692 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
693 + MTK_PPE_TB_CFG_SMA_MASK,
694 + MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
695 + MTK_REG_PPE_TB_CFG);
696 +
697 + /* set ip proto */
698 + //writel(0xFFFFFFFF, host->ppe_base + PPE_IP_PROT_CHK);
699 + mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
700 +
701 + /* setup caching */
702 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 1);
703 + mtk_m32(eth, 1, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
704 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 0);
705 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
706 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_EN, 1);
707 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
708 + MTK_REG_PPE_CAH_CTRL);
709 +
710 + /* enable FOE */
711 + /* cr_set_bits(host->ppe_base + PPE_FLOW_CFG,
712 + BIT_UDP_IP4F_NAT_EN | BIT_IPV4_NAT_EN | BIT_IPV4_NAPT_EN |
713 + BIT_IPV4_NAT_FRAG_EN | BIT_IPV4_HASH_GREK |
714 + BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN |
715 + BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); */
716 + mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
717 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
718 + MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
719 + MTK_REG_PPE_FLOW_CFG);
720 +
721 + mtk_w32(eth, 0x000a7780, MTK_REG_PPE_FLOW_CFG);
722 +
723 + /* setup flow entry un/bind aging */
724 + // cr_set_field(host->ppe_base + PPE_TB_CFG, NTU_AGE, 1);
725 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UNBD_AGE, 1);
726 + // cr_set_field(host->ppe_base + PPE_TB_CFG, TCP_AGE, 1);
727 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UDP_AGE, 1);
728 + // cr_set_field(host->ppe_base + PPE_TB_CFG, FIN_AGE, 1);
729 + mtk_m32(eth, 0,
730 + MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
731 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
732 + MTK_PPE_TB_CFG_TCP_AGE,
733 + MTK_REG_PPE_TB_CFG);
734 +
735 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_MNP, 1000);
736 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_DLTA, 3);
737 + mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
738 + MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
739 + MTK_REG_PPE_UNB_AGE);
740 +
741 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, UDP_DLTA, 12);
742 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, NTU_DLTA, 1);
743 + mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
744 + MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
745 + MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
746 + MTK_REG_PPE_BND_AGE0);
747 + mtk_w32(eth, 0x0001000c, MTK_REG_PPE_BND_AGE0);
748 +
749 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, FIN_DLTA, 1);
750 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, TCP_DLTA, 7);
751 + mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
752 + MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
753 + MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
754 + MTK_REG_PPE_BND_AGE1);
755 + mtk_w32(eth, 0x00010007, MTK_REG_PPE_BND_AGE1);
756 +
757 + /* setup flow entry keep alive */
758 + // cr_set_field(host->ppe_base + PPE_TB_CFG, SCAN_MODE, 2);
759 + // cr_set_field(host->ppe_base + PPE_TB_CFG, KA_CFG, 3);
760 + mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK | MTK_PPE_TB_CFG_SCAN_MODE_MASK,
761 + MTK_PPE_TB_CFG_KA | MTK_PPE_TB_CFG_SCAN_MODE,
762 + MTK_REG_PPE_TB_CFG);
763 + // cr_set_field(host->ppe_base + PPE_KA, KA_T, 1);
764 + // cr_set_field(host->ppe_base + PPE_KA, TCP_KA, 1);
765 + // cr_set_field(host->ppe_base + PPE_KA, UDP_KA, 1);
766 + mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
767 +
768 + /* setup flow entry rate limit */
769 + mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
770 + mtk_w32(eth, 0x2000000 | MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
771 + /* 30 packets per second */
772 + mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 0x1e, MTK_REG_PPE_BNDR);
773 +
774 + /* enable the PPE */
775 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
776 +
777 + /* set the default forwarding port to PDMA */
778 + mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
779 +
780 + /* disallow packets with TTL=0 */
781 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG);
782 +
783 + /*enable ppe mib counter*/
784 + if (eth->per_flow_accounting) {
785 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CFG);
786 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CAH_CTRL);
787 + }
788 +
789 + /* send all traffic from gmac to the ppe */
790 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
791 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
792 +
793 + mtk_w32(eth, 0x00027fb4, MTK_REG_PPE_TB_CFG);
794 +
795 + dev_info(eth->dev, "PPE started\n");
796 +
797 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
798 + mtk_ppe_scheduler(eth, 0, 500000);
799 + mtk_ppe_scheduler(eth, 1, 500000);
800 + mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
801 + mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
802 + mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
803 + mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
804 +#endif
805 +
806 + return 0;
807 +}
808 +
809 +static int mtk_ppe_busy_wait(struct mtk_eth *eth)
810 +{
811 + unsigned long t_start = jiffies;
812 + u32 r = 0;
813 +
814 + while (1) {
815 + r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
816 + if (!(r & MTK_PPE_GLO_CFG_BUSY))
817 + return 0;
818 + if (time_after(jiffies, t_start + HZ))
819 + break;
820 + usleep_range(10, 20);
821 + }
822 +
823 + dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
824 + reset_control_reset(eth->rst_ppe);
825 +
826 + return -ETIMEDOUT;
827 +}
828 +
829 +static int mtk_ppe_stop(struct mtk_eth *eth)
830 +{
831 + u32 r1 = 0, r2 = 0;
832 + int i;
833 +
834 + /* discard all traffic while we disable the PPE */
835 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
836 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
837 +
838 + if (mtk_ppe_busy_wait(eth))
839 + return -ETIMEDOUT;
840 +
841 + /* invalidate all flow table entries */
842 + for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
843 + eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
844 +
845 + /* disable caching */
846 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
847 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
848 + MTK_REG_PPE_CAH_CTRL);
849 +
850 + /* flush cache has to be ahead of hnat diable --*/
851 + mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
852 +
853 + /* disable FOE */
854 + mtk_m32(eth,
855 + MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
856 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
857 + MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
858 + 0, MTK_REG_PPE_FLOW_CFG);
859 +
860 + /* disable FOE aging */
861 + mtk_m32(eth, 0,
862 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
863 + MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
864 + MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
865 +
866 + r1 = mtk_r32(eth, 0x100);
867 + r2 = mtk_r32(eth, 0x10c);
868 +
869 + dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
870 +
871 + if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
872 + ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
873 + dev_info(eth->dev, "reset pse\n");
874 + mtk_w32(eth, 0x1, 0x4);
875 + }
876 +
877 + /* set the foe entry base address to 0 */
878 + mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
879 +
880 + if (mtk_ppe_busy_wait(eth))
881 + return -ETIMEDOUT;
882 +
883 + /* send all traffic back to the DMA engine */
884 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
885 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
886 + return 0;
887 +}
888 +
889 +static void mtk_offload_keepalive(struct mtk_eth *eth, unsigned int hash)
890 +{
891 + struct flow_offload *flow;
892 +
893 + rcu_read_lock();
894 + flow = rcu_dereference(eth->foe_flow_table[hash]);
895 + if (flow)
896 + flow->timeout = jiffies + 30 * HZ;
897 + rcu_read_unlock();
898 +}
899 +
900 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4)
901 +{
902 + unsigned int hash;
903 +
904 + switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
905 + case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
906 + case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
907 + case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
908 + hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
909 + mtk_offload_keepalive(eth, hash);
910 + return -1;
911 + case MTK_CPU_REASON_PACKET_SAMPLING:
912 + return -1;
913 + default:
914 + return 0;
915 + }
916 +}
917 +
918 +int mtk_ppe_probe(struct mtk_eth *eth)
919 +{
920 + int err;
921 +
922 + err = mtk_ppe_start(eth);
923 + if (err)
924 + return err;
925 +
926 + err = mtk_ppe_debugfs_init(eth);
927 + if (err)
928 + return err;
929 +
930 + return 0;
931 +}
932 +
933 +void mtk_ppe_remove(struct mtk_eth *eth)
934 +{
935 + mtk_ppe_stop(eth);
936 +}
937 --- /dev/null
938 +++ b/drivers/net/ethernet/mediatek/mtk_offload.h
939 @@ -0,0 +1,298 @@
940 +/* This program is free software; you can redistribute it and/or modify
941 + * it under the terms of the GNU General Public License as published by
942 + * the Free Software Foundation; version 2 of the License
943 + *
944 + * This program is distributed in the hope that it will be useful,
945 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
946 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
947 + * GNU General Public License for more details.
948 + *
949 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
950 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
951 + */
952 +
953 +#include <linux/dma-mapping.h>
954 +#include <linux/delay.h>
955 +#include <linux/if.h>
956 +#include <linux/io.h>
957 +#include <linux/module.h>
958 +#include <linux/of_device.h>
959 +#include <linux/platform_device.h>
960 +#include <linux/reset.h>
961 +#include <linux/netfilter.h>
962 +#include <linux/netdevice.h>
963 +#include <net/netfilter/nf_flow_table.h>
964 +#include <linux/debugfs.h>
965 +#include <linux/etherdevice.h>
966 +#include <linux/bitfield.h>
967 +
968 +#include "mtk_eth_soc.h"
969 +
970 +#ifdef CONFIG_RALINK
971 +/* ramips compat */
972 +#define mtk_eth fe_priv
973 +#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
974 +#define mtk_m32 fe_m32
975 +
976 +static inline u32
977 +mtk_r32(struct mtk_eth *eth, u32 reg)
978 +{
979 + return fe_r32(reg);
980 +}
981 +
982 +static inline void
983 +mtk_w32(struct mtk_eth *eth, u32 val, u32 reg)
984 +{
985 + fe_w32(val, reg);
986 +}
987 +#endif
988 +
989 +#define MTK_REG_PPE_GLO_CFG 0xe00
990 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
991 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
992 +#define MTK_PPE_GLO_CFG_EN BIT(0)
993 +
994 +#define MTK_REG_PPE_FLOW_CFG 0xe04
995 +#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
996 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
997 +#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
998 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
999 +#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
1000 +#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
1001 +
1002 +#define MTK_REG_PPE_IP_PROT_CHK 0xe08
1003 +
1004 +#define MTK_REG_PPE_TB_BASE 0xe20
1005 +
1006 +#define MTK_REG_PPE_BNDR 0xe28
1007 +#define MTK_PPE_BNDR_RATE_MASK 0xffff
1008 +
1009 +#define MTK_REG_PPE_BIND_LMT_0 0xe2C
1010 +
1011 +#define MTK_REG_PPE_BIND_LMT_1 0xe30
1012 +#define MTK_PPE_NTU_KA BIT(16)
1013 +
1014 +#define MTK_REG_PPE_KA 0xe34
1015 +#define MTK_PPE_KA_T BIT(0)
1016 +#define MTK_PPE_KA_TCP BIT(16)
1017 +#define MTK_PPE_KA_UDP BIT(24)
1018 +
1019 +#define MTK_REG_PPE_UNB_AGE 0xe38
1020 +#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
1021 +#define MTK_PPE_UNB_AGE_MNP (1000 << 16)
1022 +#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
1023 +#define MTK_PPE_UNB_AGE_DLTA 3
1024 +
1025 +#define MTK_REG_PPE_BND_AGE0 0xe3c
1026 +#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
1027 +#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
1028 +#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
1029 +#define MTK_PPE_BND_AGE0_UDP_DLTA 5
1030 +
1031 +#define MTK_REG_PPE_BND_AGE1 0xe40
1032 +#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
1033 +#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
1034 +#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
1035 +#define MTK_PPE_BND_AGE1_TCP_DLTA 5
1036 +
1037 +#define MTK_REG_PPE_DFT_CPORT 0xe48
1038 +
1039 +#define MTK_REG_PPE_TB_CFG 0xe1c
1040 +#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
1041 +#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
1042 +#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
1043 +#define MTK_PPE_TB_CFG_KA (3 << 12)
1044 +#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
1045 +#define MTK_PPE_TB_CFG_SCAN_MODE (2 << 16)
1046 +#define MTK_PPE_TB_CFG_SCAN_MODE_MASK (0x3 << 16)
1047 +#define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
1048 +#define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
1049 +#define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
1050 +#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
1051 +#define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
1052 +#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
1053 +#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
1054 +#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
1055 +#define MTK_PPE_TB_CFG_ENTRY_SZ_80B 1
1056 +#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
1057 +#define MTK_PPE_TB_CFG_TBL_SZ_4K 4
1058 +#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
1059 +
1060 +#define MTK_REG_PPE_HASH_SEED 0xe44
1061 +#define MTK_PPE_HASH_SEED 0x12345678
1062 +
1063 +
1064 +#define MTK_REG_PPE_CAH_CTRL 0xf20
1065 +#define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
1066 +#define MTK_PPE_CAH_CTRL_EN BIT(0)
1067 +
1068 +#define MTK_REG_PPE_MIB_CFG 0xf34
1069 +#define MTK_REG_PPE_MIB_TB_BASE 0xf38
1070 +#define MTK_REG_PPE_MIB_CAH_CTRL 0Xf50
1071 +
1072 +
1073 +struct mtk_foe_unbind_info_blk {
1074 + u32 time_stamp:8;
1075 + u32 pcnt:16; /* packet count */
1076 + u32 preb:1;
1077 + u32 pkt_type:3;
1078 + u32 state:2;
1079 + u32 udp:1;
1080 + u32 sta:1; /* static entry */
1081 +} __attribute__ ((packed));
1082 +
1083 +struct mtk_foe_bind_info_blk {
1084 + u32 time_stamp:15;
1085 + u32 ka:1; /* keep alive */
1086 + u32 vlan_layer:3;
1087 + u32 psn:1; /* egress packet has PPPoE session */
1088 +#ifdef CONFIG_RALINK
1089 + u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */
1090 +#else
1091 + u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */
1092 + u32 ps:1; /* packet sampling */
1093 +#endif
1094 + u32 cah:1; /* cacheable flag */
1095 + u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */
1096 + u32 ttl:1;
1097 + u32 pkt_type:3;
1098 + u32 state:2;
1099 + u32 udp:1;
1100 + u32 sta:1; /* static entry */
1101 +} __attribute__ ((packed));
1102 +
1103 +struct mtk_foe_info_blk2 {
1104 + u32 qid:4; /* QID in Qos Port */
1105 + u32 fqos:1; /* force to PSE QoS port */
1106 + u32 dp:3; /* force to PSE port x
1107 + 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
1108 + u32 mcast:1; /* multicast this packet to CPU */
1109 + u32 pcpl:1; /* OSBN */
1110 + u32 mlen:1; /* 0:post 1:pre packet length in meter */
1111 + u32 alen:1; /* 0:post 1:pre packet length in accounting */
1112 + u32 port_mg:6; /* port meter group */
1113 + u32 port_ag:6; /* port account group */
1114 + u32 dscp:8; /* DSCP value */
1115 +} __attribute__ ((packed));
1116 +
1117 +/* info blk2 for WHNAT */
1118 +struct hnat_info_blk2_whnat {
1119 + u32 qid : 4; /* QID[3:0] in Qos Port */
1120 + u32 fqos : 1; /* force to PSE QoS port */
1121 + u32 dp : 3; /* force to PSE port x
1122 + * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
1123 + */
1124 + u32 mcast : 1; /* multicast this packet to CPU */
1125 + u32 pcpl : 1; /* OSBN */
1126 + u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
1127 + u32 alen : 1; /* 0:post 1:pre packet length in accounting */
1128 + u32 qid2 : 2; /* QID[5:4] in Qos Port */
1129 + u32 resv : 2;
1130 + u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
1131 + u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
1132 + u32 port_ag : 6; /* port account group */
1133 + u32 dscp : 8; /* DSCP value */
1134 +} __attribute__ ((packed));
1135 +
1136 +struct hnat_winfo {
1137 + u32 bssid : 6; /* WiFi Bssidx */
1138 + u32 wcid : 8; /* WiFi wtable Idx */
1139 + u32 rxid : 2; /* WiFi Ring idx */
1140 +} __attribute__ ((packed));
1141 +
1142 +struct mtk_foe_ipv4_hnapt {
1143 + union {
1144 + struct mtk_foe_bind_info_blk bfib1;
1145 + struct mtk_foe_unbind_info_blk udib1;
1146 + u32 info_blk1;
1147 + };
1148 + u32 sip;
1149 + u32 dip;
1150 + u16 dport;
1151 + u16 sport;
1152 + union {
1153 + struct mtk_foe_info_blk2 iblk2;
1154 + struct hnat_info_blk2_whnat iblk2w;
1155 + u32 info_blk2;
1156 + };
1157 + u32 new_sip;
1158 + u32 new_dip;
1159 + u16 new_dport;
1160 + u16 new_sport;
1161 + u32 resv1;
1162 + u32 resv2;
1163 + u32 resv3:26;
1164 + u32 act_dp:6; /* UDF */
1165 + u16 vlan1;
1166 + u16 etype;
1167 + u32 dmac_hi;
1168 + union {
1169 + struct hnat_winfo winfo;
1170 + u16 vlan2;
1171 + };
1172 + u16 dmac_lo;
1173 + u32 smac_hi;
1174 + u16 pppoe_id;
1175 + u16 smac_lo;
1176 +} __attribute__ ((packed));
1177 +
1178 +struct mtk_foe_entry {
1179 + union {
1180 + struct mtk_foe_unbind_info_blk udib1;
1181 + struct mtk_foe_bind_info_blk bfib1;
1182 + struct mtk_foe_ipv4_hnapt ipv4_hnapt;
1183 + };
1184 +};
1185 +
1186 +enum mtk_foe_entry_state {
1187 + FOE_STATE_INVALID = 0,
1188 + FOE_STATE_UNBIND = 1,
1189 + FOE_STATE_BIND = 2,
1190 + FOE_STATE_FIN = 3
1191 +};
1192 +
1193 +
1194 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
1195 +#define MTK_RXD4_CPU_REASON GENMASK(18, 14)
1196 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
1197 +#define MTK_RXD4_ALG GENMASK(31, 22)
1198 +
1199 +enum mtk_foe_cpu_reason {
1200 + MTK_CPU_REASON_TTL_EXCEEDED = 0x02,
1201 + MTK_CPU_REASON_OPTION_HEADER = 0x03,
1202 + MTK_CPU_REASON_NO_FLOW = 0x07,
1203 + MTK_CPU_REASON_IPV4_FRAG = 0x08,
1204 + MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
1205 + MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
1206 + MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
1207 + MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
1208 + MTK_CPU_REASON_UN_HIT = 0x0d,
1209 + MTK_CPU_REASON_HIT_UNBIND = 0x0e,
1210 + MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
1211 + MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
1212 + MTK_CPU_REASON_HIT_TTL_1 = 0x11,
1213 + MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
1214 + MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
1215 + MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
1216 + MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
1217 + MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
1218 + MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
1219 + MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18,
1220 + MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
1221 + MTK_CPU_REASON_HIT_PRE_BIND = 0x1a,
1222 + MTK_CPU_REASON_PACKET_SAMPLING = 0x1b,
1223 + MTK_CPU_REASON_EXCEED_MTU = 0x1c,
1224 + MTK_CPU_REASON_PPE_BYPASS = 0x1e,
1225 + MTK_CPU_REASON_INVALID = 0x1f,
1226 +};
1227 +
1228 +
1229 +/* our table size is 4K */
1230 +#define MTK_PPE_ENTRY_CNT 0x4000
1231 +#define MTK_PPE_TBL_SZ \
1232 + (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
1233 +
1234 +int mtk_ppe_debugfs_init(struct mtk_eth *eth);
1235 +
1236 +
1237 +
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