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[openwrt/staging/yousong.git] / package / boot / uboot-lantiq / patches / 0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch
1 From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Sat, 2 Mar 2013 23:34:00 +0100
4 Subject: MIPS: add board support for AVM FritzBox 3370
5
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7
8 --- /dev/null
9 +++ b/board/avm/fb3370/Makefile
10 @@ -0,0 +1,28 @@
11 +#
12 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
13 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
14 +#
15 +# SPDX-License-Identifier: GPL-2.0+
16 +#
17 +
18 +include $(TOPDIR)/config.mk
19 +
20 +LIB = $(obj)lib$(BOARD).o
21 +
22 +COBJS = $(BOARD).o
23 +
24 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
25 +OBJS := $(addprefix $(obj),$(COBJS))
26 +SOBJS := $(addprefix $(obj),$(SOBJS))
27 +
28 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
29 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
30 +
31 +#########################################################################
32 +
33 +# defines $(obj).depend target
34 +include $(SRCTREE)/rules.mk
35 +
36 +sinclude $(obj).depend
37 +
38 +#########################################################################
39 --- /dev/null
40 +++ b/board/avm/fb3370/config.mk
41 @@ -0,0 +1,7 @@
42 +#
43 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
44 +#
45 +# SPDX-License-Identifier: GPL-2.0+
46 +#
47 +
48 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
49 --- /dev/null
50 +++ b/board/avm/fb3370/ddr_settings.h
51 @@ -0,0 +1,69 @@
52 +/*
53 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
54 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
55 + *
56 + * SPDX-License-Identifier: GPL-2.0+
57 + */
58 +
59 +#define MC_CCR00_VALUE 0x101
60 +#define MC_CCR01_VALUE 0x1000100
61 +#define MC_CCR02_VALUE 0x1010000
62 +#define MC_CCR03_VALUE 0x101
63 +#define MC_CCR04_VALUE 0x1000000
64 +#define MC_CCR05_VALUE 0x1000101
65 +#define MC_CCR06_VALUE 0x1000100
66 +#define MC_CCR07_VALUE 0x1010000
67 +#define MC_CCR08_VALUE 0x1000101
68 +#define MC_CCR09_VALUE 0x0
69 +#define MC_CCR10_VALUE 0x2000100
70 +#define MC_CCR11_VALUE 0x2000300
71 +#define MC_CCR12_VALUE 0x30000
72 +#define MC_CCR13_VALUE 0x202
73 +#define MC_CCR14_VALUE 0x7080A0F
74 +#define MC_CCR15_VALUE 0x2040F
75 +#define MC_CCR16_VALUE 0x40000
76 +#define MC_CCR17_VALUE 0x70102
77 +#define MC_CCR18_VALUE 0x4020002
78 +#define MC_CCR19_VALUE 0x30302
79 +#define MC_CCR20_VALUE 0x8000700
80 +#define MC_CCR21_VALUE 0x40F020A
81 +#define MC_CCR22_VALUE 0x0
82 +#define MC_CCR23_VALUE 0xC020000
83 +#define MC_CCR24_VALUE 0x4401B04
84 +#define MC_CCR25_VALUE 0x0
85 +#define MC_CCR26_VALUE 0x0
86 +#define MC_CCR27_VALUE 0x6420000
87 +#define MC_CCR28_VALUE 0x0
88 +#define MC_CCR29_VALUE 0x0
89 +#define MC_CCR30_VALUE 0x798
90 +#define MC_CCR31_VALUE 0x0
91 +#define MC_CCR32_VALUE 0x0
92 +#define MC_CCR33_VALUE 0x650000
93 +#define MC_CCR34_VALUE 0x200C8
94 +#define MC_CCR35_VALUE 0x1D445D
95 +#define MC_CCR36_VALUE 0xC8
96 +#define MC_CCR37_VALUE 0xC351
97 +#define MC_CCR38_VALUE 0x0
98 +#define MC_CCR39_VALUE 0x141F04
99 +#define MC_CCR40_VALUE 0x142704
100 +#define MC_CCR41_VALUE 0x141B42
101 +#define MC_CCR42_VALUE 0x141B42
102 +#define MC_CCR43_VALUE 0x566504
103 +#define MC_CCR44_VALUE 0x566504
104 +#define MC_CCR45_VALUE 0x565F17
105 +#define MC_CCR46_VALUE 0x565F17
106 +#define MC_CCR47_VALUE 0x0
107 +#define MC_CCR48_VALUE 0x0
108 +#define MC_CCR49_VALUE 0x0
109 +#define MC_CCR50_VALUE 0x0
110 +#define MC_CCR51_VALUE 0x0
111 +#define MC_CCR52_VALUE 0x133
112 +#define MC_CCR53_VALUE 0xF3014B27
113 +#define MC_CCR54_VALUE 0xF3014B27
114 +#define MC_CCR55_VALUE 0xF3014B27
115 +#define MC_CCR56_VALUE 0xF3014B27
116 +#define MC_CCR57_VALUE 0x7800301
117 +#define MC_CCR58_VALUE 0x7800301
118 +#define MC_CCR59_VALUE 0x7800301
119 +#define MC_CCR60_VALUE 0x7800301
120 +#define MC_CCR61_VALUE 0x4
121 --- /dev/null
122 +++ b/board/avm/fb3370/fb3370.c
123 @@ -0,0 +1,138 @@
124 +/*
125 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
126 + *
127 + * SPDX-License-Identifier: GPL-2.0+
128 + */
129 +
130 +#include <common.h>
131 +#include <spi.h>
132 +#include <asm/gpio.h>
133 +#include <asm/lantiq/eth.h>
134 +#include <asm/lantiq/chipid.h>
135 +#include <asm/lantiq/cpu.h>
136 +#include <asm/arch/gphy.h>
137 +
138 +#if defined(CONFIG_SPL_BUILD)
139 +#define do_gpio_init 1
140 +#define do_pll_init 1
141 +#define do_dcdc_init 0
142 +#elif defined(CONFIG_SYS_BOOT_RAM)
143 +#define do_gpio_init 1
144 +#define do_pll_init 0
145 +#define do_dcdc_init 1
146 +#elif defined(CONFIG_SYS_BOOT_NOR)
147 +#define do_gpio_init 1
148 +#define do_pll_init 1
149 +#define do_dcdc_init 1
150 +#else
151 +#define do_gpio_init 0
152 +#define do_pll_init 0
153 +#define do_dcdc_init 1
154 +#endif
155 +
156 +static void gpio_init(void)
157 +{
158 + /* SPI CS 0.4 to serial flash */
159 + gpio_direction_output(10, 1);
160 +
161 + /* EBU.FL_CS1 as output for NAND CE */
162 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
163 + /* EBU.FL_A23 as output for NAND CLE */
164 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
165 + /* EBU.FL_A24 as output for NAND ALE */
166 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
167 + /* GPIO 3.0 as input for NAND Ready Busy */
168 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
169 + /* GPIO 3.1 as output for NAND Read */
170 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
171 +}
172 +
173 +int board_early_init_f(void)
174 +{
175 + if (do_gpio_init)
176 + gpio_init();
177 +
178 + if (do_pll_init)
179 + ltq_pll_init();
180 +
181 + if (do_dcdc_init)
182 + ltq_dcdc_init(0x7F);
183 +
184 + return 0;
185 +}
186 +
187 +int checkboard(void)
188 +{
189 + puts("Board: " CONFIG_BOARD_NAME "\n");
190 + ltq_chip_print_info();
191 +
192 + return 0;
193 +}
194 +
195 +static const struct ltq_eth_port_config eth_port_config[] = {
196 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
197 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
198 + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
199 + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
200 + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
201 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
202 + /* GMAC3: unused */
203 + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
204 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
205 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
206 + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
207 + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
208 +};
209 +
210 +static const struct ltq_eth_board_config eth_board_config = {
211 + .ports = eth_port_config,
212 + .num_ports = ARRAY_SIZE(eth_port_config),
213 +};
214 +
215 +int board_eth_init(bd_t * bis)
216 +{
217 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
218 + const ulong fw_addr = 0x80FF0000;
219 +
220 + ltq_gphy_phy11g_a1x_load(fw_addr);
221 +
222 + ltq_cgu_gphy_clk_src(clk);
223 +
224 + ltq_rcu_gphy_boot(0, fw_addr);
225 + ltq_rcu_gphy_boot(1, fw_addr);
226 +
227 + return ltq_eth_initialize(&eth_board_config);
228 +}
229 +
230 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
231 +{
232 + if (bus)
233 + return 0;
234 +
235 + if (cs == 4)
236 + return 1;
237 +
238 + return 0;
239 +}
240 +
241 +void spi_cs_activate(struct spi_slave *slave)
242 +{
243 + switch (slave->cs) {
244 + case 4:
245 + gpio_set_value(10, 0);
246 + break;
247 + default:
248 + break;
249 + }
250 +}
251 +
252 +void spi_cs_deactivate(struct spi_slave *slave)
253 +{
254 + switch (slave->cs) {
255 + case 4:
256 + gpio_set_value(10, 1);
257 + break;
258 + default:
259 + break;
260 + }
261 +}
262 --- a/boards.cfg
263 +++ b/boards.cfg
264 @@ -517,6 +517,9 @@ Active mips mips32 incai
265 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
266 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
267 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
268 +Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
269 +Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
270 +Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
271 Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
272 Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
273 Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
274 --- /dev/null
275 +++ b/include/configs/fb3370.h
276 @@ -0,0 +1,78 @@
277 +/*
278 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
279 + *
280 + * SPDX-License-Identifier: GPL-2.0+
281 + */
282 +
283 +#ifndef __CONFIG_H
284 +#define __CONFIG_H
285 +
286 +#define CONFIG_MACH_TYPE "FB3370"
287 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
288 +#define CONFIG_BOARD_NAME "AVM FritzBox 3370"
289 +
290 +/* Configure SoC */
291 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
292 +
293 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
294 +
295 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
296 +#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
297 +
298 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
299 +
300 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
301 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
302 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
303 +
304 +#define CONFIG_SPL_SPI_BUS 0
305 +#define CONFIG_SPL_SPI_CS 4
306 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
307 +#define CONFIG_SPL_SPI_MODE 0
308 +
309 +#define CONFIG_SYS_DRAM_PROBE
310 +
311 +/* Environment */
312 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
313 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
314 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
315 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
316 +
317 +#if defined(CONFIG_SYS_BOOT_SFSPL)
318 +#define CONFIG_ENV_IS_IN_SPI_FLASH
319 +#define CONFIG_ENV_OVERWRITE
320 +#define CONFIG_ENV_OFFSET (192 * 1024)
321 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
322 +#else
323 +#define CONFIG_ENV_IS_NOWHERE
324 +#endif
325 +
326 +#define CONFIG_ENV_SIZE (8 * 1024)
327 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
328 +
329 +#if defined(CONFIG_SYS_BOOT_EVA)
330 +#define CONFIG_SYS_TEXT_BASE 0x80100000
331 +#define CONFIG_SKIP_LOWLEVEL_INIT
332 +#endif
333 +
334 +/* Console */
335 +#define CONFIG_LTQ_ADVANCED_CONSOLE
336 +#define CONFIG_BAUDRATE 115200
337 +#define CONFIG_CONSOLE_ASC 1
338 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
339 +
340 +/* Pull in default board configs for Lantiq XWAY VRX200 */
341 +#include <asm/lantiq/config.h>
342 +#include <asm/arch/config.h>
343 +
344 +/* Pull in default OpenWrt configs for Lantiq SoC */
345 +#include "openwrt-lantiq-common.h"
346 +
347 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
348 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
349 +
350 +#define CONFIG_EXTRA_ENV_SETTINGS \
351 + CONFIG_ENV_LANTIQ_DEFAULTS \
352 + CONFIG_ENV_UPDATE_UBOOT_SF
353 +
354 +#endif /* __CONFIG_H */
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