package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_danube.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include "ifxmips_atm_core.h"
  49
  50 #ifdef CONFIG_DANUBE
  51
  52 #include "ifxmips_atm_fw_danube.h"
  53 #include "ifxmips_atm_fw_regs_danube.h"
  54
  55 #include <lantiq_soc.h>
  56
  57 #define EMA_CMD_BUF_LEN      0x0040
  58 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  59 #define EMA_DATA_BUF_LEN     0x0100
  60 #define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
  61 #define EMA_WRITE_BURST      0x2
  62 #define EMA_READ_BURST       0x2
  63
  64 static inline void reset_ppe(void);
  65
  66 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
  67 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
  68 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
  69 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
  70 #define IFX_PMU_MODULE_TPE       BIT(13)
  71 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
  72
  73 static inline void reset_ppe(void)
  74 {
  75 /*#ifdef MODULE
  76     unsigned int etop_cfg;
  77     unsigned int etop_mdio_cfg;
  78     unsigned int etop_ig_plen_ctrl;
  79     unsigned int enet_mac_cfg;
  80
  81     etop_cfg            = *IFX_PP32_ETOP_CFG;
  82     etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;
  83     etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;
  84     enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;
  85
  86     *IFX_PP32_ETOP_CFG &= ~0x03C0;
  87
  88     //  reset PPE
  89     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
  90
  91     *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;
  92     *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
  93     *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;
  94     *IFX_PP32_ETOP_CFG          = etop_cfg;
  95 #endif*/
  96 }
  97
  98 /*
  99  *  Description:
 100  *    Download PPE firmware binary code.
 101  *  Input:
 102  *    src       --- u32 *, binary code buffer
 103  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 104  *  Output:
 105  *    int       --- 0:    Success
 106  *                  else:           Error Code
 107  */
 108 static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 109 {
 110         volatile u32 *dest;
 111
 112         if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 113                         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 114                 return -1;
 115
 116         if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 117                 IFX_REG_W32(0x00, CDM_CFG);
 118         else
 119                 IFX_REG_W32(0x04, CDM_CFG);
 120
 121         /*  copy code   */
 122         dest = CDM_CODE_MEMORY(0, 0);
 123         while ( code_dword_len-- > 0 )
 124                 IFX_REG_W32(*code_src++, dest++);
 125
 126         /*  copy data   */
 127         dest = CDM_DATA_MEMORY(0, 0);
 128         while ( data_dword_len-- > 0 )
 129                 IFX_REG_W32(*data_src++, dest++);
 130
 131         return 0;
 132 }
 133
 134 static void danube_fw_ver(unsigned int *major, unsigned int *minor)
 135 {
 136         ASSERT(major != NULL, "pointer is NULL");
 137         ASSERT(minor != NULL, "pointer is NULL");
 138
 139         *major = FW_VER_ID->major;
 140         *minor = FW_VER_ID->minor;
 141 }
 142
 143 static void danube_init(void)
 144 {
 145             volatile u32 *p = SB_RAM0_ADDR(0);
 146     unsigned int i;
 147
 148         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 149                 IFX_PMU_MODULE_PPE_TC |
 150                 IFX_PMU_MODULE_PPE_EMA |
 151                 IFX_PMU_MODULE_PPE_QSB |
 152                 IFX_PMU_MODULE_TPE |
 153                 IFX_PMU_MODULE_DSL_DFE);
 154
 155         reset_ppe();
 156
 157     /* init ema */
 158         IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 159     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 160     IFX_REG_W32(0x000000FF, EMA_IER);
 161     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 162
 163         /* init mailbox */
 164         IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 165         IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 166         IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 167         IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 168
 169     /* init atm tc */
 170     IFX_REG_W32(0x0000,     DREG_AT_CTRL);
 171     IFX_REG_W32(0x0000,     DREG_AR_CTRL);
 172     IFX_REG_W32(0x0,        DREG_AT_IDLE0);
 173     IFX_REG_W32(0x0,        DREG_AT_IDLE1);
 174     IFX_REG_W32(0x0,        DREG_AR_IDLE0);
 175     IFX_REG_W32(0x0,        DREG_AR_IDLE1);
 176     IFX_REG_W32(0x40,       RFBI_CFG);
 177     IFX_REG_W32(0x1600,     SFSM_DBA0);
 178     IFX_REG_W32(0x1718,     SFSM_DBA1);
 179     IFX_REG_W32(0x1830,     SFSM_CBA0);
 180     IFX_REG_W32(0x1844,     SFSM_CBA1);
 181     IFX_REG_W32(0x14014,    SFSM_CFG0);
 182     IFX_REG_W32(0x14014,    SFSM_CFG1);
 183     IFX_REG_W32(0x1858,     FFSM_DBA0);
 184     IFX_REG_W32(0x18AC,     FFSM_DBA1);
 185     IFX_REG_W32(0x10006,    FFSM_CFG0);
 186     IFX_REG_W32(0x10006,    FFSM_CFG1);
 187     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
 188     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
 189
 190     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 191         IFX_REG_W32(0, p++);
 192 }
 193
 194 static void danube_shutdown(void)
 195 {
 196 }
 197
 198 int danube_start(int pp32)
 199 {
 200         int ret;
 201
 202         /*  download firmware   */
 203         ret = danube_pp32_download_code(
 204                 danube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin),
 205                 danube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data));
 206         if ( ret != 0 )
 207                 return ret;
 208
 209         /*  run PP32    */
 210         IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
 211
 212         /*  idle for a while to let PP32 init itself    */
 213         udelay(10);
 214
 215         return 0;
 216 }
 217
 218 void danube_stop(int pp32)
 219 {
 220         IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
 221 }
 222
 223 struct ltq_atm_ops danube_ops = {
 224         .init = danube_init,
 225         .shutdown = danube_shutdown,
 226         .start = danube_start,
 227         .stop = danube_stop,
 228         .fw_ver = danube_fw_ver,
 229 };
 230
 231 #endif