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ar71xx: don't set builtin_switch flag for QCA9558
[openwrt/staging/yousong.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
187 max_id = 1;
188 else
189 max_id = 0;
190
191 if (id > max_id) {
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
193 return;
194 }
195
196 switch (ath79_soc) {
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 mdio_dev = &ath79_mdio1_device;
201 mdio_data = &ath79_mdio1_data;
202 break;
203
204 case ATH79_SOC_AR9341:
205 case ATH79_SOC_AR9342:
206 case ATH79_SOC_AR9344:
207 case ATH79_SOC_QCA9556:
208 case ATH79_SOC_QCA9558:
209 if (id == 0) {
210 mdio_dev = &ath79_mdio0_device;
211 mdio_data = &ath79_mdio0_data;
212 } else {
213 mdio_dev = &ath79_mdio1_device;
214 mdio_data = &ath79_mdio1_data;
215 }
216 break;
217
218 case ATH79_SOC_AR7242:
219 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
220 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
221 AR71XX_ETH0_PLL_SHIFT);
222 /* fall through */
223 default:
224 mdio_dev = &ath79_mdio0_device;
225 mdio_data = &ath79_mdio0_data;
226 break;
227 }
228
229 mdio_data->phy_mask = phy_mask;
230
231 switch (ath79_soc) {
232 case ATH79_SOC_AR7240:
233 mdio_data->is_ar7240 = 1;
234 /* fall through */
235 case ATH79_SOC_AR7241:
236 mdio_data->builtin_switch = 1;
237 break;
238
239 case ATH79_SOC_AR9330:
240 mdio_data->is_ar9330 = 1;
241 /* fall through */
242 case ATH79_SOC_AR9331:
243 mdio_data->builtin_switch = 1;
244 break;
245
246 case ATH79_SOC_AR9341:
247 case ATH79_SOC_AR9342:
248 case ATH79_SOC_AR9344:
249 if (id == 1) {
250 mdio_data->builtin_switch = 1;
251 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
252 mdio_data->mdio_clock = 6250000;
253 }
254 mdio_data->is_ar934x = 1;
255 break;
256
257 case ATH79_SOC_QCA9556:
258 case ATH79_SOC_QCA9558:
259 mdio_data->is_ar934x = 1;
260 break;
261
262 default:
263 break;
264 }
265
266 platform_device_register(mdio_dev);
267 }
268
269 struct ath79_eth_pll_data ath79_eth0_pll_data;
270 struct ath79_eth_pll_data ath79_eth1_pll_data;
271
272 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
273 {
274 struct ath79_eth_pll_data *pll_data;
275 u32 pll_val;
276
277 switch (mac) {
278 case 0:
279 pll_data = &ath79_eth0_pll_data;
280 break;
281 case 1:
282 pll_data = &ath79_eth1_pll_data;
283 break;
284 default:
285 BUG();
286 }
287
288 switch (speed) {
289 case SPEED_10:
290 pll_val = pll_data->pll_10;
291 break;
292 case SPEED_100:
293 pll_val = pll_data->pll_100;
294 break;
295 case SPEED_1000:
296 pll_val = pll_data->pll_1000;
297 break;
298 default:
299 BUG();
300 }
301
302 return pll_val;
303 }
304
305 static void ath79_set_speed_ge0(int speed)
306 {
307 u32 val = ath79_get_eth_pll(0, speed);
308
309 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
310 val, AR71XX_ETH0_PLL_SHIFT);
311 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
312 }
313
314 static void ath79_set_speed_ge1(int speed)
315 {
316 u32 val = ath79_get_eth_pll(1, speed);
317
318 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
319 val, AR71XX_ETH1_PLL_SHIFT);
320 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
321 }
322
323 static void ar7242_set_speed_ge0(int speed)
324 {
325 u32 val = ath79_get_eth_pll(0, speed);
326 void __iomem *base;
327
328 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
329 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
330 iounmap(base);
331 }
332
333 static void ar91xx_set_speed_ge0(int speed)
334 {
335 u32 val = ath79_get_eth_pll(0, speed);
336
337 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
338 val, AR913X_ETH0_PLL_SHIFT);
339 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
340 }
341
342 static void ar91xx_set_speed_ge1(int speed)
343 {
344 u32 val = ath79_get_eth_pll(1, speed);
345
346 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
347 val, AR913X_ETH1_PLL_SHIFT);
348 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
349 }
350
351 static void ar934x_set_speed_ge0(int speed)
352 {
353 void __iomem *base;
354 u32 val = ath79_get_eth_pll(0, speed);
355
356 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
357 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
358 iounmap(base);
359 }
360
361 static void qca955x_set_speed_xmii(int speed)
362 {
363 void __iomem *base;
364 u32 val = ath79_get_eth_pll(0, speed);
365
366 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
367 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
368 iounmap(base);
369 }
370
371 static void qca955x_set_speed_sgmii(int speed)
372 {
373 void __iomem *base;
374 u32 val = ath79_get_eth_pll(1, speed);
375
376 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
377 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
378 iounmap(base);
379 }
380
381 static void ath79_set_speed_dummy(int speed)
382 {
383 }
384
385 static void ath79_ddr_no_flush(void)
386 {
387 }
388
389 static void ath79_ddr_flush_ge0(void)
390 {
391 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
392 }
393
394 static void ath79_ddr_flush_ge1(void)
395 {
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
397 }
398
399 static void ar724x_ddr_flush_ge0(void)
400 {
401 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
402 }
403
404 static void ar724x_ddr_flush_ge1(void)
405 {
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
407 }
408
409 static void ar91xx_ddr_flush_ge0(void)
410 {
411 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
412 }
413
414 static void ar91xx_ddr_flush_ge1(void)
415 {
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
417 }
418
419 static void ar933x_ddr_flush_ge0(void)
420 {
421 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
422 }
423
424 static void ar933x_ddr_flush_ge1(void)
425 {
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
427 }
428
429 static struct resource ath79_eth0_resources[] = {
430 {
431 .name = "mac_base",
432 .flags = IORESOURCE_MEM,
433 .start = AR71XX_GE0_BASE,
434 .end = AR71XX_GE0_BASE + 0x200 - 1,
435 }, {
436 .name = "mac_irq",
437 .flags = IORESOURCE_IRQ,
438 .start = ATH79_CPU_IRQ(4),
439 .end = ATH79_CPU_IRQ(4),
440 },
441 };
442
443 struct ag71xx_platform_data ath79_eth0_data = {
444 .reset_bit = AR71XX_RESET_GE0_MAC,
445 };
446
447 struct platform_device ath79_eth0_device = {
448 .name = "ag71xx",
449 .id = 0,
450 .resource = ath79_eth0_resources,
451 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
452 .dev = {
453 .platform_data = &ath79_eth0_data,
454 },
455 };
456
457 static struct resource ath79_eth1_resources[] = {
458 {
459 .name = "mac_base",
460 .flags = IORESOURCE_MEM,
461 .start = AR71XX_GE1_BASE,
462 .end = AR71XX_GE1_BASE + 0x200 - 1,
463 }, {
464 .name = "mac_irq",
465 .flags = IORESOURCE_IRQ,
466 .start = ATH79_CPU_IRQ(5),
467 .end = ATH79_CPU_IRQ(5),
468 },
469 };
470
471 struct ag71xx_platform_data ath79_eth1_data = {
472 .reset_bit = AR71XX_RESET_GE1_MAC,
473 };
474
475 struct platform_device ath79_eth1_device = {
476 .name = "ag71xx",
477 .id = 1,
478 .resource = ath79_eth1_resources,
479 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
480 .dev = {
481 .platform_data = &ath79_eth1_data,
482 },
483 };
484
485 struct ag71xx_switch_platform_data ath79_switch_data;
486
487 #define AR71XX_PLL_VAL_1000 0x00110000
488 #define AR71XX_PLL_VAL_100 0x00001099
489 #define AR71XX_PLL_VAL_10 0x00991099
490
491 #define AR724X_PLL_VAL_1000 0x00110000
492 #define AR724X_PLL_VAL_100 0x00001099
493 #define AR724X_PLL_VAL_10 0x00991099
494
495 #define AR7242_PLL_VAL_1000 0x16000000
496 #define AR7242_PLL_VAL_100 0x00000101
497 #define AR7242_PLL_VAL_10 0x00001616
498
499 #define AR913X_PLL_VAL_1000 0x1a000000
500 #define AR913X_PLL_VAL_100 0x13000a44
501 #define AR913X_PLL_VAL_10 0x00441099
502
503 #define AR933X_PLL_VAL_1000 0x00110000
504 #define AR933X_PLL_VAL_100 0x00001099
505 #define AR933X_PLL_VAL_10 0x00991099
506
507 #define AR934X_PLL_VAL_1000 0x16000000
508 #define AR934X_PLL_VAL_100 0x00000101
509 #define AR934X_PLL_VAL_10 0x00001616
510
511 static void __init ath79_init_eth_pll_data(unsigned int id)
512 {
513 struct ath79_eth_pll_data *pll_data;
514 u32 pll_10, pll_100, pll_1000;
515
516 switch (id) {
517 case 0:
518 pll_data = &ath79_eth0_pll_data;
519 break;
520 case 1:
521 pll_data = &ath79_eth1_pll_data;
522 break;
523 default:
524 BUG();
525 }
526
527 switch (ath79_soc) {
528 case ATH79_SOC_AR7130:
529 case ATH79_SOC_AR7141:
530 case ATH79_SOC_AR7161:
531 pll_10 = AR71XX_PLL_VAL_10;
532 pll_100 = AR71XX_PLL_VAL_100;
533 pll_1000 = AR71XX_PLL_VAL_1000;
534 break;
535
536 case ATH79_SOC_AR7240:
537 case ATH79_SOC_AR7241:
538 pll_10 = AR724X_PLL_VAL_10;
539 pll_100 = AR724X_PLL_VAL_100;
540 pll_1000 = AR724X_PLL_VAL_1000;
541 break;
542
543 case ATH79_SOC_AR7242:
544 pll_10 = AR7242_PLL_VAL_10;
545 pll_100 = AR7242_PLL_VAL_100;
546 pll_1000 = AR7242_PLL_VAL_1000;
547 break;
548
549 case ATH79_SOC_AR9130:
550 case ATH79_SOC_AR9132:
551 pll_10 = AR913X_PLL_VAL_10;
552 pll_100 = AR913X_PLL_VAL_100;
553 pll_1000 = AR913X_PLL_VAL_1000;
554 break;
555
556 case ATH79_SOC_AR9330:
557 case ATH79_SOC_AR9331:
558 pll_10 = AR933X_PLL_VAL_10;
559 pll_100 = AR933X_PLL_VAL_100;
560 pll_1000 = AR933X_PLL_VAL_1000;
561 break;
562
563 case ATH79_SOC_AR9341:
564 case ATH79_SOC_AR9342:
565 case ATH79_SOC_AR9344:
566 case ATH79_SOC_QCA9556:
567 case ATH79_SOC_QCA9558:
568 pll_10 = AR934X_PLL_VAL_10;
569 pll_100 = AR934X_PLL_VAL_100;
570 pll_1000 = AR934X_PLL_VAL_1000;
571 break;
572
573 default:
574 BUG();
575 }
576
577 if (!pll_data->pll_10)
578 pll_data->pll_10 = pll_10;
579
580 if (!pll_data->pll_100)
581 pll_data->pll_100 = pll_100;
582
583 if (!pll_data->pll_1000)
584 pll_data->pll_1000 = pll_1000;
585 }
586
587 static int __init ath79_setup_phy_if_mode(unsigned int id,
588 struct ag71xx_platform_data *pdata)
589 {
590 unsigned int mii_if;
591
592 switch (id) {
593 case 0:
594 switch (ath79_soc) {
595 case ATH79_SOC_AR7130:
596 case ATH79_SOC_AR7141:
597 case ATH79_SOC_AR7161:
598 case ATH79_SOC_AR9130:
599 case ATH79_SOC_AR9132:
600 switch (pdata->phy_if_mode) {
601 case PHY_INTERFACE_MODE_MII:
602 mii_if = AR71XX_MII0_CTRL_IF_MII;
603 break;
604 case PHY_INTERFACE_MODE_GMII:
605 mii_if = AR71XX_MII0_CTRL_IF_GMII;
606 break;
607 case PHY_INTERFACE_MODE_RGMII:
608 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
609 break;
610 case PHY_INTERFACE_MODE_RMII:
611 mii_if = AR71XX_MII0_CTRL_IF_RMII;
612 break;
613 default:
614 return -EINVAL;
615 }
616 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
617 break;
618
619 case ATH79_SOC_AR7240:
620 case ATH79_SOC_AR7241:
621 case ATH79_SOC_AR9330:
622 case ATH79_SOC_AR9331:
623 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
624 break;
625
626 case ATH79_SOC_AR7242:
627 /* FIXME */
628
629 case ATH79_SOC_AR9341:
630 case ATH79_SOC_AR9342:
631 case ATH79_SOC_AR9344:
632 switch (pdata->phy_if_mode) {
633 case PHY_INTERFACE_MODE_MII:
634 case PHY_INTERFACE_MODE_GMII:
635 case PHY_INTERFACE_MODE_RGMII:
636 case PHY_INTERFACE_MODE_RMII:
637 break;
638 default:
639 return -EINVAL;
640 }
641 break;
642
643 case ATH79_SOC_QCA9556:
644 case ATH79_SOC_QCA9558:
645 switch (pdata->phy_if_mode) {
646 case PHY_INTERFACE_MODE_MII:
647 case PHY_INTERFACE_MODE_RGMII:
648 case PHY_INTERFACE_MODE_SGMII:
649 break;
650 default:
651 return -EINVAL;
652 }
653 break;
654
655 default:
656 BUG();
657 }
658 break;
659 case 1:
660 switch (ath79_soc) {
661 case ATH79_SOC_AR7130:
662 case ATH79_SOC_AR7141:
663 case ATH79_SOC_AR7161:
664 case ATH79_SOC_AR9130:
665 case ATH79_SOC_AR9132:
666 switch (pdata->phy_if_mode) {
667 case PHY_INTERFACE_MODE_RMII:
668 mii_if = AR71XX_MII1_CTRL_IF_RMII;
669 break;
670 case PHY_INTERFACE_MODE_RGMII:
671 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
672 break;
673 default:
674 return -EINVAL;
675 }
676 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
677 break;
678
679 case ATH79_SOC_AR7240:
680 case ATH79_SOC_AR7241:
681 case ATH79_SOC_AR9330:
682 case ATH79_SOC_AR9331:
683 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
684 break;
685
686 case ATH79_SOC_AR7242:
687 /* FIXME */
688
689 case ATH79_SOC_AR9341:
690 case ATH79_SOC_AR9342:
691 case ATH79_SOC_AR9344:
692 switch (pdata->phy_if_mode) {
693 case PHY_INTERFACE_MODE_MII:
694 case PHY_INTERFACE_MODE_GMII:
695 break;
696 default:
697 return -EINVAL;
698 }
699 break;
700
701 case ATH79_SOC_QCA9556:
702 case ATH79_SOC_QCA9558:
703 switch (pdata->phy_if_mode) {
704 case PHY_INTERFACE_MODE_MII:
705 case PHY_INTERFACE_MODE_RGMII:
706 case PHY_INTERFACE_MODE_SGMII:
707 break;
708 default:
709 return -EINVAL;
710 }
711 break;
712
713 default:
714 BUG();
715 }
716 break;
717 }
718
719 return 0;
720 }
721
722 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
723 {
724 void __iomem *base;
725 u32 t;
726
727 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
728
729 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
730 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
731 if (mac)
732 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
733 if (mdio)
734 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
735 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
736
737 iounmap(base);
738 }
739
740 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
741 {
742 void __iomem *base;
743 u32 t;
744
745 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
746
747 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
748
749 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
750 AR934X_ETH_CFG_MII_GMAC0 |
751 AR934X_ETH_CFG_GMII_GMAC0 |
752 AR934X_ETH_CFG_SW_ONLY_MODE |
753 AR934X_ETH_CFG_SW_PHY_SWAP);
754
755 t |= mask;
756
757 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
758 /* flush write */
759 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
760
761 iounmap(base);
762 }
763
764 static int ath79_eth_instance __initdata;
765 void __init ath79_register_eth(unsigned int id)
766 {
767 struct platform_device *pdev;
768 struct ag71xx_platform_data *pdata;
769 int err;
770
771 if (id > 1) {
772 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
773 return;
774 }
775
776 ath79_init_eth_pll_data(id);
777
778 if (id == 0)
779 pdev = &ath79_eth0_device;
780 else
781 pdev = &ath79_eth1_device;
782
783 pdata = pdev->dev.platform_data;
784
785 pdata->max_frame_len = 1540;
786 pdata->desc_pktlen_mask = 0xfff;
787
788 err = ath79_setup_phy_if_mode(id, pdata);
789 if (err) {
790 printk(KERN_ERR
791 "ar71xx: invalid PHY interface mode for GE%u\n", id);
792 return;
793 }
794
795 switch (ath79_soc) {
796 case ATH79_SOC_AR7130:
797 if (id == 0) {
798 pdata->ddr_flush = ath79_ddr_flush_ge0;
799 pdata->set_speed = ath79_set_speed_ge0;
800 } else {
801 pdata->ddr_flush = ath79_ddr_flush_ge1;
802 pdata->set_speed = ath79_set_speed_ge1;
803 }
804 break;
805
806 case ATH79_SOC_AR7141:
807 case ATH79_SOC_AR7161:
808 if (id == 0) {
809 pdata->ddr_flush = ath79_ddr_flush_ge0;
810 pdata->set_speed = ath79_set_speed_ge0;
811 } else {
812 pdata->ddr_flush = ath79_ddr_flush_ge1;
813 pdata->set_speed = ath79_set_speed_ge1;
814 }
815 pdata->has_gbit = 1;
816 break;
817
818 case ATH79_SOC_AR7242:
819 if (id == 0) {
820 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
821 AR71XX_RESET_GE0_PHY;
822 pdata->ddr_flush = ar724x_ddr_flush_ge0;
823 pdata->set_speed = ar7242_set_speed_ge0;
824 } else {
825 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
826 AR71XX_RESET_GE1_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge1;
828 pdata->set_speed = ath79_set_speed_dummy;
829 }
830 pdata->has_gbit = 1;
831 pdata->is_ar724x = 1;
832
833 if (!pdata->fifo_cfg1)
834 pdata->fifo_cfg1 = 0x0010ffff;
835 if (!pdata->fifo_cfg2)
836 pdata->fifo_cfg2 = 0x015500aa;
837 if (!pdata->fifo_cfg3)
838 pdata->fifo_cfg3 = 0x01f00140;
839 break;
840
841 case ATH79_SOC_AR7241:
842 if (id == 0)
843 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
844 else
845 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
846 /* fall through */
847 case ATH79_SOC_AR7240:
848 if (id == 0) {
849 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
850 pdata->ddr_flush = ar724x_ddr_flush_ge0;
851 pdata->set_speed = ath79_set_speed_dummy;
852
853 pdata->phy_mask = BIT(4);
854 } else {
855 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
856 pdata->ddr_flush = ar724x_ddr_flush_ge1;
857 pdata->set_speed = ath79_set_speed_dummy;
858
859 pdata->speed = SPEED_1000;
860 pdata->duplex = DUPLEX_FULL;
861 pdata->switch_data = &ath79_switch_data;
862
863 ath79_switch_data.phy_poll_mask |= BIT(4);
864 }
865 pdata->has_gbit = 1;
866 pdata->is_ar724x = 1;
867 if (ath79_soc == ATH79_SOC_AR7240)
868 pdata->is_ar7240 = 1;
869
870 if (!pdata->fifo_cfg1)
871 pdata->fifo_cfg1 = 0x0010ffff;
872 if (!pdata->fifo_cfg2)
873 pdata->fifo_cfg2 = 0x015500aa;
874 if (!pdata->fifo_cfg3)
875 pdata->fifo_cfg3 = 0x01f00140;
876 break;
877
878 case ATH79_SOC_AR9130:
879 if (id == 0) {
880 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
881 pdata->set_speed = ar91xx_set_speed_ge0;
882 } else {
883 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
884 pdata->set_speed = ar91xx_set_speed_ge1;
885 }
886 pdata->is_ar91xx = 1;
887 break;
888
889 case ATH79_SOC_AR9132:
890 if (id == 0) {
891 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
892 pdata->set_speed = ar91xx_set_speed_ge0;
893 } else {
894 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
895 pdata->set_speed = ar91xx_set_speed_ge1;
896 }
897 pdata->is_ar91xx = 1;
898 pdata->has_gbit = 1;
899 break;
900
901 case ATH79_SOC_AR9330:
902 case ATH79_SOC_AR9331:
903 if (id == 0) {
904 pdata->reset_bit = AR933X_RESET_GE0_MAC |
905 AR933X_RESET_GE0_MDIO;
906 pdata->ddr_flush = ar933x_ddr_flush_ge0;
907 pdata->set_speed = ath79_set_speed_dummy;
908
909 pdata->phy_mask = BIT(4);
910 } else {
911 pdata->reset_bit = AR933X_RESET_GE1_MAC |
912 AR933X_RESET_GE1_MDIO;
913 pdata->ddr_flush = ar933x_ddr_flush_ge1;
914 pdata->set_speed = ath79_set_speed_dummy;
915
916 pdata->speed = SPEED_1000;
917 pdata->duplex = DUPLEX_FULL;
918 pdata->switch_data = &ath79_switch_data;
919
920 ath79_switch_data.phy_poll_mask |= BIT(4);
921 }
922
923 pdata->has_gbit = 1;
924 pdata->is_ar724x = 1;
925
926 if (!pdata->fifo_cfg1)
927 pdata->fifo_cfg1 = 0x0010ffff;
928 if (!pdata->fifo_cfg2)
929 pdata->fifo_cfg2 = 0x015500aa;
930 if (!pdata->fifo_cfg3)
931 pdata->fifo_cfg3 = 0x01f00140;
932 break;
933
934 case ATH79_SOC_AR9341:
935 case ATH79_SOC_AR9342:
936 case ATH79_SOC_AR9344:
937 if (id == 0) {
938 pdata->reset_bit = AR934X_RESET_GE0_MAC |
939 AR934X_RESET_GE0_MDIO;
940 pdata->set_speed = ar934x_set_speed_ge0;
941 } else {
942 pdata->reset_bit = AR934X_RESET_GE1_MAC |
943 AR934X_RESET_GE1_MDIO;
944 pdata->set_speed = ath79_set_speed_dummy;
945
946 pdata->switch_data = &ath79_switch_data;
947
948 /* reset the built-in switch */
949 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
950 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
951 }
952
953 pdata->ddr_flush = ath79_ddr_no_flush;
954 pdata->has_gbit = 1;
955 pdata->is_ar724x = 1;
956
957 pdata->max_frame_len = SZ_16K - 1;
958 pdata->desc_pktlen_mask = SZ_16K - 1;
959
960 if (!pdata->fifo_cfg1)
961 pdata->fifo_cfg1 = 0x0010ffff;
962 if (!pdata->fifo_cfg2)
963 pdata->fifo_cfg2 = 0x015500aa;
964 if (!pdata->fifo_cfg3)
965 pdata->fifo_cfg3 = 0x01f00140;
966 break;
967
968 case ATH79_SOC_QCA9556:
969 case ATH79_SOC_QCA9558:
970 if (id == 0) {
971 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
972 QCA955X_RESET_GE0_MDIO;
973 pdata->set_speed = qca955x_set_speed_xmii;
974 } else {
975 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
976 QCA955X_RESET_GE1_MDIO;
977 pdata->set_speed = qca955x_set_speed_sgmii;
978 }
979
980 pdata->ddr_flush = ath79_ddr_no_flush;
981 pdata->has_gbit = 1;
982 pdata->is_ar724x = 1;
983
984 if (!pdata->fifo_cfg1)
985 pdata->fifo_cfg1 = 0x0010ffff;
986 if (!pdata->fifo_cfg2)
987 pdata->fifo_cfg2 = 0x015500aa;
988 if (!pdata->fifo_cfg3)
989 pdata->fifo_cfg3 = 0x01f00140;
990 break;
991
992 default:
993 BUG();
994 }
995
996 switch (pdata->phy_if_mode) {
997 case PHY_INTERFACE_MODE_GMII:
998 case PHY_INTERFACE_MODE_RGMII:
999 case PHY_INTERFACE_MODE_SGMII:
1000 if (!pdata->has_gbit) {
1001 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1002 id);
1003 return;
1004 }
1005 /* fallthrough */
1006 default:
1007 break;
1008 }
1009
1010 if (!is_valid_ether_addr(pdata->mac_addr)) {
1011 random_ether_addr(pdata->mac_addr);
1012 printk(KERN_DEBUG
1013 "ar71xx: using random MAC address for eth%d\n",
1014 ath79_eth_instance);
1015 }
1016
1017 if (pdata->mii_bus_dev == NULL) {
1018 switch (ath79_soc) {
1019 case ATH79_SOC_AR9341:
1020 case ATH79_SOC_AR9342:
1021 case ATH79_SOC_AR9344:
1022 if (id == 0)
1023 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1024 else
1025 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1026 break;
1027
1028 case ATH79_SOC_AR7241:
1029 case ATH79_SOC_AR9330:
1030 case ATH79_SOC_AR9331:
1031 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1032 break;
1033
1034 case ATH79_SOC_QCA9556:
1035 case ATH79_SOC_QCA9558:
1036 /* don't assign any MDIO device by default */
1037 break;
1038
1039 default:
1040 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1041 break;
1042 }
1043 }
1044
1045 /* Reset the device */
1046 ath79_device_reset_set(pdata->reset_bit);
1047 mdelay(100);
1048
1049 ath79_device_reset_clear(pdata->reset_bit);
1050 mdelay(100);
1051
1052 platform_device_register(pdev);
1053 ath79_eth_instance++;
1054 }
1055
1056 void __init ath79_set_mac_base(unsigned char *mac)
1057 {
1058 memcpy(ath79_mac_base, mac, ETH_ALEN);
1059 }
1060
1061 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1062 {
1063 int t;
1064
1065 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1066 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1067
1068 if (t != ETH_ALEN)
1069 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1070 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1071
1072 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1073 memset(mac, 0, ETH_ALEN);
1074 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1075 mac_str);
1076 }
1077 }
1078
1079 static void __init ath79_set_mac_base_ascii(char *str)
1080 {
1081 u8 mac[ETH_ALEN];
1082
1083 ath79_parse_ascii_mac(str, mac);
1084 ath79_set_mac_base(mac);
1085 }
1086
1087 static int __init ath79_ethaddr_setup(char *str)
1088 {
1089 ath79_set_mac_base_ascii(str);
1090 return 1;
1091 }
1092 __setup("ethaddr=", ath79_ethaddr_setup);
1093
1094 static int __init ath79_kmac_setup(char *str)
1095 {
1096 ath79_set_mac_base_ascii(str);
1097 return 1;
1098 }
1099 __setup("kmac=", ath79_kmac_setup);
1100
1101 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1102 int offset)
1103 {
1104 int t;
1105
1106 if (!dst)
1107 return;
1108
1109 if (!src || !is_valid_ether_addr(src)) {
1110 memset(dst, '\0', ETH_ALEN);
1111 return;
1112 }
1113
1114 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1115 t += offset;
1116
1117 dst[0] = src[0];
1118 dst[1] = src[1];
1119 dst[2] = src[2];
1120 dst[3] = (t >> 16) & 0xff;
1121 dst[4] = (t >> 8) & 0xff;
1122 dst[5] = t & 0xff;
1123 }
1124
1125 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1126 {
1127 int i;
1128
1129 if (!dst)
1130 return;
1131
1132 if (!src || !is_valid_ether_addr(src)) {
1133 memset(dst, '\0', ETH_ALEN);
1134 return;
1135 }
1136
1137 for (i = 0; i < ETH_ALEN; i++)
1138 dst[i] = src[i];
1139 dst[0] |= 0x02;
1140 }
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