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rtl8366_smi: move chip specific stuff into its own struct
[openwrt/staging/yousong.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
29 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
30 #define RTL8366_SMI_DRIVER_VER "0.1.1"
31
32 #define RTL8366S_PHY_NO_MAX 4
33 #define RTL8366S_PHY_PAGE_MAX 7
34 #define RTL8366S_PHY_ADDR_MAX 31
35
36 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
37 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
38
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0105
46 #define RTL8366S_CHIP_ID_8366 0x8366
47
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
51
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
54
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60
61 #define RTL8366_SMI_ACK_RETRY_COUNT 5
62 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
63
64 /* LED control registers */
65 #define RTL8366_LED_BLINKRATE_REG 0x0420
66 #define RTL8366_LED_BLINKRATE_BIT 0
67 #define RTL8366_LED_BLINKRATE_MASK 0x0007
68
69 #define RTL8366_LED_CTRL_REG 0x0421
70 #define RTL8366_LED_0_1_CTRL_REG 0x0422
71 #define RTL8366_LED_2_3_CTRL_REG 0x0423
72
73 #define RTL8366S_MIB_COUNT 33
74 #define RTL8366S_GLOBAL_MIB_COUNT 1
75 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
76 #define RTL8366S_MIB_COUNTER_BASE 0x1000
77 #define RTL8366S_MIB_CTRL_REG 0x11F0
78 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
79 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
80 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
81
82 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
83 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
84 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
85
86
87 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
88 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
89 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
90 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
91 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
92
93
94 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
95 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
96
97 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
98
99 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
100 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
101 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
102
103 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
104
105
106 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
107 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
108 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
109 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
110 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
111 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
112 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
113
114
115 #define RTL8366_PORT_NUM_CPU 5
116 #define RTL8366_NUM_PORTS 6
117 #define RTL8366_NUM_VLANS 16
118 #define RTL8366_NUM_LEDGROUPS 4
119 #define RTL8366_NUM_VIDS 4096
120 #define RTL8366S_PRIORITYMAX 7
121 #define RTL8366S_FIDMAX 7
122
123
124 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
125 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
126 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
127 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
128
129 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
130 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
131
132 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
133 RTL8366_PORT_2 | \
134 RTL8366_PORT_3 | \
135 RTL8366_PORT_4 | \
136 RTL8366_PORT_UNKNOWN | \
137 RTL8366_PORT_CPU)
138
139 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
140 RTL8366_PORT_2 | \
141 RTL8366_PORT_3 | \
142 RTL8366_PORT_4 | \
143 RTL8366_PORT_UNKNOWN)
144
145 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 RTL8366_PORT_2 | \
147 RTL8366_PORT_3 | \
148 RTL8366_PORT_4)
149
150 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
151 RTL8366_PORT_CPU)
152
153 struct rtl8366s_vlanconfig {
154 u16 reserved2:1;
155 u16 priority:3;
156 u16 vid:12;
157
158 u16 reserved1:1;
159 u16 fid:3;
160 u16 untag:6;
161 u16 member:6;
162 };
163
164 struct rtl8366s_vlan4kentry {
165 u16 reserved1:4;
166 u16 vid:12;
167
168 u16 reserved2:1;
169 u16 fid:3;
170 u16 untag:6;
171 u16 member:6;
172 };
173
174 static const char *MIBCOUNTERS[] = {
175 "IfInOctets ",
176 "EtherStatsOctets ",
177 "EtherStatsUnderSizePkts ",
178 "EtherFregament ",
179 "EtherStatsPkts64Octets ",
180 "EtherStatsPkts65to127Octets ",
181 "EtherStatsPkts128to255Octets ",
182 "EtherStatsPkts256to511Octets ",
183 "EtherStatsPkts512to1023Octets ",
184 "EtherStatsPkts1024to1518Octets ",
185 "EtherOversizeStats ",
186 "EtherStatsJabbers ",
187 "IfInUcastPkts ",
188 "EtherStatsMulticastPkts ",
189 "EtherStatsBroadcastPkts ",
190 "EtherStatsDropEvents ",
191 "Dot3StatsFCSErrors ",
192 "Dot3StatsSymbolErrors ",
193 "Dot3InPauseFrames ",
194 "Dot3ControlInUnknownOpcodes ",
195 "IfOutOctets ",
196 "Dot3StatsSingleCollisionFrames ",
197 "Dot3StatMultipleCollisionFrames ",
198 "Dot3sDeferredTransmissions ",
199 "Dot3StatsLateCollisions ",
200 "EtherStatsCollisions ",
201 "Dot3StatsExcessiveCollisions ",
202 "Dot3OutPauseFrames ",
203 "Dot1dBasePortDelayExceededDiscards",
204 "Dot1dTpPortInDiscards ",
205 "IfOutUcastPkts ",
206 "IfOutMulticastPkts ",
207 "IfOutBroadcastPkts ",
208 NULL,
209 };
210
211 struct rtl8366_smi {
212 struct device *parent;
213 unsigned int gpio_sda;
214 unsigned int gpio_sck;
215 spinlock_t lock;
216 };
217
218 struct rtl8366s {
219 struct device *parent;
220 struct rtl8366_smi smi;
221 struct mii_bus *mii_bus;
222 int mii_irq[PHY_MAX_ADDR];
223 struct switch_dev dev;
224 char buf[4096];
225 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
226 struct dentry *debugfs_root;
227 #endif
228 };
229
230 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
231 u16 g_dbg_reg;
232 #endif
233
234 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
235 {
236 return container_of(sw, struct rtl8366s, dev);
237 }
238
239 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
240 {
241 ndelay(RTL8366_SMI_CLK_DELAY);
242 }
243
244 static void rtl8366_smi_start(struct rtl8366_smi *smi)
245 {
246 unsigned int sda = smi->gpio_sda;
247 unsigned int sck = smi->gpio_sck;
248
249 /*
250 * Set GPIO pins to output mode, with initial state:
251 * SCK = 0, SDA = 1
252 */
253 gpio_direction_output(sck, 0);
254 gpio_direction_output(sda, 1);
255 rtl8366_smi_clk_delay(smi);
256
257 /* CLK 1: 0 -> 1, 1 -> 0 */
258 gpio_set_value(sck, 1);
259 rtl8366_smi_clk_delay(smi);
260 gpio_set_value(sck, 0);
261 rtl8366_smi_clk_delay(smi);
262
263 /* CLK 2: */
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 0);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 0);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sda, 1);
271 }
272
273 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
274 {
275 unsigned int sda = smi->gpio_sda;
276 unsigned int sck = smi->gpio_sck;
277
278 rtl8366_smi_clk_delay(smi);
279 gpio_set_value(sda, 0);
280 gpio_set_value(sck, 1);
281 rtl8366_smi_clk_delay(smi);
282 gpio_set_value(sda, 1);
283 rtl8366_smi_clk_delay(smi);
284 gpio_set_value(sck, 1);
285 rtl8366_smi_clk_delay(smi);
286 gpio_set_value(sck, 0);
287 rtl8366_smi_clk_delay(smi);
288 gpio_set_value(sck, 1);
289
290 /* add a click */
291 rtl8366_smi_clk_delay(smi);
292 gpio_set_value(sck, 0);
293 rtl8366_smi_clk_delay(smi);
294 gpio_set_value(sck, 1);
295
296 /* set GPIO pins to input mode */
297 gpio_direction_input(sda);
298 gpio_direction_input(sck);
299 }
300
301 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
302 {
303 unsigned int sda = smi->gpio_sda;
304 unsigned int sck = smi->gpio_sck;
305
306 for (; len > 0; len--) {
307 rtl8366_smi_clk_delay(smi);
308
309 /* prepare data */
310 if ( data & ( 1 << (len - 1)) )
311 gpio_set_value(sda, 1);
312 else
313 gpio_set_value(sda, 0);
314 rtl8366_smi_clk_delay(smi);
315
316 /* clocking */
317 gpio_set_value(sck, 1);
318 rtl8366_smi_clk_delay(smi);
319 gpio_set_value(sck, 0);
320 }
321 }
322
323 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
324 {
325 unsigned int sda = smi->gpio_sda;
326 unsigned int sck = smi->gpio_sck;
327
328 gpio_direction_input(sda);
329
330 for (*data = 0; len > 0; len--) {
331 u32 u;
332
333 rtl8366_smi_clk_delay(smi);
334
335 /* clocking */
336 gpio_set_value(sck, 1);
337 rtl8366_smi_clk_delay(smi);
338 u = gpio_get_value(sda);
339 gpio_set_value(sck, 0);
340
341 *data |= (u << (len - 1));
342 }
343
344 gpio_direction_output(sda, 0);
345 }
346
347 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
348 {
349 int retry_cnt;
350
351 retry_cnt = 0;
352 do {
353 u32 ack;
354
355 rtl8366_smi_read_bits(smi, 1, &ack);
356 if (ack == 0)
357 break;
358
359 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
360 return -EIO;
361 } while (1);
362
363 return 0;
364 }
365
366 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
367 {
368 rtl8366_smi_write_bits(smi, data, 8);
369 return rtl8366_smi_wait_for_ack(smi);
370 }
371
372 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
373 {
374 u32 t;
375
376 /* read data */
377 rtl8366_smi_read_bits(smi, 8, &t);
378 *data = (t & 0xff);
379
380 /* send an ACK */
381 rtl8366_smi_write_bits(smi, 0x00, 1);
382
383 return 0;
384 }
385
386 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
387 {
388 u32 t;
389
390 /* read data */
391 rtl8366_smi_read_bits(smi, 8, &t);
392 *data = (t & 0xff);
393
394 /* send an ACK */
395 rtl8366_smi_write_bits(smi, 0x01, 1);
396
397 return 0;
398 }
399
400 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
401 {
402 unsigned long flags;
403 u8 lo = 0;
404 u8 hi = 0;
405 int ret;
406
407 spin_lock_irqsave(&smi->lock, flags);
408
409 rtl8366_smi_start(smi);
410
411 /* send READ command */
412 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
413 if (ret)
414 goto out;
415
416 /* set ADDR[7:0] */
417 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
418 if (ret)
419 goto out;
420
421 /* set ADDR[15:8] */
422 ret = rtl8366_smi_write_byte(smi, addr >> 8);
423 if (ret)
424 goto out;
425
426 /* read DATA[7:0] */
427 rtl8366_smi_read_byte0(smi, &lo);
428 /* read DATA[15:8] */
429 rtl8366_smi_read_byte1(smi, &hi);
430
431 *data = ((u32) lo) | (((u32) hi) << 8);
432
433 ret = 0;
434
435 out:
436 rtl8366_smi_stop(smi);
437 spin_unlock_irqrestore(&smi->lock, flags);
438
439 return ret;
440 }
441
442 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
443 {
444 unsigned long flags;
445 int ret;
446
447 spin_lock_irqsave(&smi->lock, flags);
448
449 rtl8366_smi_start(smi);
450
451 /* send WRITE command */
452 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
453 if (ret)
454 goto out;
455
456 /* set ADDR[7:0] */
457 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
458 if (ret)
459 goto out;
460
461 /* set ADDR[15:8] */
462 ret = rtl8366_smi_write_byte(smi, addr >> 8);
463 if (ret)
464 goto out;
465
466 /* write DATA[7:0] */
467 ret = rtl8366_smi_write_byte(smi, data & 0xff);
468 if (ret)
469 goto out;
470
471 /* write DATA[15:8] */
472 ret = rtl8366_smi_write_byte(smi, data >> 8);
473 if (ret)
474 goto out;
475
476 ret = 0;
477
478 out:
479 rtl8366_smi_stop(smi);
480 spin_unlock_irqrestore(&smi->lock, flags);
481
482 return ret;
483 }
484
485 static int rtl8366_smi_read_phy_reg(struct rtl8366s *rtl,
486 u32 phy_no, u32 page, u32 addr, u32 *data)
487 {
488 struct rtl8366_smi *smi = &rtl->smi;
489 u32 reg;
490 int ret;
491
492 if (phy_no > RTL8366S_PHY_NO_MAX)
493 return -EINVAL;
494
495 if (page > RTL8366S_PHY_PAGE_MAX)
496 return -EINVAL;
497
498 if (addr > RTL8366S_PHY_ADDR_MAX)
499 return -EINVAL;
500
501 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
502 RTL8366S_PHY_CTRL_READ);
503 if (ret)
504 return ret;
505
506 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
507 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
508 (addr & RTL8366S_PHY_REG_MASK);
509
510 ret = rtl8366_smi_write_reg(smi, reg, 0);
511 if (ret)
512 return ret;
513
514 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
515 if (ret)
516 return ret;
517
518 return 0;
519 }
520
521 static int rtl8366_smi_write_phy_reg(struct rtl8366s *rtl,
522 u32 phy_no, u32 page, u32 addr, u32 data)
523 {
524 struct rtl8366_smi *smi = &rtl->smi;
525 u32 reg;
526 int ret;
527
528 if (phy_no > RTL8366S_PHY_NO_MAX)
529 return -EINVAL;
530
531 if (page > RTL8366S_PHY_PAGE_MAX)
532 return -EINVAL;
533
534 if (addr > RTL8366S_PHY_ADDR_MAX)
535 return -EINVAL;
536
537 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
538 RTL8366S_PHY_CTRL_WRITE);
539 if (ret)
540 return ret;
541
542 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
543 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
544 (addr & RTL8366S_PHY_REG_MASK);
545
546 ret = rtl8366_smi_write_reg(smi, reg, data);
547 if (ret)
548 return ret;
549
550 return 0;
551 }
552
553 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
554 int port, unsigned long long *val)
555 {
556 struct rtl8366_smi *smi = &rtl->smi;
557 int i;
558 int err;
559 u32 addr, data, regoffset;
560 u64 mibvalue;
561
562 /* address offset to MIBs counter */
563 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
564 2, 2, 2, 2, 2, 2, 2, 2, 2,
565 2, 2, 4, 2, 2, 2, 2, 2, 2,
566 2, 2, 2, 2, 2, 2};
567
568 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
569 return -EINVAL;
570
571 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
572
573 for (i = 0; i < counter; i++)
574 regoffset += mibLength[i];
575
576 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
577
578 /*
579 * Writing access counter address first
580 * then ASIC will prepare 64bits counter wait for being retrived
581 */
582 data = 0; /* writing data will be discard by ASIC */
583 err = rtl8366_smi_write_reg(smi, addr, data);
584 if (err)
585 return err;
586
587 /* read MIB control register */
588 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
589 if (err)
590 return err;
591
592 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
593 return -EBUSY;
594
595 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
596 return -EIO;
597
598 mibvalue = 0;
599 addr = addr + mibLength[counter] - 1;
600 i = mibLength[counter];
601
602 while (i) {
603 err = rtl8366_smi_read_reg(smi, addr, &data);
604 if (err)
605 return err;
606
607 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
608
609 addr--;
610 i--;
611 }
612
613 *val = mibvalue;
614 return 0;
615 }
616
617 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
618 struct rtl8366s_vlan4kentry *vlan4k)
619 {
620 struct rtl8366_smi *smi = &rtl->smi;
621 int err;
622 u32 data;
623 u16 *tableaddr;
624
625 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
626 vlan4k->vid = vid;
627
628 if (vid >= RTL8366_NUM_VIDS)
629 return -EINVAL;
630
631 tableaddr = (u16 *)vlan4k;
632
633 /* write VID */
634 data = *tableaddr;
635 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
636 if (err)
637 return err;
638
639 /* write table access control word */
640 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
641 RTL8366S_TABLE_VLAN_READ_CTRL);
642 if (err)
643 return err;
644
645 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
646 if (err)
647 return err;
648
649 *tableaddr = data;
650 tableaddr++;
651
652 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
653 &data);
654 if (err)
655 return err;
656
657 *tableaddr = data;
658 vlan4k->vid = vid;
659
660 return 0;
661 }
662
663 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
664 const struct rtl8366s_vlan4kentry *vlan4k)
665 {
666 struct rtl8366_smi *smi = &rtl->smi;
667 int err;
668 u32 data;
669 u16 *tableaddr;
670
671 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
672 vlan4k->member > RTL8366_PORT_ALL ||
673 vlan4k->untag > RTL8366_PORT_ALL ||
674 vlan4k->fid > RTL8366S_FIDMAX)
675 return -EINVAL;
676
677 tableaddr = (u16 *)vlan4k;
678
679 data = *tableaddr;
680
681 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
682 if (err)
683 return err;
684
685 tableaddr++;
686
687 data = *tableaddr;
688
689 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
690 data);
691 if (err)
692 return err;
693
694 /* write table access control word */
695 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
696 RTL8366S_TABLE_VLAN_WRITE_CTRL);
697
698 return err;
699 }
700
701 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
702 struct rtl8366s_vlanconfig *vlanmc)
703 {
704 struct rtl8366_smi *smi = &rtl->smi;
705 int err;
706 u32 addr;
707 u32 data;
708 u16 *tableaddr;
709
710 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
711
712 if (index >= RTL8366_NUM_VLANS)
713 return -EINVAL;
714
715 tableaddr = (u16 *)vlanmc;
716
717 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
718 err = rtl8366_smi_read_reg(smi, addr, &data);
719 if (err)
720 return err;
721
722 *tableaddr = data;
723 tableaddr++;
724
725 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
726 err = rtl8366_smi_read_reg(smi, addr, &data);
727 if (err)
728 return err;
729
730 *tableaddr = data;
731
732 return 0;
733 }
734
735 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
736 const struct rtl8366s_vlanconfig
737 *vlanmc)
738 {
739 struct rtl8366_smi *smi = &rtl->smi;
740 int err;
741 u32 addr;
742 u32 data;
743 u16 *tableaddr;
744
745 if (index >= RTL8366_NUM_VLANS ||
746 vlanmc->vid >= RTL8366_NUM_VIDS ||
747 vlanmc->priority > RTL8366S_PRIORITYMAX ||
748 vlanmc->member > RTL8366_PORT_ALL ||
749 vlanmc->untag > RTL8366_PORT_ALL ||
750 vlanmc->fid > RTL8366S_FIDMAX)
751 return -EINVAL;
752
753 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
754
755 tableaddr = (u16 *)vlanmc;
756 data = *tableaddr;
757
758 err = rtl8366_smi_write_reg(smi, addr, data);
759 if (err)
760 return err;
761
762 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
763
764 tableaddr++;
765 data = *tableaddr;
766
767 err = rtl8366_smi_write_reg(smi, addr, data);
768 if (err)
769 return err;
770
771 return 0;
772 }
773
774 static int rtl8366_get_port_vlan_index(struct rtl8366s *rtl, int port,
775 int *val)
776 {
777 struct rtl8366_smi *smi = &rtl->smi;
778 u32 data;
779 int err;
780
781 if (port >= RTL8366_NUM_PORTS)
782 return -EINVAL;
783
784 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
785 &data);
786 if (err)
787 return err;
788
789 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
790 RTL8366S_PORT_VLAN_CTRL_MASK;
791
792 return 0;
793
794 }
795
796 static int rtl8366_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
797 int *val)
798 {
799 struct rtl8366s_vlanconfig vlanmc;
800 int err;
801 int index;
802
803 err = rtl8366_get_port_vlan_index(rtl, port, &index);
804 if (err)
805 return err;
806
807 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
808 if (err)
809 return err;
810
811 *val = vlanmc.vid;
812 return 0;
813 }
814
815 static int rtl8366_set_port_vlan_index(struct rtl8366s *rtl, int port,
816 int index)
817 {
818 struct rtl8366_smi *smi = &rtl->smi;
819 u32 data;
820 int err;
821
822 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
823 return -EINVAL;
824
825 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
826 &data);
827 if (err)
828 return err;
829
830 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
831 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
832 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
833 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
834
835 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
836 data);
837 return err;
838 }
839
840 static int rtl8366_set_vlan_port_pvid(struct rtl8366s *rtl, int port,
841 int val)
842 {
843 int i;
844 struct rtl8366s_vlanconfig vlanmc;
845 struct rtl8366s_vlan4kentry vlan4k;
846
847 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
848 return -EINVAL;
849
850 /* Updating the 4K entry; lookup it and change the port member set */
851 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
852 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
853 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
854 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
855
856 /*
857 * For the 16 entries more work needs to be done. First see if such
858 * VID is already there and change it
859 */
860 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
861 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
862
863 /* Try to find an existing vid and update port member set */
864 if (val == vlanmc.vid) {
865 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
866 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
867
868 /* Now update PVID register settings */
869 rtl8366_set_port_vlan_index(rtl, port, i);
870
871 return 0;
872 }
873 }
874
875 /*
876 * PVID could not be found from vlan table. Replace unused (one that
877 * has no member ports) with new one
878 */
879 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
880 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
881
882 /*
883 * See if this vlan member configuration is unused. It is
884 * unused if member set contains no ports or CPU port only
885 */
886 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
887 vlanmc.vid = val;
888 vlanmc.priority = 0;
889 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
890 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
891 vlanmc.fid = 0;
892
893 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
894
895 /* Now update PVID register settings */
896 rtl8366_set_port_vlan_index(rtl, port, i);
897
898 return 0;
899 }
900 }
901
902 dev_err(rtl->parent,
903 "All 16 vlan member configurations are in use\n");
904
905 return -EINVAL;
906 }
907
908
909 static int rtl8366_vlan_set_vlan(struct rtl8366s *rtl, int enable)
910 {
911 struct rtl8366_smi *smi = &rtl->smi;
912 u32 data = 0;
913
914 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
915
916 if (enable)
917 data |= RTL8366_CHIP_CTRL_VLAN;
918 else
919 data &= ~RTL8366_CHIP_CTRL_VLAN;
920
921 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
922 }
923
924 static int rtl8366_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
925 {
926 struct rtl8366_smi *smi = &rtl->smi;
927 u32 data = 0;
928
929 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
930
931 if (enable)
932 data |= 1;
933 else
934 data &= ~1;
935
936 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
937 }
938
939 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
940 {
941 struct rtl8366s_vlan4kentry vlan4k;
942 struct rtl8366s_vlanconfig vlanmc;
943 int err;
944 int i;
945
946 /* clear 16 VLAN member configuration */
947 vlanmc.vid = 0;
948 vlanmc.priority = 0;
949 vlanmc.member = 0;
950 vlanmc.untag = 0;
951 vlanmc.fid = 0;
952 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
953 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
954 if (err)
955 return err;
956 }
957
958 /* Set a default VLAN with vid 1 to 4K table for all ports */
959 vlan4k.vid = 1;
960 vlan4k.member = RTL8366_PORT_ALL;
961 vlan4k.untag = RTL8366_PORT_ALL;
962 vlan4k.fid = 0;
963 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
964 if (err)
965 return err;
966
967 /* Set all ports PVID to default VLAN */
968 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
969 err = rtl8366_set_vlan_port_pvid(rtl, i, 0);
970 if (err)
971 return err;
972 }
973
974 return 0;
975 }
976
977 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
978 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
979 {
980 file->private_data = inode->i_private;
981 return 0;
982 }
983
984 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
985 char __user *user_buf,
986 size_t count, loff_t *ppos)
987 {
988 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
989 int i, j, len = 0;
990 char *buf = rtl->buf;
991
992 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
993 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
994 " "
995 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
996 "Port 4\n");
997
998 for (i = 0; i < 33; ++i) {
999 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
1000 i, MIBCOUNTERS[i]);
1001 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1002 unsigned long long counter = 0;
1003
1004 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
1005 len += snprintf(buf + len,
1006 sizeof(rtl->buf) - len,
1007 "[%llu]", counter);
1008 else
1009 len += snprintf(buf + len,
1010 sizeof(rtl->buf) - len,
1011 "[error]");
1012
1013 if (j != RTL8366_NUM_PORTS - 1) {
1014 if (counter < 100000)
1015 len += snprintf(buf + len,
1016 sizeof(rtl->buf) - len,
1017 "\t");
1018
1019 len += snprintf(buf + len,
1020 sizeof(rtl->buf) - len,
1021 "\t");
1022 }
1023 }
1024 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1025 }
1026
1027 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1028
1029 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1030 }
1031
1032 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1033 char __user *user_buf,
1034 size_t count, loff_t *ppos)
1035 {
1036 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1037 int i, j, len = 0;
1038 char *buf = rtl->buf;
1039
1040 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1041 "VLAN Member Config:\n");
1042 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1043 "\t id \t vid \t prio \t member \t untag \t fid "
1044 "\tports\n");
1045
1046 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1047 struct rtl8366s_vlanconfig vlanmc;
1048
1049 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
1050
1051 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1052 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1053 "\t", i, vlanmc.vid, vlanmc.priority,
1054 vlanmc.member, vlanmc.untag, vlanmc.fid);
1055
1056 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1057 int index = 0;
1058 if (!rtl8366_get_port_vlan_index(rtl, j, &index)) {
1059 if (index == i)
1060 len += snprintf(buf + len,
1061 sizeof(rtl->buf) - len,
1062 "%d", j);
1063 }
1064 }
1065 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1066 }
1067
1068 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1069 }
1070
1071 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1072 char __user *user_buf,
1073 size_t count, loff_t *ppos)
1074 {
1075 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1076 struct rtl8366_smi *smi = &rtl->smi;
1077 u32 t, reg = g_dbg_reg;
1078 int err, len = 0;
1079 char *buf = rtl->buf;
1080
1081 memset(buf, '\0', sizeof(rtl->buf));
1082
1083 err = rtl8366_smi_read_reg(smi, reg, &t);
1084 if (err) {
1085 len += snprintf(buf, sizeof(rtl->buf),
1086 "Read failed (reg: 0x%04x)\n", reg);
1087 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1088 }
1089
1090 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
1091 reg, t);
1092
1093 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1094 }
1095
1096 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1097 const char __user *user_buf,
1098 size_t count, loff_t *ppos)
1099 {
1100 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
1101 struct rtl8366_smi *smi = &rtl->smi;
1102 unsigned long data;
1103 u32 reg = g_dbg_reg;
1104 int err;
1105 size_t len;
1106 char *buf = rtl->buf;
1107
1108 len = min(count, sizeof(rtl->buf) - 1);
1109 if (copy_from_user(buf, user_buf, len)) {
1110 dev_err(rtl->parent, "copy from user failed\n");
1111 return -EFAULT;
1112 }
1113
1114 buf[len] = '\0';
1115 if (len > 0 && buf[len - 1] == '\n')
1116 buf[len - 1] = '\0';
1117
1118
1119 if (strict_strtoul(buf, 16, &data)) {
1120 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
1121 } else {
1122 err = rtl8366_smi_write_reg(smi, reg, data);
1123 if (err) {
1124 dev_err(rtl->parent,
1125 "writing reg 0x%04x val 0x%04lx failed\n",
1126 reg, data);
1127 }
1128 }
1129
1130 return count;
1131 }
1132
1133 static const struct file_operations fops_rtl8366_regs = {
1134 .read = rtl8366_read_debugfs_reg,
1135 .write = rtl8366_write_debugfs_reg,
1136 .open = rtl8366_debugfs_open,
1137 .owner = THIS_MODULE
1138 };
1139
1140 static const struct file_operations fops_rtl8366_vlan = {
1141 .read = rtl8366_read_debugfs_vlan,
1142 .open = rtl8366_debugfs_open,
1143 .owner = THIS_MODULE
1144 };
1145
1146 static const struct file_operations fops_rtl8366_mibs = {
1147 .read = rtl8366_read_debugfs_mibs,
1148 .open = rtl8366_debugfs_open,
1149 .owner = THIS_MODULE
1150 };
1151
1152 static void rtl8366_debugfs_init(struct rtl8366s *rtl)
1153 {
1154 struct dentry *node;
1155 struct dentry *root;
1156
1157 if (!rtl->debugfs_root)
1158 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1159
1160 if (!rtl->debugfs_root) {
1161 dev_err(rtl->parent, "Unable to create debugfs dir\n");
1162 return;
1163 }
1164 root = rtl->debugfs_root;
1165
1166 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1167 if (!node) {
1168 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
1169 return;
1170 }
1171
1172 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1173 &fops_rtl8366_regs);
1174 if (!node) {
1175 dev_err(rtl->parent, "Creating debugfs file val failed\n");
1176 return;
1177 }
1178
1179 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
1180 &fops_rtl8366_vlan);
1181 if (!node) {
1182 dev_err(rtl->parent,
1183 "Creating debugfs file vlan failed\n");
1184 return;
1185 }
1186
1187 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1188 &fops_rtl8366_mibs);
1189 if (!node) {
1190 dev_err(rtl->parent,
1191 "Creating debugfs file mibs failed\n");
1192 return;
1193 }
1194 }
1195
1196 static void rtl8366_debugfs_remove(struct rtl8366s *rtl)
1197 {
1198 if (rtl->debugfs_root) {
1199 debugfs_remove_recursive(rtl->debugfs_root);
1200 rtl->debugfs_root = NULL;
1201 }
1202 }
1203
1204 #else
1205 static inline void rtl8366_debugfs_init(struct rtl8366s *rtl) {}
1206 static inline void rtl8366_debugfs_remove(struct rtl8366s *rtl) {}
1207 #endif /* CONFIG_RTL8366_SMI_DEBUG_FS */
1208
1209 static int rtl8366_sw_reset_mibs(struct switch_dev *dev,
1210 const struct switch_attr *attr,
1211 struct switch_val *val)
1212 {
1213 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1214 struct rtl8366_smi *smi = &rtl->smi;
1215 u32 data = 0;
1216
1217 if (val->value.i == 1) {
1218 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1219 data |= (1 << 2);
1220 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1221 }
1222
1223 return 0;
1224 }
1225
1226 static int rtl8366_sw_get_vlan_enable(struct switch_dev *dev,
1227 const struct switch_attr *attr,
1228 struct switch_val *val)
1229 {
1230 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1231 struct rtl8366_smi *smi = &rtl->smi;
1232 u32 data;
1233
1234 if (attr->ofs == 1) {
1235 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1236
1237 if (data & RTL8366_CHIP_CTRL_VLAN)
1238 val->value.i = 1;
1239 else
1240 val->value.i = 0;
1241 } else if (attr->ofs == 2) {
1242 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1243
1244 if (data & 0x0001)
1245 val->value.i = 1;
1246 else
1247 val->value.i = 0;
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int rtl8366_sw_get_blinkrate(struct switch_dev *dev,
1254 const struct switch_attr *attr,
1255 struct switch_val *val)
1256 {
1257 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1258 struct rtl8366_smi *smi = &rtl->smi;
1259 u32 data;
1260
1261 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1262
1263 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1264
1265 return 0;
1266 }
1267
1268 static int rtl8366_sw_set_blinkrate(struct switch_dev *dev,
1269 const struct switch_attr *attr,
1270 struct switch_val *val)
1271 {
1272 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1273 struct rtl8366_smi *smi = &rtl->smi;
1274 u32 data;
1275
1276 if (val->value.i >= 6)
1277 return -EINVAL;
1278
1279 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1280
1281 data &= ~RTL8366_LED_BLINKRATE_MASK;
1282 data |= val->value.i;
1283
1284 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1285
1286 return 0;
1287 }
1288
1289 static int rtl8366_sw_set_vlan_enable(struct switch_dev *dev,
1290 const struct switch_attr *attr,
1291 struct switch_val *val)
1292 {
1293 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1294
1295 if (attr->ofs == 1)
1296 return rtl8366_vlan_set_vlan(rtl, val->value.i);
1297 else
1298 return rtl8366_vlan_set_4ktable(rtl, val->value.i);
1299 }
1300
1301 static const char *rtl8366_speed_str(unsigned speed)
1302 {
1303 switch (speed) {
1304 case 0:
1305 return "10baseT";
1306 case 1:
1307 return "100baseT";
1308 case 2:
1309 return "1000baseT";
1310 }
1311
1312 return "unknown";
1313 }
1314
1315 static int rtl8366_sw_get_port_link(struct switch_dev *dev,
1316 const struct switch_attr *attr,
1317 struct switch_val *val)
1318 {
1319 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1320 struct rtl8366_smi *smi = &rtl->smi;
1321 u32 len = 0, data = 0;
1322
1323 if (val->port_vlan >= RTL8366_NUM_PORTS)
1324 return -EINVAL;
1325
1326 memset(rtl->buf, '\0', sizeof(rtl->buf));
1327 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1328 (val->port_vlan / 2), &data);
1329
1330 if (val->port_vlan % 2)
1331 data = data >> 8;
1332
1333 len = snprintf(rtl->buf, sizeof(rtl->buf),
1334 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1335 val->port_vlan,
1336 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1337 rtl8366_speed_str(data &
1338 RTL8366S_PORT_STATUS_SPEED_MASK),
1339 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1340 "full" : "half",
1341 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1342 "tx-pause ": "",
1343 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1344 "rx-pause " : "",
1345 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1346
1347 val->value.s = rtl->buf;
1348 val->len = len;
1349
1350 return 0;
1351 }
1352
1353 static int rtl8366_sw_get_vlan_info(struct switch_dev *dev,
1354 const struct switch_attr *attr,
1355 struct switch_val *val)
1356 {
1357 int i;
1358 u32 len = 0;
1359 struct rtl8366s_vlanconfig vlanmc;
1360 struct rtl8366s_vlan4kentry vlan4k;
1361 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1362 char *buf = rtl->buf;
1363
1364 if (val->port_vlan >= RTL8366_NUM_VLANS)
1365 return -EINVAL;
1366
1367 memset(buf, '\0', sizeof(rtl->buf));
1368
1369 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1370 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1371
1372 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1373 val->port_vlan);
1374
1375 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1376 int index = 0;
1377 if (!rtl8366_get_port_vlan_index(rtl, i, &index) &&
1378 index == val->port_vlan)
1379 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1380 "%d", i);
1381 }
1382 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1383
1384 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1385 "\t\t vid \t prio \t member \t untag \t fid\n");
1386 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1387 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1388 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1389 vlanmc.vid, vlanmc.priority, vlanmc.member,
1390 vlanmc.untag, vlanmc.fid);
1391 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1392 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1393 "%d \t \t 0x%04x \t 0x%04x \t %d",
1394 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1395
1396 val->value.s = buf;
1397 val->len = len;
1398
1399 return 0;
1400 }
1401
1402 static int rtl8366_sw_set_port_led(struct switch_dev *dev,
1403 const struct switch_attr *attr,
1404 struct switch_val *val)
1405 {
1406 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1407 struct rtl8366_smi *smi = &rtl->smi;
1408 u32 data = 0;
1409
1410 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1411 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1412 return -EINVAL;
1413
1414 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1415 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1416 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1417 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1418 } else {
1419 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1420 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1421 (val->value.i << (val->port_vlan * 4));
1422 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1423 }
1424
1425 return 0;
1426 }
1427
1428 static int rtl8366_sw_get_port_led(struct switch_dev *dev,
1429 const struct switch_attr *attr,
1430 struct switch_val *val)
1431 {
1432 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1433 struct rtl8366_smi *smi = &rtl->smi;
1434 u32 data = 0;
1435
1436 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1437 return -EINVAL;
1438
1439 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1440 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1441
1442 return 0;
1443 }
1444
1445 static int rtl8366_sw_reset_port_mibs(struct switch_dev *dev,
1446 const struct switch_attr *attr,
1447 struct switch_val *val)
1448 {
1449 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1450 struct rtl8366_smi *smi = &rtl->smi;
1451 u32 data = 0;
1452
1453 if (val->port_vlan >= RTL8366_NUM_PORTS)
1454 return -EINVAL;
1455
1456 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1457 data |= (1 << (val->port_vlan + 3));
1458 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1459
1460 return 0;
1461 }
1462
1463 static int rtl8366_sw_get_port_mib(struct switch_dev *dev,
1464 const struct switch_attr *attr,
1465 struct switch_val *val)
1466 {
1467 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1468 int i, len = 0;
1469 unsigned long long counter = 0;
1470 char *buf = rtl->buf;
1471
1472 if (val->port_vlan >= RTL8366_NUM_PORTS)
1473 return -EINVAL;
1474
1475 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1476 "Port %d MIB counters\n",
1477 val->port_vlan);
1478
1479 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1480 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1481 "%d:%s\t", i, MIBCOUNTERS[i]);
1482 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1483 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1484 "[%llu]\n", counter);
1485 else
1486 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1487 "[error]\n");
1488 }
1489
1490 val->value.s = buf;
1491 val->len = len;
1492 return 0;
1493 }
1494
1495 static int rtl8366_sw_get_vlan_ports(struct switch_dev *dev,
1496 struct switch_val *val)
1497 {
1498 struct rtl8366s_vlanconfig vlanmc;
1499 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1500 struct switch_port *port;
1501 int i;
1502
1503 if (val->port_vlan >= RTL8366_NUM_VLANS)
1504 return -EINVAL;
1505
1506 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1507
1508 port = &val->value.ports[0];
1509 val->len = 0;
1510 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1511 if (!(vlanmc.member & BIT(i)))
1512 continue;
1513
1514 port->id = i;
1515 port->flags = (vlanmc.untag & BIT(i)) ?
1516 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1517 val->len++;
1518 port++;
1519 }
1520 return 0;
1521 }
1522
1523 static int rtl8366_sw_set_vlan_ports(struct switch_dev *dev,
1524 struct switch_val *val)
1525 {
1526 struct rtl8366s_vlanconfig vlanmc;
1527 struct rtl8366s_vlan4kentry vlan4k;
1528 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1529 struct switch_port *port;
1530 int i;
1531
1532 if (val->port_vlan >= RTL8366_NUM_VLANS)
1533 return -EINVAL;
1534
1535 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1536 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1537
1538 vlanmc.untag = 0;
1539 vlanmc.member = 0;
1540
1541 port = &val->value.ports[0];
1542 for (i = 0; i < val->len; i++, port++) {
1543 vlanmc.member |= BIT(port->id);
1544
1545 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1546 vlanmc.untag |= BIT(port->id);
1547 }
1548
1549 vlan4k.member = vlanmc.member;
1550 vlan4k.untag = vlanmc.untag;
1551
1552 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1553 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1554 return 0;
1555 }
1556
1557 static int rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1558 {
1559 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1560 return rtl8366_get_vlan_port_pvid(rtl, port, val);
1561 }
1562
1563 static int rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1564 {
1565 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1566 return rtl8366_set_vlan_port_pvid(rtl, port, val);
1567 }
1568
1569 static int rtl8366_sw_reset_switch(struct switch_dev *dev)
1570 {
1571 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1572 struct rtl8366_smi *smi = &rtl->smi;
1573 int timeout = 10;
1574 u32 data;
1575
1576 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1577 RTL8366_CHIP_CTRL_RESET_HW);
1578 do {
1579 msleep(1);
1580 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1581 return -EIO;
1582
1583 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1584 break;
1585 } while (--timeout);
1586
1587 if (!timeout) {
1588 printk("Timeout waiting for the switch to reset\n");
1589 return -EIO;
1590 }
1591
1592 return rtl8366s_reset_vlan(rtl);
1593 }
1594
1595 static struct switch_attr rtl8366_globals[] = {
1596 {
1597 .type = SWITCH_TYPE_INT,
1598 .name = "enable_vlan",
1599 .description = "Enable VLAN mode",
1600 .set = rtl8366_sw_set_vlan_enable,
1601 .get = rtl8366_sw_get_vlan_enable,
1602 .max = 1,
1603 .ofs = 1
1604 }, {
1605 .type = SWITCH_TYPE_INT,
1606 .name = "enable_vlan4k",
1607 .description = "Enable VLAN 4K mode",
1608 .set = rtl8366_sw_set_vlan_enable,
1609 .get = rtl8366_sw_get_vlan_enable,
1610 .max = 1,
1611 .ofs = 2
1612 }, {
1613 .type = SWITCH_TYPE_INT,
1614 .name = "reset_mibs",
1615 .description = "Reset all MIB counters",
1616 .set = rtl8366_sw_reset_mibs,
1617 .get = NULL,
1618 .max = 1
1619 }, {
1620 .type = SWITCH_TYPE_INT,
1621 .name = "blinkrate",
1622 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1623 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1624 .set = rtl8366_sw_set_blinkrate,
1625 .get = rtl8366_sw_get_blinkrate,
1626 .max = 5
1627 },
1628 };
1629
1630 static struct switch_attr rtl8366_port[] = {
1631 {
1632 .type = SWITCH_TYPE_STRING,
1633 .name = "link",
1634 .description = "Get port link information",
1635 .max = 1,
1636 .set = NULL,
1637 .get = rtl8366_sw_get_port_link,
1638 }, {
1639 .type = SWITCH_TYPE_INT,
1640 .name = "reset_mib",
1641 .description = "Reset single port MIB counters",
1642 .max = 1,
1643 .set = rtl8366_sw_reset_port_mibs,
1644 .get = NULL,
1645 }, {
1646 .type = SWITCH_TYPE_STRING,
1647 .name = "mib",
1648 .description = "Get MIB counters for port",
1649 .max = 33,
1650 .set = NULL,
1651 .get = rtl8366_sw_get_port_mib,
1652 }, {
1653 .type = SWITCH_TYPE_INT,
1654 .name = "led",
1655 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1656 .max = 15,
1657 .set = rtl8366_sw_set_port_led,
1658 .get = rtl8366_sw_get_port_led,
1659 },
1660 };
1661
1662 static struct switch_attr rtl8366_vlan[] = {
1663 {
1664 .type = SWITCH_TYPE_STRING,
1665 .name = "info",
1666 .description = "Get vlan information",
1667 .max = 1,
1668 .set = NULL,
1669 .get = rtl8366_sw_get_vlan_info,
1670 },
1671 };
1672
1673
1674 /* template */
1675 static struct switch_dev rtldev = {
1676 .name = "RTL8366S",
1677 .cpu_port = RTL8366_PORT_NUM_CPU,
1678 .ports = RTL8366_NUM_PORTS,
1679 .vlans = RTL8366_NUM_VLANS,
1680 .attr_global = {
1681 .attr = rtl8366_globals,
1682 .n_attr = ARRAY_SIZE(rtl8366_globals),
1683 },
1684 .attr_port = {
1685 .attr = rtl8366_port,
1686 .n_attr = ARRAY_SIZE(rtl8366_port),
1687 },
1688 .attr_vlan = {
1689 .attr = rtl8366_vlan,
1690 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1691 },
1692
1693 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1694 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1695 .get_port_pvid = rtl8366_sw_get_port_pvid,
1696 .set_port_pvid = rtl8366_sw_set_port_pvid,
1697 .reset_switch = rtl8366_sw_reset_switch,
1698 };
1699
1700 static int rtl8366_smi_switch_init(struct rtl8366s *rtl)
1701 {
1702 struct switch_dev *dev = &rtl->dev;
1703 int err;
1704
1705 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1706 dev->priv = rtl;
1707 dev->devname = dev_name(rtl->parent);
1708
1709 err = register_switch(dev, NULL);
1710 if (err)
1711 dev_err(rtl->parent, "switch registration failed\n");
1712
1713 return err;
1714 }
1715
1716 static void rtl8366_smi_switch_cleanup(struct rtl8366s *rtl)
1717 {
1718 unregister_switch(&rtl->dev);
1719 }
1720
1721 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1722 {
1723 struct rtl8366s *rtl = bus->priv;
1724 u32 val = 0;
1725 int err;
1726
1727 err = rtl8366_smi_read_phy_reg(rtl, addr, 0, reg, &val);
1728 if (err)
1729 return 0xffff;
1730
1731 return val;
1732 }
1733
1734 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1735 u16 val)
1736 {
1737 struct rtl8366s *rtl = bus->priv;
1738 u32 t;
1739 int err;
1740
1741 err = rtl8366_smi_write_phy_reg(rtl, addr, 0, reg, val);
1742 /* flush write */
1743 (void) rtl8366_smi_read_phy_reg(rtl, addr, 0, reg, &t);
1744
1745 return err;
1746 }
1747
1748 static int rtl8366_smi_mii_init(struct rtl8366s *rtl)
1749 {
1750 int ret;
1751 int i;
1752
1753 rtl->mii_bus = mdiobus_alloc();
1754 if (rtl->mii_bus == NULL) {
1755 ret = -ENOMEM;
1756 goto err;
1757 }
1758
1759 rtl->mii_bus->priv = (void *) rtl;
1760 rtl->mii_bus->name = "rtl8366-rtl";
1761 rtl->mii_bus->read = rtl8366_smi_mii_read;
1762 rtl->mii_bus->write = rtl8366_smi_mii_write;
1763 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1764 dev_name(rtl->parent));
1765 rtl->mii_bus->parent = rtl->parent;
1766 rtl->mii_bus->phy_mask = ~(0x1f);
1767 rtl->mii_bus->irq = rtl->mii_irq;
1768 for (i = 0; i < PHY_MAX_ADDR; i++)
1769 rtl->mii_irq[i] = PHY_POLL;
1770
1771 ret = mdiobus_register(rtl->mii_bus);
1772 if (ret)
1773 goto err_free;
1774
1775 return 0;
1776
1777 err_free:
1778 mdiobus_free(rtl->mii_bus);
1779 err:
1780 return ret;
1781 }
1782
1783 static void rtl8366_smi_mii_cleanup(struct rtl8366s *rtl)
1784 {
1785 mdiobus_unregister(rtl->mii_bus);
1786 mdiobus_free(rtl->mii_bus);
1787 }
1788
1789 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1790 {
1791 return (bus->read == rtl8366_smi_mii_read &&
1792 bus->write == rtl8366_smi_mii_write);
1793 }
1794
1795 static int rtl8366_smi_setup(struct rtl8366s *rtl)
1796 {
1797 struct rtl8366_smi *smi = &rtl->smi;
1798 u32 chip_id = 0;
1799 u32 chip_ver = 0;
1800 int ret;
1801
1802 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1803 if (ret) {
1804 dev_err(rtl->parent, "unable to read chip id\n");
1805 return ret;
1806 }
1807
1808 switch (chip_id) {
1809 case RTL8366S_CHIP_ID_8366:
1810 break;
1811 default:
1812 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1813 return -ENODEV;
1814 }
1815
1816 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1817 &chip_ver);
1818 if (ret) {
1819 dev_err(rtl->parent, "unable to read chip version\n");
1820 return ret;
1821 }
1822
1823 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1824 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1825
1826 rtl8366_debugfs_init(rtl);
1827
1828 return 0;
1829 }
1830
1831 static int __init rtl8366_smi_init(struct rtl8366_smi *smi)
1832 {
1833 int err;
1834
1835 if (!smi->parent)
1836 return -EINVAL;
1837
1838 err = gpio_request(smi->gpio_sda, dev_name(smi->parent));
1839 if (err) {
1840 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1841 smi->gpio_sda, err);
1842 goto err_out;
1843 }
1844
1845 err = gpio_request(smi->gpio_sck, dev_name(smi->parent));
1846 if (err) {
1847 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1848 smi->gpio_sck, err);
1849 goto err_free_sda;
1850 }
1851
1852 spin_lock_init(&smi->lock);
1853
1854 dev_info(smi->parent, "using GPIO pins %u (SDA) and %u (SCK)\n",
1855 smi->gpio_sda, smi->gpio_sck);
1856
1857 return 0;
1858
1859 err_free_sda:
1860 gpio_free(smi->gpio_sda);
1861 err_out:
1862 return err;
1863 }
1864
1865 static void rtl8366_smi_cleanup(struct rtl8366_smi *smi)
1866 {
1867 gpio_free(smi->gpio_sck);
1868 gpio_free(smi->gpio_sda);
1869 }
1870
1871 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1872 {
1873 static int rtl8366_smi_version_printed;
1874 struct rtl8366_smi_platform_data *pdata;
1875 struct rtl8366s *rtl;
1876 struct rtl8366_smi *smi;
1877 int err;
1878
1879 if (!rtl8366_smi_version_printed++)
1880 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1881 " version " RTL8366_SMI_DRIVER_VER"\n");
1882
1883 pdata = pdev->dev.platform_data;
1884 if (!pdata) {
1885 dev_err(&pdev->dev, "no platform data specified\n");
1886 err = -EINVAL;
1887 goto err_out;
1888 }
1889
1890 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1891 if (!rtl) {
1892 dev_err(&pdev->dev, "no memory for private data\n");
1893 err = -ENOMEM;
1894 goto err_out;
1895 }
1896
1897 rtl->parent = &pdev->dev;
1898
1899 smi = &rtl->smi;
1900 smi->parent = &pdev->dev;
1901 smi->gpio_sda = pdata->gpio_sda;
1902 smi->gpio_sck = pdata->gpio_sck;
1903
1904 err = rtl8366_smi_init(smi);
1905 if (err)
1906 goto err_free_rtl;
1907
1908 platform_set_drvdata(pdev, rtl);
1909
1910 err = rtl8366_smi_setup(rtl);
1911 if (err)
1912 goto err_clear_drvdata;
1913
1914 err = rtl8366_smi_mii_init(rtl);
1915 if (err)
1916 goto err_clear_drvdata;
1917
1918 err = rtl8366_smi_switch_init(rtl);
1919 if (err)
1920 goto err_mii_cleanup;
1921
1922 return 0;
1923
1924 err_mii_cleanup:
1925 rtl8366_smi_mii_cleanup(rtl);
1926 err_clear_drvdata:
1927 platform_set_drvdata(pdev, NULL);
1928 rtl8366_smi_cleanup(smi);
1929 err_free_rtl:
1930 kfree(rtl);
1931 err_out:
1932 return err;
1933 }
1934
1935 static int rtl8366_phy_config_init(struct phy_device *phydev)
1936 {
1937 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1938 return -EINVAL;
1939
1940 return 0;
1941 }
1942
1943 static int rtl8366_phy_config_aneg(struct phy_device *phydev)
1944 {
1945 return 0;
1946 }
1947
1948 static struct phy_driver rtl8366_smi_phy_driver = {
1949 .phy_id = 0x001cc960,
1950 .name = "Realtek RTL8366",
1951 .phy_id_mask = 0x1ffffff0,
1952 .features = PHY_GBIT_FEATURES,
1953 .config_aneg = rtl8366_phy_config_aneg,
1954 .config_init = rtl8366_phy_config_init,
1955 .read_status = genphy_read_status,
1956 .driver = {
1957 .owner = THIS_MODULE,
1958 },
1959 };
1960
1961 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1962 {
1963 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1964
1965 if (rtl) {
1966 rtl8366_smi_switch_cleanup(rtl);
1967 rtl8366_debugfs_remove(rtl);
1968 rtl8366_smi_mii_cleanup(rtl);
1969 platform_set_drvdata(pdev, NULL);
1970 rtl8366_smi_cleanup(&rtl->smi);
1971 kfree(rtl);
1972 }
1973
1974 return 0;
1975 }
1976
1977 static struct platform_driver rtl8366_smi_driver = {
1978 .driver = {
1979 .name = RTL8366_SMI_DRIVER_NAME,
1980 .owner = THIS_MODULE,
1981 },
1982 .probe = rtl8366_smi_probe,
1983 .remove = __devexit_p(rtl8366_smi_remove),
1984 };
1985
1986 static int __init rtl8366_smi_module_init(void)
1987 {
1988 int ret;
1989 ret = platform_driver_register(&rtl8366_smi_driver);
1990 if (ret)
1991 return ret;
1992
1993 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1994 if (ret)
1995 goto err_platform_unregister;
1996
1997 return 0;
1998
1999 err_platform_unregister:
2000 platform_driver_unregister(&rtl8366_smi_driver);
2001 return ret;
2002 }
2003 module_init(rtl8366_smi_module_init);
2004
2005 static void __exit rtl8366_smi_exit(void)
2006 {
2007 phy_driver_unregister(&rtl8366_smi_phy_driver);
2008 platform_driver_unregister(&rtl8366_smi_driver);
2009 }
2010 module_exit(rtl8366_smi_exit);
2011
2012 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
2013 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
2014 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2015 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2016 MODULE_LICENSE("GPL v2");
2017 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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