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[openwrt/staging/yousong.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
29 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
30 #define RTL8366_SMI_DRIVER_VER "0.1.1"
31
32 #define RTL8366S_PHY_NO_MAX 4
33 #define RTL8366S_PHY_PAGE_MAX 7
34 #define RTL8366S_PHY_ADDR_MAX 31
35
36 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
37 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
38
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0105
46 #define RTL8366S_CHIP_ID_8366 0x8366
47
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
51
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
54
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60
61 #define RTL8366_SMI_ACK_RETRY_COUNT 5
62 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
63
64 /* LED control registers */
65 #define RTL8366_LED_BLINKRATE_REG 0x0420
66 #define RTL8366_LED_BLINKRATE_BIT 0
67 #define RTL8366_LED_BLINKRATE_MASK 0x0007
68
69 #define RTL8366_LED_CTRL_REG 0x0421
70 #define RTL8366_LED_0_1_CTRL_REG 0x0422
71 #define RTL8366_LED_2_3_CTRL_REG 0x0423
72
73 #define RTL8366S_MIB_COUNT 33
74 #define RTL8366S_GLOBAL_MIB_COUNT 1
75 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
76 #define RTL8366S_MIB_COUNTER_BASE 0x1000
77 #define RTL8366S_MIB_CTRL_REG 0x11F0
78 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
79 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
80 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
81
82 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
83 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
84 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
85
86
87 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
88 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
89 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
90 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
91 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
92
93
94 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
95 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
96
97 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
98
99 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
100 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
101 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
102
103 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
104
105
106 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
107 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
108 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
109 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
110 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
111 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
112 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
113
114
115 #define RTL8366_PORT_NUM_CPU 5
116 #define RTL8366_NUM_PORTS 6
117 #define RTL8366_NUM_VLANS 16
118 #define RTL8366_NUM_LEDGROUPS 4
119 #define RTL8366_NUM_VIDS 4096
120 #define RTL8366S_PRIORITYMAX 7
121 #define RTL8366S_FIDMAX 7
122
123
124 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
125 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
126 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
127 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
128
129 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
130 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
131
132 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
133 RTL8366_PORT_2 | \
134 RTL8366_PORT_3 | \
135 RTL8366_PORT_4 | \
136 RTL8366_PORT_UNKNOWN | \
137 RTL8366_PORT_CPU)
138
139 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
140 RTL8366_PORT_2 | \
141 RTL8366_PORT_3 | \
142 RTL8366_PORT_4 | \
143 RTL8366_PORT_UNKNOWN)
144
145 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 RTL8366_PORT_2 | \
147 RTL8366_PORT_3 | \
148 RTL8366_PORT_4)
149
150 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
151 RTL8366_PORT_CPU)
152
153 struct rtl8366s_vlanconfig {
154 u16 reserved2:1;
155 u16 priority:3;
156 u16 vid:12;
157
158 u16 reserved1:1;
159 u16 fid:3;
160 u16 untag:6;
161 u16 member:6;
162 };
163
164 struct rtl8366s_vlan4kentry {
165 u16 reserved1:4;
166 u16 vid:12;
167
168 u16 reserved2:1;
169 u16 fid:3;
170 u16 untag:6;
171 u16 member:6;
172 };
173
174 static const char *MIBCOUNTERS[] = {
175 "IfInOctets ",
176 "EtherStatsOctets ",
177 "EtherStatsUnderSizePkts ",
178 "EtherFregament ",
179 "EtherStatsPkts64Octets ",
180 "EtherStatsPkts65to127Octets ",
181 "EtherStatsPkts128to255Octets ",
182 "EtherStatsPkts256to511Octets ",
183 "EtherStatsPkts512to1023Octets ",
184 "EtherStatsPkts1024to1518Octets ",
185 "EtherOversizeStats ",
186 "EtherStatsJabbers ",
187 "IfInUcastPkts ",
188 "EtherStatsMulticastPkts ",
189 "EtherStatsBroadcastPkts ",
190 "EtherStatsDropEvents ",
191 "Dot3StatsFCSErrors ",
192 "Dot3StatsSymbolErrors ",
193 "Dot3InPauseFrames ",
194 "Dot3ControlInUnknownOpcodes ",
195 "IfOutOctets ",
196 "Dot3StatsSingleCollisionFrames ",
197 "Dot3StatMultipleCollisionFrames ",
198 "Dot3sDeferredTransmissions ",
199 "Dot3StatsLateCollisions ",
200 "EtherStatsCollisions ",
201 "Dot3StatsExcessiveCollisions ",
202 "Dot3OutPauseFrames ",
203 "Dot1dBasePortDelayExceededDiscards",
204 "Dot1dTpPortInDiscards ",
205 "IfOutUcastPkts ",
206 "IfOutMulticastPkts ",
207 "IfOutBroadcastPkts ",
208 NULL,
209 };
210
211 struct rtl8366_smi {
212 struct device *parent;
213 unsigned int gpio_sda;
214 unsigned int gpio_sck;
215 spinlock_t lock;
216 struct mii_bus *mii_bus;
217 struct switch_dev dev;
218 int mii_irq[PHY_MAX_ADDR];
219 char buf[4096];
220 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
221 struct dentry *debugfs_root;
222 #endif
223 };
224
225 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
226 u16 g_dbg_reg;
227 #endif
228
229 static inline struct rtl8366_smi *sw_to_rtl8366(struct switch_dev *sw)
230 {
231 return container_of(sw, struct rtl8366_smi, dev);
232 }
233
234 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
235 {
236 ndelay(RTL8366_SMI_CLK_DELAY);
237 }
238
239 static void rtl8366_smi_start(struct rtl8366_smi *smi)
240 {
241 unsigned int sda = smi->gpio_sda;
242 unsigned int sck = smi->gpio_sck;
243
244 /*
245 * Set GPIO pins to output mode, with initial state:
246 * SCK = 0, SDA = 1
247 */
248 gpio_direction_output(sck, 0);
249 gpio_direction_output(sda, 1);
250 rtl8366_smi_clk_delay(smi);
251
252 /* CLK 1: 0 -> 1, 1 -> 0 */
253 gpio_set_value(sck, 1);
254 rtl8366_smi_clk_delay(smi);
255 gpio_set_value(sck, 0);
256 rtl8366_smi_clk_delay(smi);
257
258 /* CLK 2: */
259 gpio_set_value(sck, 1);
260 rtl8366_smi_clk_delay(smi);
261 gpio_set_value(sda, 0);
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sck, 0);
264 rtl8366_smi_clk_delay(smi);
265 gpio_set_value(sda, 1);
266 }
267
268 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
269 {
270 unsigned int sda = smi->gpio_sda;
271 unsigned int sck = smi->gpio_sck;
272
273 rtl8366_smi_clk_delay(smi);
274 gpio_set_value(sda, 0);
275 gpio_set_value(sck, 1);
276 rtl8366_smi_clk_delay(smi);
277 gpio_set_value(sda, 1);
278 rtl8366_smi_clk_delay(smi);
279 gpio_set_value(sck, 1);
280 rtl8366_smi_clk_delay(smi);
281 gpio_set_value(sck, 0);
282 rtl8366_smi_clk_delay(smi);
283 gpio_set_value(sck, 1);
284
285 /* add a click */
286 rtl8366_smi_clk_delay(smi);
287 gpio_set_value(sck, 0);
288 rtl8366_smi_clk_delay(smi);
289 gpio_set_value(sck, 1);
290
291 /* set GPIO pins to input mode */
292 gpio_direction_input(sda);
293 gpio_direction_input(sck);
294 }
295
296 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
297 {
298 unsigned int sda = smi->gpio_sda;
299 unsigned int sck = smi->gpio_sck;
300
301 for (; len > 0; len--) {
302 rtl8366_smi_clk_delay(smi);
303
304 /* prepare data */
305 if ( data & ( 1 << (len - 1)) )
306 gpio_set_value(sda, 1);
307 else
308 gpio_set_value(sda, 0);
309 rtl8366_smi_clk_delay(smi);
310
311 /* clocking */
312 gpio_set_value(sck, 1);
313 rtl8366_smi_clk_delay(smi);
314 gpio_set_value(sck, 0);
315 }
316 }
317
318 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
319 {
320 unsigned int sda = smi->gpio_sda;
321 unsigned int sck = smi->gpio_sck;
322
323 gpio_direction_input(sda);
324
325 for (*data = 0; len > 0; len--) {
326 u32 u;
327
328 rtl8366_smi_clk_delay(smi);
329
330 /* clocking */
331 gpio_set_value(sck, 1);
332 rtl8366_smi_clk_delay(smi);
333 u = gpio_get_value(sda);
334 gpio_set_value(sck, 0);
335
336 *data |= (u << (len - 1));
337 }
338
339 gpio_direction_output(sda, 0);
340 }
341
342 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
343 {
344 int retry_cnt;
345
346 retry_cnt = 0;
347 do {
348 u32 ack;
349
350 rtl8366_smi_read_bits(smi, 1, &ack);
351 if (ack == 0)
352 break;
353
354 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
355 return -EIO;
356 } while (1);
357
358 return 0;
359 }
360
361 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
362 {
363 rtl8366_smi_write_bits(smi, data, 8);
364 return rtl8366_smi_wait_for_ack(smi);
365 }
366
367 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
368 {
369 u32 t;
370
371 /* read data */
372 rtl8366_smi_read_bits(smi, 8, &t);
373 *data = (t & 0xff);
374
375 /* send an ACK */
376 rtl8366_smi_write_bits(smi, 0x00, 1);
377
378 return 0;
379 }
380
381 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
382 {
383 u32 t;
384
385 /* read data */
386 rtl8366_smi_read_bits(smi, 8, &t);
387 *data = (t & 0xff);
388
389 /* send an ACK */
390 rtl8366_smi_write_bits(smi, 0x01, 1);
391
392 return 0;
393 }
394
395 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
396 {
397 unsigned long flags;
398 u8 lo = 0;
399 u8 hi = 0;
400 int ret;
401
402 spin_lock_irqsave(&smi->lock, flags);
403
404 rtl8366_smi_start(smi);
405
406 /* send READ command */
407 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
408 if (ret)
409 goto out;
410
411 /* set ADDR[7:0] */
412 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
413 if (ret)
414 goto out;
415
416 /* set ADDR[15:8] */
417 ret = rtl8366_smi_write_byte(smi, addr >> 8);
418 if (ret)
419 goto out;
420
421 /* read DATA[7:0] */
422 rtl8366_smi_read_byte0(smi, &lo);
423 /* read DATA[15:8] */
424 rtl8366_smi_read_byte1(smi, &hi);
425
426 *data = ((u32) lo) | (((u32) hi) << 8);
427
428 ret = 0;
429
430 out:
431 rtl8366_smi_stop(smi);
432 spin_unlock_irqrestore(&smi->lock, flags);
433
434 return ret;
435 }
436
437 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
438 {
439 unsigned long flags;
440 int ret;
441
442 spin_lock_irqsave(&smi->lock, flags);
443
444 rtl8366_smi_start(smi);
445
446 /* send WRITE command */
447 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
448 if (ret)
449 goto out;
450
451 /* set ADDR[7:0] */
452 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
453 if (ret)
454 goto out;
455
456 /* set ADDR[15:8] */
457 ret = rtl8366_smi_write_byte(smi, addr >> 8);
458 if (ret)
459 goto out;
460
461 /* write DATA[7:0] */
462 ret = rtl8366_smi_write_byte(smi, data & 0xff);
463 if (ret)
464 goto out;
465
466 /* write DATA[15:8] */
467 ret = rtl8366_smi_write_byte(smi, data >> 8);
468 if (ret)
469 goto out;
470
471 ret = 0;
472
473 out:
474 rtl8366_smi_stop(smi);
475 spin_unlock_irqrestore(&smi->lock, flags);
476
477 return ret;
478 }
479
480 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
481 u32 phy_no, u32 page, u32 addr, u32 *data)
482 {
483 u32 reg;
484 int ret;
485
486 if (phy_no > RTL8366S_PHY_NO_MAX)
487 return -EINVAL;
488
489 if (page > RTL8366S_PHY_PAGE_MAX)
490 return -EINVAL;
491
492 if (addr > RTL8366S_PHY_ADDR_MAX)
493 return -EINVAL;
494
495 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
496 RTL8366S_PHY_CTRL_READ);
497 if (ret)
498 return ret;
499
500 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
501 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
502 (addr & RTL8366S_PHY_REG_MASK);
503
504 ret = rtl8366_smi_write_reg(smi, reg, 0);
505 if (ret)
506 return ret;
507
508 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
509 if (ret)
510 return ret;
511
512 return 0;
513 }
514
515 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
516 u32 phy_no, u32 page, u32 addr, u32 data)
517 {
518 u32 reg;
519 int ret;
520
521 if (phy_no > RTL8366S_PHY_NO_MAX)
522 return -EINVAL;
523
524 if (page > RTL8366S_PHY_PAGE_MAX)
525 return -EINVAL;
526
527 if (addr > RTL8366S_PHY_ADDR_MAX)
528 return -EINVAL;
529
530 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
531 RTL8366S_PHY_CTRL_WRITE);
532 if (ret)
533 return ret;
534
535 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
536 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
537 (addr & RTL8366S_PHY_REG_MASK);
538
539 ret = rtl8366_smi_write_reg(smi, reg, data);
540 if (ret)
541 return ret;
542
543 return 0;
544 }
545
546 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
547 int port, unsigned long long *val)
548 {
549 int i;
550 int err;
551 u32 addr, data, regoffset;
552 u64 mibvalue;
553
554 /* address offset to MIBs counter */
555 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
556 2, 2, 2, 2, 2, 2, 2, 2, 2,
557 2, 2, 4, 2, 2, 2, 2, 2, 2,
558 2, 2, 2, 2, 2, 2};
559
560 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
561 return -EINVAL;
562
563 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
564
565 for (i = 0; i < counter; i++)
566 regoffset += mibLength[i];
567
568 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
569
570 /*
571 * Writing access counter address first
572 * then ASIC will prepare 64bits counter wait for being retrived
573 */
574 data = 0; /* writing data will be discard by ASIC */
575 err = rtl8366_smi_write_reg(smi, addr, data);
576 if (err)
577 return err;
578
579 /* read MIB control register */
580 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
581 if (err)
582 return err;
583
584 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
585 return -EBUSY;
586
587 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
588 return -EIO;
589
590 mibvalue = 0;
591 addr = addr + mibLength[counter] - 1;
592 i = mibLength[counter];
593
594 while (i) {
595 err = rtl8366_smi_read_reg(smi, addr, &data);
596 if (err)
597 return err;
598
599 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
600
601 addr--;
602 i--;
603 }
604
605 *val = mibvalue;
606 return 0;
607 }
608
609 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
610 struct rtl8366s_vlan4kentry *vlan4k)
611 {
612 int err;
613 u32 data;
614 u16 *tableaddr;
615
616 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
617 vlan4k->vid = vid;
618
619 if (vid >= RTL8366_NUM_VIDS)
620 return -EINVAL;
621
622 tableaddr = (u16 *)vlan4k;
623
624 /* write VID */
625 data = *tableaddr;
626 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
627 if (err)
628 return err;
629
630 /* write table access control word */
631 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
632 RTL8366S_TABLE_VLAN_READ_CTRL);
633 if (err)
634 return err;
635
636 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
637 if (err)
638 return err;
639
640 *tableaddr = data;
641 tableaddr++;
642
643 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
644 &data);
645 if (err)
646 return err;
647
648 *tableaddr = data;
649 vlan4k->vid = vid;
650
651 return 0;
652 }
653
654 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
655 const struct rtl8366s_vlan4kentry *vlan4k)
656 {
657 int err;
658 u32 data;
659 u16 *tableaddr;
660
661 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
662 vlan4k->member > RTL8366_PORT_ALL ||
663 vlan4k->untag > RTL8366_PORT_ALL ||
664 vlan4k->fid > RTL8366S_FIDMAX)
665 return -EINVAL;
666
667 tableaddr = (u16 *)vlan4k;
668
669 data = *tableaddr;
670
671 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
672 if (err)
673 return err;
674
675 tableaddr++;
676
677 data = *tableaddr;
678
679 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
680 data);
681 if (err)
682 return err;
683
684 /* write table access control word */
685 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
686 RTL8366S_TABLE_VLAN_WRITE_CTRL);
687
688 return err;
689 }
690
691 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
692 struct rtl8366s_vlanconfig *vlanmc)
693 {
694 int err;
695 u32 addr;
696 u32 data;
697 u16 *tableaddr;
698
699 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
700
701 if (index >= RTL8366_NUM_VLANS)
702 return -EINVAL;
703
704 tableaddr = (u16 *)vlanmc;
705
706 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
707 err = rtl8366_smi_read_reg(smi, addr, &data);
708 if (err)
709 return err;
710
711 *tableaddr = data;
712 tableaddr++;
713
714 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
715 err = rtl8366_smi_read_reg(smi, addr, &data);
716 if (err)
717 return err;
718
719 *tableaddr = data;
720
721 return 0;
722 }
723
724 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
725 const struct rtl8366s_vlanconfig
726 *vlanmc)
727 {
728 int err;
729 u32 addr;
730 u32 data;
731 u16 *tableaddr;
732
733 if (index >= RTL8366_NUM_VLANS ||
734 vlanmc->vid >= RTL8366_NUM_VIDS ||
735 vlanmc->priority > RTL8366S_PRIORITYMAX ||
736 vlanmc->member > RTL8366_PORT_ALL ||
737 vlanmc->untag > RTL8366_PORT_ALL ||
738 vlanmc->fid > RTL8366S_FIDMAX)
739 return -EINVAL;
740
741 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
742
743 tableaddr = (u16 *)vlanmc;
744 data = *tableaddr;
745
746 err = rtl8366_smi_write_reg(smi, addr, data);
747 if (err)
748 return err;
749
750 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
751
752 tableaddr++;
753 data = *tableaddr;
754
755 err = rtl8366_smi_write_reg(smi, addr, data);
756 if (err)
757 return err;
758
759 return 0;
760 }
761
762 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
763 int *val)
764 {
765 u32 data;
766 int err;
767
768 if (port >= RTL8366_NUM_PORTS)
769 return -EINVAL;
770
771 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
772 &data);
773 if (err)
774 return err;
775
776 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
777 RTL8366S_PORT_VLAN_CTRL_MASK;
778
779 return 0;
780
781 }
782
783 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
784 int *val)
785 {
786 struct rtl8366s_vlanconfig vlanmc;
787 int err;
788 int index;
789
790 err = rtl8366_get_port_vlan_index(smi, port, &index);
791 if (err)
792 return err;
793
794 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
795 if (err)
796 return err;
797
798 *val = vlanmc.vid;
799 return 0;
800 }
801
802 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
803 int index)
804 {
805 u32 data;
806 int err;
807
808 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
809 return -EINVAL;
810
811 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
812 &data);
813 if (err)
814 return err;
815
816 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
817 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
818 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
819 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
820
821 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
822 data);
823 return err;
824 }
825
826 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
827 int val)
828 {
829 int i;
830 struct rtl8366s_vlanconfig vlanmc;
831 struct rtl8366s_vlan4kentry vlan4k;
832
833 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
834 return -EINVAL;
835
836 /* Updating the 4K entry; lookup it and change the port member set */
837 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
838 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
839 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
840 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
841
842 /*
843 * For the 16 entries more work needs to be done. First see if such
844 * VID is already there and change it
845 */
846 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
847 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
848
849 /* Try to find an existing vid and update port member set */
850 if (val == vlanmc.vid) {
851 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
852 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
853
854 /* Now update PVID register settings */
855 rtl8366_set_port_vlan_index(smi, port, i);
856
857 return 0;
858 }
859 }
860
861 /*
862 * PVID could not be found from vlan table. Replace unused (one that
863 * has no member ports) with new one
864 */
865 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
866 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
867
868 /*
869 * See if this vlan member configuration is unused. It is
870 * unused if member set contains no ports or CPU port only
871 */
872 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
873 vlanmc.vid = val;
874 vlanmc.priority = 0;
875 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
876 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
877 vlanmc.fid = 0;
878
879 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
880
881 /* Now update PVID register settings */
882 rtl8366_set_port_vlan_index(smi, port, i);
883
884 return 0;
885 }
886 }
887
888 dev_err(smi->parent,
889 "All 16 vlan member configurations are in use\n");
890
891 return -EINVAL;
892 }
893
894
895 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
896 {
897 u32 data = 0;
898
899 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
900
901 if (enable)
902 data |= RTL8366_CHIP_CTRL_VLAN;
903 else
904 data &= ~RTL8366_CHIP_CTRL_VLAN;
905
906 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
907 }
908
909 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
910 {
911 u32 data = 0;
912
913 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
914
915 if (enable)
916 data |= 1;
917 else
918 data &= ~1;
919
920 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
921 }
922
923 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
924 {
925 struct rtl8366s_vlan4kentry vlan4k;
926 struct rtl8366s_vlanconfig vlanmc;
927 int err;
928 int i;
929
930 /* clear 16 VLAN member configuration */
931 vlanmc.vid = 0;
932 vlanmc.priority = 0;
933 vlanmc.member = 0;
934 vlanmc.untag = 0;
935 vlanmc.fid = 0;
936 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
937 err = rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
938 if (err)
939 return err;
940 }
941
942 /* Set a default VLAN with vid 1 to 4K table for all ports */
943 vlan4k.vid = 1;
944 vlan4k.member = RTL8366_PORT_ALL;
945 vlan4k.untag = RTL8366_PORT_ALL;
946 vlan4k.fid = 0;
947 err = rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
948 if (err)
949 return err;
950
951 /* Set all ports PVID to default VLAN */
952 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
953 err = rtl8366_set_vlan_port_pvid(smi, i, 0);
954 if (err)
955 return err;
956 }
957
958 return 0;
959 }
960
961 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
962 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
963 {
964 file->private_data = inode->i_private;
965 return 0;
966 }
967
968 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
969 char __user *user_buf,
970 size_t count, loff_t *ppos)
971 {
972 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
973 int i, j, len = 0;
974 char *buf = smi->buf;
975
976 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
977 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
978 " "
979 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
980 "Port 4\n");
981
982 for (i = 0; i < 33; ++i) {
983 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
984 i, MIBCOUNTERS[i]);
985 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
986 unsigned long long counter = 0;
987
988 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
989 len += snprintf(buf + len,
990 sizeof(smi->buf) - len,
991 "[%llu]", counter);
992 else
993 len += snprintf(buf + len,
994 sizeof(smi->buf) - len,
995 "[error]");
996
997 if (j != RTL8366_NUM_PORTS - 1) {
998 if (counter < 100000)
999 len += snprintf(buf + len,
1000 sizeof(smi->buf) - len,
1001 "\t");
1002
1003 len += snprintf(buf + len,
1004 sizeof(smi->buf) - len,
1005 "\t");
1006 }
1007 }
1008 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1009 }
1010
1011 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1012
1013 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1014 }
1015
1016 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1017 char __user *user_buf,
1018 size_t count, loff_t *ppos)
1019 {
1020 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1021 int i, j, len = 0;
1022 char *buf = smi->buf;
1023
1024 len += snprintf(buf + len, sizeof(smi->buf) - len,
1025 "VLAN Member Config:\n");
1026 len += snprintf(buf + len, sizeof(smi->buf) - len,
1027 "\t id \t vid \t prio \t member \t untag \t fid "
1028 "\tports\n");
1029
1030 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1031 struct rtl8366s_vlanconfig vlanmc;
1032
1033 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1034
1035 len += snprintf(buf + len, sizeof(smi->buf) - len,
1036 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1037 "\t", i, vlanmc.vid, vlanmc.priority,
1038 vlanmc.member, vlanmc.untag, vlanmc.fid);
1039
1040 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1041 int index = 0;
1042 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1043 if (index == i)
1044 len += snprintf(buf + len,
1045 sizeof(smi->buf) - len,
1046 "%d", j);
1047 }
1048 }
1049 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1050 }
1051
1052 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1053 }
1054
1055 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1056 char __user *user_buf,
1057 size_t count, loff_t *ppos)
1058 {
1059 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1060 u32 t, reg = g_dbg_reg;
1061 int err, len = 0;
1062 char *buf = smi->buf;
1063
1064 memset(buf, '\0', sizeof(smi->buf));
1065
1066 err = rtl8366_smi_read_reg(smi, reg, &t);
1067 if (err) {
1068 len += snprintf(buf, sizeof(smi->buf),
1069 "Read failed (reg: 0x%04x)\n", reg);
1070 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1071 }
1072
1073 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1074 reg, t);
1075
1076 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1077 }
1078
1079 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1080 const char __user *user_buf,
1081 size_t count, loff_t *ppos)
1082 {
1083 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1084 unsigned long data;
1085 u32 reg = g_dbg_reg;
1086 int err;
1087 size_t len;
1088 char *buf = smi->buf;
1089
1090 len = min(count, sizeof(smi->buf) - 1);
1091 if (copy_from_user(buf, user_buf, len)) {
1092 dev_err(smi->parent, "copy from user failed\n");
1093 return -EFAULT;
1094 }
1095
1096 buf[len] = '\0';
1097 if (len > 0 && buf[len - 1] == '\n')
1098 buf[len - 1] = '\0';
1099
1100
1101 if (strict_strtoul(buf, 16, &data)) {
1102 dev_err(smi->parent, "Invalid reg value %s\n", buf);
1103 } else {
1104 err = rtl8366_smi_write_reg(smi, reg, data);
1105 if (err) {
1106 dev_err(smi->parent,
1107 "writing reg 0x%04x val 0x%04lx failed\n",
1108 reg, data);
1109 }
1110 }
1111
1112 return count;
1113 }
1114
1115 static const struct file_operations fops_rtl8366_regs = {
1116 .read = rtl8366_read_debugfs_reg,
1117 .write = rtl8366_write_debugfs_reg,
1118 .open = rtl8366_debugfs_open,
1119 .owner = THIS_MODULE
1120 };
1121
1122 static const struct file_operations fops_rtl8366_vlan = {
1123 .read = rtl8366_read_debugfs_vlan,
1124 .open = rtl8366_debugfs_open,
1125 .owner = THIS_MODULE
1126 };
1127
1128 static const struct file_operations fops_rtl8366_mibs = {
1129 .read = rtl8366_read_debugfs_mibs,
1130 .open = rtl8366_debugfs_open,
1131 .owner = THIS_MODULE
1132 };
1133
1134 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1135 {
1136 struct dentry *node;
1137 struct dentry *root;
1138
1139 if (!smi->debugfs_root)
1140 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1141
1142 if (!smi->debugfs_root) {
1143 dev_err(smi->parent, "Unable to create debugfs dir\n");
1144 return;
1145 }
1146 root = smi->debugfs_root;
1147
1148 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1149 if (!node) {
1150 dev_err(smi->parent, "Creating debugfs file reg failed\n");
1151 return;
1152 }
1153
1154 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1155 &fops_rtl8366_regs);
1156 if (!node) {
1157 dev_err(smi->parent, "Creating debugfs file val failed\n");
1158 return;
1159 }
1160
1161 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1162 &fops_rtl8366_vlan);
1163 if (!node) {
1164 dev_err(smi->parent,
1165 "Creating debugfs file vlan failed\n");
1166 return;
1167 }
1168
1169 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1170 &fops_rtl8366_mibs);
1171 if (!node) {
1172 dev_err(smi->parent,
1173 "Creating debugfs file mibs failed\n");
1174 return;
1175 }
1176 }
1177
1178 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1179 {
1180 if (smi->debugfs_root) {
1181 debugfs_remove_recursive(smi->debugfs_root);
1182 smi->debugfs_root = NULL;
1183 }
1184 }
1185
1186 #else
1187 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1188 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1189 #endif /* CONFIG_RTL8366_SMI_DEBUG_FS */
1190
1191 static int rtl8366_sw_reset_mibs(struct switch_dev *dev,
1192 const struct switch_attr *attr,
1193 struct switch_val *val)
1194 {
1195 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1196 u32 data = 0;
1197
1198 if (val->value.i == 1) {
1199 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1200 data |= (1 << 2);
1201 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int rtl8366_sw_get_vlan_enable(struct switch_dev *dev,
1208 const struct switch_attr *attr,
1209 struct switch_val *val)
1210 {
1211 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1212 u32 data;
1213
1214 if (attr->ofs == 1) {
1215 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1216
1217 if (data & RTL8366_CHIP_CTRL_VLAN)
1218 val->value.i = 1;
1219 else
1220 val->value.i = 0;
1221 } else if (attr->ofs == 2) {
1222 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1223
1224 if (data & 0x0001)
1225 val->value.i = 1;
1226 else
1227 val->value.i = 0;
1228 }
1229
1230 return 0;
1231 }
1232
1233 static int rtl8366_sw_get_blinkrate(struct switch_dev *dev,
1234 const struct switch_attr *attr,
1235 struct switch_val *val)
1236 {
1237 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1238 u32 data;
1239
1240 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1241
1242 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1243
1244 return 0;
1245 }
1246
1247 static int rtl8366_sw_set_blinkrate(struct switch_dev *dev,
1248 const struct switch_attr *attr,
1249 struct switch_val *val)
1250 {
1251 u32 data;
1252 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1253
1254 if (val->value.i >= 6)
1255 return -EINVAL;
1256
1257 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1258
1259 data &= ~RTL8366_LED_BLINKRATE_MASK;
1260 data |= val->value.i;
1261
1262 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1263
1264 return 0;
1265 }
1266
1267 static int rtl8366_sw_set_vlan_enable(struct switch_dev *dev,
1268 const struct switch_attr *attr,
1269 struct switch_val *val)
1270 {
1271 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1272
1273 if (attr->ofs == 1)
1274 return rtl8366_vlan_set_vlan(smi, val->value.i);
1275 else
1276 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1277 }
1278
1279 static const char *rtl8366_speed_str(unsigned speed)
1280 {
1281 switch (speed) {
1282 case 0:
1283 return "10baseT";
1284 case 1:
1285 return "100baseT";
1286 case 2:
1287 return "1000baseT";
1288 }
1289
1290 return "unknown";
1291 }
1292
1293 static int rtl8366_sw_get_port_link(struct switch_dev *dev,
1294 const struct switch_attr *attr,
1295 struct switch_val *val)
1296 {
1297 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1298 u32 len = 0, data = 0;
1299
1300 if (val->port_vlan >= RTL8366_NUM_PORTS)
1301 return -EINVAL;
1302
1303 memset(smi->buf, '\0', sizeof(smi->buf));
1304 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1305 (val->port_vlan / 2), &data);
1306
1307 if (val->port_vlan % 2)
1308 data = data >> 8;
1309
1310 len = snprintf(smi->buf, sizeof(smi->buf),
1311 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1312 val->port_vlan,
1313 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1314 rtl8366_speed_str(data &
1315 RTL8366S_PORT_STATUS_SPEED_MASK),
1316 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1317 "full" : "half",
1318 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1319 "tx-pause ": "",
1320 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1321 "rx-pause " : "",
1322 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1323
1324 val->value.s = smi->buf;
1325 val->len = len;
1326
1327 return 0;
1328 }
1329
1330 static int rtl8366_sw_get_vlan_info(struct switch_dev *dev,
1331 const struct switch_attr *attr,
1332 struct switch_val *val)
1333 {
1334 int i;
1335 u32 len = 0;
1336 struct rtl8366s_vlanconfig vlanmc;
1337 struct rtl8366s_vlan4kentry vlan4k;
1338 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1339 char *buf = smi->buf;
1340
1341 if (val->port_vlan >= RTL8366_NUM_VLANS)
1342 return -EINVAL;
1343
1344 memset(buf, '\0', sizeof(smi->buf));
1345
1346 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1347 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1348
1349 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1350 val->port_vlan);
1351
1352 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1353 int index = 0;
1354 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1355 index == val->port_vlan)
1356 len += snprintf(buf + len, sizeof(smi->buf) - len,
1357 "%d", i);
1358 }
1359 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1360
1361 len += snprintf(buf + len, sizeof(smi->buf) - len,
1362 "\t\t vid \t prio \t member \t untag \t fid\n");
1363 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1364 len += snprintf(buf + len, sizeof(smi->buf) - len,
1365 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1366 vlanmc.vid, vlanmc.priority, vlanmc.member,
1367 vlanmc.untag, vlanmc.fid);
1368 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1369 len += snprintf(buf + len, sizeof(smi->buf) - len,
1370 "%d \t \t 0x%04x \t 0x%04x \t %d",
1371 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1372
1373 val->value.s = buf;
1374 val->len = len;
1375
1376 return 0;
1377 }
1378
1379 static int rtl8366_sw_set_port_led(struct switch_dev *dev,
1380 const struct switch_attr *attr,
1381 struct switch_val *val)
1382 {
1383 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1384 u32 data = 0;
1385
1386 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1387 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1388 return -EINVAL;
1389
1390 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1391 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1392 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1393 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1394 } else {
1395 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1396 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1397 (val->value.i << (val->port_vlan * 4));
1398 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1399 }
1400
1401 return 0;
1402 }
1403
1404 static int rtl8366_sw_get_port_led(struct switch_dev *dev,
1405 const struct switch_attr *attr,
1406 struct switch_val *val)
1407 {
1408 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1409 u32 data = 0;
1410
1411 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1412 return -EINVAL;
1413
1414 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1415 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1416
1417 return 0;
1418 }
1419
1420 static int rtl8366_sw_reset_port_mibs(struct switch_dev *dev,
1421 const struct switch_attr *attr,
1422 struct switch_val *val)
1423 {
1424 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1425 u32 data = 0;
1426
1427 if (val->port_vlan >= RTL8366_NUM_PORTS)
1428 return -EINVAL;
1429
1430 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1431 data |= (1 << (val->port_vlan + 3));
1432 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1433
1434 return 0;
1435 }
1436
1437 static int rtl8366_sw_get_port_mib(struct switch_dev *dev,
1438 const struct switch_attr *attr,
1439 struct switch_val *val)
1440 {
1441 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1442 int i, len = 0;
1443 unsigned long long counter = 0;
1444 char *buf = smi->buf;
1445
1446 if (val->port_vlan >= RTL8366_NUM_PORTS)
1447 return -EINVAL;
1448
1449 len += snprintf(buf + len, sizeof(smi->buf) - len,
1450 "Port %d MIB counters\n",
1451 val->port_vlan);
1452
1453 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1454 len += snprintf(buf + len, sizeof(smi->buf) - len,
1455 "%d:%s\t", i, MIBCOUNTERS[i]);
1456 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1457 len += snprintf(buf + len, sizeof(smi->buf) - len,
1458 "[%llu]\n", counter);
1459 else
1460 len += snprintf(buf + len, sizeof(smi->buf) - len,
1461 "[error]\n");
1462 }
1463
1464 val->value.s = buf;
1465 val->len = len;
1466 return 0;
1467 }
1468
1469 static int rtl8366_sw_get_vlan_ports(struct switch_dev *dev,
1470 struct switch_val *val)
1471 {
1472 struct rtl8366s_vlanconfig vlanmc;
1473 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1474 struct switch_port *port;
1475 int i;
1476
1477 if (val->port_vlan >= RTL8366_NUM_VLANS)
1478 return -EINVAL;
1479
1480 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1481
1482 port = &val->value.ports[0];
1483 val->len = 0;
1484 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1485 if (!(vlanmc.member & BIT(i)))
1486 continue;
1487
1488 port->id = i;
1489 port->flags = (vlanmc.untag & BIT(i)) ?
1490 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1491 val->len++;
1492 port++;
1493 }
1494 return 0;
1495 }
1496
1497 static int rtl8366_sw_set_vlan_ports(struct switch_dev *dev,
1498 struct switch_val *val)
1499 {
1500 struct rtl8366s_vlanconfig vlanmc;
1501 struct rtl8366s_vlan4kentry vlan4k;
1502 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1503 struct switch_port *port;
1504 int i;
1505
1506 if (val->port_vlan >= RTL8366_NUM_VLANS)
1507 return -EINVAL;
1508
1509 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1510 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1511
1512 vlanmc.untag = 0;
1513 vlanmc.member = 0;
1514
1515 port = &val->value.ports[0];
1516 for (i = 0; i < val->len; i++, port++) {
1517 vlanmc.member |= BIT(port->id);
1518
1519 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1520 vlanmc.untag |= BIT(port->id);
1521 }
1522
1523 vlan4k.member = vlanmc.member;
1524 vlan4k.untag = vlanmc.untag;
1525
1526 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1527 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1528 return 0;
1529 }
1530
1531 static int rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1532 {
1533 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1534 return rtl8366_get_vlan_port_pvid(smi, port, val);
1535 }
1536
1537 static int rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1538 {
1539 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1540 return rtl8366_set_vlan_port_pvid(smi, port, val);
1541 }
1542
1543 static int rtl8366_sw_reset_switch(struct switch_dev *dev)
1544 {
1545 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1546 int timeout = 10;
1547 u32 data;
1548
1549 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1550 RTL8366_CHIP_CTRL_RESET_HW);
1551 do {
1552 msleep(1);
1553 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1554 return -EIO;
1555
1556 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1557 break;
1558 } while (--timeout);
1559
1560 if (!timeout) {
1561 printk("Timeout waiting for the switch to reset\n");
1562 return -EIO;
1563 }
1564
1565 return rtl8366s_reset_vlan(smi);
1566 }
1567
1568 static struct switch_attr rtl8366_globals[] = {
1569 {
1570 .type = SWITCH_TYPE_INT,
1571 .name = "enable_vlan",
1572 .description = "Enable VLAN mode",
1573 .set = rtl8366_sw_set_vlan_enable,
1574 .get = rtl8366_sw_get_vlan_enable,
1575 .max = 1,
1576 .ofs = 1
1577 }, {
1578 .type = SWITCH_TYPE_INT,
1579 .name = "enable_vlan4k",
1580 .description = "Enable VLAN 4K mode",
1581 .set = rtl8366_sw_set_vlan_enable,
1582 .get = rtl8366_sw_get_vlan_enable,
1583 .max = 1,
1584 .ofs = 2
1585 }, {
1586 .type = SWITCH_TYPE_INT,
1587 .name = "reset_mibs",
1588 .description = "Reset all MIB counters",
1589 .set = rtl8366_sw_reset_mibs,
1590 .get = NULL,
1591 .max = 1
1592 }, {
1593 .type = SWITCH_TYPE_INT,
1594 .name = "blinkrate",
1595 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1596 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1597 .set = rtl8366_sw_set_blinkrate,
1598 .get = rtl8366_sw_get_blinkrate,
1599 .max = 5
1600 },
1601 };
1602
1603 static struct switch_attr rtl8366_port[] = {
1604 {
1605 .type = SWITCH_TYPE_STRING,
1606 .name = "link",
1607 .description = "Get port link information",
1608 .max = 1,
1609 .set = NULL,
1610 .get = rtl8366_sw_get_port_link,
1611 }, {
1612 .type = SWITCH_TYPE_INT,
1613 .name = "reset_mib",
1614 .description = "Reset single port MIB counters",
1615 .max = 1,
1616 .set = rtl8366_sw_reset_port_mibs,
1617 .get = NULL,
1618 }, {
1619 .type = SWITCH_TYPE_STRING,
1620 .name = "mib",
1621 .description = "Get MIB counters for port",
1622 .max = 33,
1623 .set = NULL,
1624 .get = rtl8366_sw_get_port_mib,
1625 }, {
1626 .type = SWITCH_TYPE_INT,
1627 .name = "led",
1628 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1629 .max = 15,
1630 .set = rtl8366_sw_set_port_led,
1631 .get = rtl8366_sw_get_port_led,
1632 },
1633 };
1634
1635 static struct switch_attr rtl8366_vlan[] = {
1636 {
1637 .type = SWITCH_TYPE_STRING,
1638 .name = "info",
1639 .description = "Get vlan information",
1640 .max = 1,
1641 .set = NULL,
1642 .get = rtl8366_sw_get_vlan_info,
1643 },
1644 };
1645
1646
1647 /* template */
1648 static struct switch_dev rtldev = {
1649 .name = "RTL8366S",
1650 .cpu_port = RTL8366_PORT_NUM_CPU,
1651 .ports = RTL8366_NUM_PORTS,
1652 .vlans = RTL8366_NUM_VLANS,
1653 .attr_global = {
1654 .attr = rtl8366_globals,
1655 .n_attr = ARRAY_SIZE(rtl8366_globals),
1656 },
1657 .attr_port = {
1658 .attr = rtl8366_port,
1659 .n_attr = ARRAY_SIZE(rtl8366_port),
1660 },
1661 .attr_vlan = {
1662 .attr = rtl8366_vlan,
1663 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1664 },
1665
1666 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1667 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1668 .get_port_pvid = rtl8366_sw_get_port_pvid,
1669 .set_port_pvid = rtl8366_sw_set_port_pvid,
1670 .reset_switch = rtl8366_sw_reset_switch,
1671 };
1672
1673 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1674 {
1675 struct switch_dev *dev = &smi->dev;
1676 int err;
1677
1678 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1679 dev->priv = smi;
1680 dev->devname = dev_name(smi->parent);
1681
1682 err = register_switch(dev, NULL);
1683 if (err)
1684 dev_err(smi->parent, "switch registration failed\n");
1685
1686 return err;
1687 }
1688
1689 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1690 {
1691 unregister_switch(&smi->dev);
1692 }
1693
1694 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1695 {
1696 struct rtl8366_smi *smi = bus->priv;
1697 u32 val = 0;
1698 int err;
1699
1700 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1701 if (err)
1702 return 0xffff;
1703
1704 return val;
1705 }
1706
1707 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1708 u16 val)
1709 {
1710 struct rtl8366_smi *smi = bus->priv;
1711 u32 t;
1712 int err;
1713
1714 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1715 /* flush write */
1716 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1717
1718 return err;
1719 }
1720
1721 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1722 {
1723 int ret;
1724 int i;
1725
1726 smi->mii_bus = mdiobus_alloc();
1727 if (smi->mii_bus == NULL) {
1728 ret = -ENOMEM;
1729 goto err;
1730 }
1731
1732 spin_lock_init(&smi->lock);
1733 smi->mii_bus->priv = (void *) smi;
1734 smi->mii_bus->name = "rtl8366-smi";
1735 smi->mii_bus->read = rtl8366_smi_mii_read;
1736 smi->mii_bus->write = rtl8366_smi_mii_write;
1737 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1738 dev_name(smi->parent));
1739 smi->mii_bus->parent = smi->parent;
1740 smi->mii_bus->phy_mask = ~(0x1f);
1741 smi->mii_bus->irq = smi->mii_irq;
1742 for (i = 0; i < PHY_MAX_ADDR; i++)
1743 smi->mii_irq[i] = PHY_POLL;
1744
1745 ret = mdiobus_register(smi->mii_bus);
1746 if (ret)
1747 goto err_free;
1748
1749 return 0;
1750
1751 err_free:
1752 mdiobus_free(smi->mii_bus);
1753 err:
1754 return ret;
1755 }
1756
1757 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1758 {
1759 mdiobus_unregister(smi->mii_bus);
1760 mdiobus_free(smi->mii_bus);
1761 }
1762
1763 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1764 {
1765 return (bus->read == rtl8366_smi_mii_read &&
1766 bus->write == rtl8366_smi_mii_write);
1767 }
1768
1769 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1770 {
1771 u32 chip_id = 0;
1772 u32 chip_ver = 0;
1773 int ret;
1774
1775 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1776 if (ret) {
1777 dev_err(smi->parent, "unable to read chip id\n");
1778 return ret;
1779 }
1780
1781 switch (chip_id) {
1782 case RTL8366S_CHIP_ID_8366:
1783 break;
1784 default:
1785 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1786 return -ENODEV;
1787 }
1788
1789 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1790 &chip_ver);
1791 if (ret) {
1792 dev_err(smi->parent, "unable to read chip version\n");
1793 return ret;
1794 }
1795
1796 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1797 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1798
1799 rtl8366_debugfs_init(smi);
1800
1801 return 0;
1802 }
1803
1804 static int __init rtl8366_smi_init(struct rtl8366_smi *smi)
1805 {
1806 int err;
1807
1808 if (!smi->parent)
1809 return -EINVAL;
1810
1811 err = gpio_request(smi->gpio_sda, dev_name(smi->parent));
1812 if (err) {
1813 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1814 smi->gpio_sda, err);
1815 goto err_out;
1816 }
1817
1818 err = gpio_request(smi->gpio_sck, dev_name(smi->parent));
1819 if (err) {
1820 dev_err(smi->parent, "gpio_request failed for %u, err=%d\n",
1821 smi->gpio_sck, err);
1822 goto err_free_sda;
1823 }
1824
1825 spin_lock_init(&smi->lock);
1826
1827 dev_info(smi->parent, "using GPIO pins %u (SDA) and %u (SCK)\n",
1828 smi->gpio_sda, smi->gpio_sck);
1829
1830 return 0;
1831
1832 err_free_sda:
1833 gpio_free(smi->gpio_sda);
1834 err_out:
1835 return err;
1836 }
1837
1838 static void rtl8366_smi_cleanup(struct rtl8366_smi *smi)
1839 {
1840 gpio_free(smi->gpio_sck);
1841 gpio_free(smi->gpio_sda);
1842 }
1843
1844 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1845 {
1846 static int rtl8366_smi_version_printed;
1847 struct rtl8366_smi_platform_data *pdata;
1848 struct rtl8366_smi *smi;
1849 int err;
1850
1851 if (!rtl8366_smi_version_printed++)
1852 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1853 " version " RTL8366_SMI_DRIVER_VER"\n");
1854
1855 pdata = pdev->dev.platform_data;
1856 if (!pdata) {
1857 dev_err(&pdev->dev, "no platform data specified\n");
1858 err = -EINVAL;
1859 goto err_out;
1860 }
1861
1862 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1863 if (!smi) {
1864 dev_err(&pdev->dev, "no memory for private data\n");
1865 err = -ENOMEM;
1866 goto err_out;
1867 }
1868
1869 smi->parent = &pdev->dev;
1870 smi->gpio_sda = pdata->gpio_sda;
1871 smi->gpio_sck = pdata->gpio_sck;
1872
1873 err = rtl8366_smi_init(smi);
1874 if (err)
1875 goto err_free_smi;
1876
1877 platform_set_drvdata(pdev, smi);
1878
1879 err = rtl8366_smi_setup(smi);
1880 if (err)
1881 goto err_clear_drvdata;
1882
1883 err = rtl8366_smi_mii_init(smi);
1884 if (err)
1885 goto err_clear_drvdata;
1886
1887 err = rtl8366_smi_switch_init(smi);
1888 if (err)
1889 goto err_mii_cleanup;
1890
1891 return 0;
1892
1893 err_mii_cleanup:
1894 rtl8366_smi_mii_cleanup(smi);
1895 err_clear_drvdata:
1896 platform_set_drvdata(pdev, NULL);
1897 err_free_smi:
1898 kfree(smi);
1899 err_out:
1900 return err;
1901 }
1902
1903 static int rtl8366_phy_config_init(struct phy_device *phydev)
1904 {
1905 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1906 return -EINVAL;
1907
1908 return 0;
1909 }
1910
1911 static int rtl8366_phy_config_aneg(struct phy_device *phydev)
1912 {
1913 return 0;
1914 }
1915
1916 static struct phy_driver rtl8366_smi_phy_driver = {
1917 .phy_id = 0x001cc960,
1918 .name = "Realtek RTL8366",
1919 .phy_id_mask = 0x1ffffff0,
1920 .features = PHY_GBIT_FEATURES,
1921 .config_aneg = rtl8366_phy_config_aneg,
1922 .config_init = rtl8366_phy_config_init,
1923 .read_status = genphy_read_status,
1924 .driver = {
1925 .owner = THIS_MODULE,
1926 },
1927 };
1928
1929 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1930 {
1931 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1932
1933 if (smi) {
1934 rtl8366_smi_switch_cleanup(smi);
1935 rtl8366_debugfs_remove(smi);
1936 rtl8366_smi_mii_cleanup(smi);
1937 platform_set_drvdata(pdev, NULL);
1938 rtl8366_smi_cleanup(smi);
1939 kfree(smi);
1940 }
1941
1942 return 0;
1943 }
1944
1945 static struct platform_driver rtl8366_smi_driver = {
1946 .driver = {
1947 .name = RTL8366_SMI_DRIVER_NAME,
1948 .owner = THIS_MODULE,
1949 },
1950 .probe = rtl8366_smi_probe,
1951 .remove = __devexit_p(rtl8366_smi_remove),
1952 };
1953
1954 static int __init rtl8366_smi_module_init(void)
1955 {
1956 int ret;
1957 ret = platform_driver_register(&rtl8366_smi_driver);
1958 if (ret)
1959 return ret;
1960
1961 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1962 if (ret)
1963 goto err_platform_unregister;
1964
1965 return 0;
1966
1967 err_platform_unregister:
1968 platform_driver_unregister(&rtl8366_smi_driver);
1969 return ret;
1970 }
1971 module_init(rtl8366_smi_module_init);
1972
1973 static void __exit rtl8366_smi_exit(void)
1974 {
1975 phy_driver_unregister(&rtl8366_smi_phy_driver);
1976 platform_driver_unregister(&rtl8366_smi_driver);
1977 }
1978 module_exit(rtl8366_smi_exit);
1979
1980 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1981 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1982 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1983 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1984 MODULE_LICENSE("GPL v2");
1985 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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