target/linux/atheros/patches-3.14/105-ar2315_pci.patch

   1 --- a/arch/mips/ar231x/Makefile
   2 +++ b/arch/mips/ar231x/Makefile
   3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
   4
   5  obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
   6  obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
   7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
   8 --- /dev/null
   9 +++ b/arch/mips/ar231x/pci.c
  10 @@ -0,0 +1,254 @@
  11 +/*
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License
  14 + * as published by the Free Software Foundation; either version 2
  15 + * of the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  24 + */
  25 +
  26 +/**
  27 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  28 + * and interrupt. PCI interface supports MMIO access method, but does not
  29 + * seem to support I/O ports.
  30 + *
  31 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  32 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  33 + * the bus are taken from memory read/write request and 2 MSBs are
  34 + * determined by PCI unit configuration.
  35 + *
  36 + * To work with the configuration space instead of memory is necessary set
  37 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  38 + *
  39 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  40 + * controller BARs are programmend as if an external device is programmed.
  41 + * Which means that during configuration, IDSEL pin of the chip should be
  42 + * asserted.
  43 + *
  44 + * We know (and support) only one board that uses the PCI interface -
  45 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  46 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  47 + * and IDSEL pin of AR125 is connected to AD[16] line.
  48 + */
  49 +
  50 +#include <linux/types.h>
  51 +#include <linux/pci.h>
  52 +#include <linux/kernel.h>
  53 +#include <linux/init.h>
  54 +#include <linux/mm.h>
  55 +#include <linux/delay.h>
  56 +#include <linux/irq.h>
  57 +#include <linux/io.h>
  58 +#include <asm/paccess.h>
  59 +#include <ar231x_platform.h>
  60 +#include <ar231x.h>
  61 +#include <ar2315_regs.h>
  62 +#include "devices.h"
  63 +
  64 +#define AR2315_MEM_BASE    0x80800000UL
  65 +#define AR2315_MEM_SIZE    0x00ffffffUL
  66 +#define AR2315_IO_SIZE     0x00007fffUL
  67 +
  68 +static unsigned long configspace;
  69 +
  70 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
  71 +                                bool write)
  72 +{
  73 +       int func = PCI_FUNC(devfn);
  74 +       int dev = PCI_SLOT(devfn);
  75 +       u32 value = 0;
  76 +       int err = 0;
  77 +       u32 addr;
  78 +
  79 +       if (((dev != 0) && (dev != 3)) || (func > 2))
  80 +               return PCIBIOS_DEVICE_NOT_FOUND;
  81 +
  82 +       /* Select Configuration access */
  83 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  84 +       mb();
  85 +
  86 +       addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where;
  87 +       if (size == 1)
  88 +               addr ^= 0x3;
  89 +       else if (size == 2)
  90 +               addr ^= 0x2;
  91 +
  92 +       if (write) {
  93 +               value = *ptr;
  94 +               if (size == 1)
  95 +                       err = put_dbe(value, (u8 *)addr);
  96 +               else if (size == 2)
  97 +                       err = put_dbe(value, (u16 *)addr);
  98 +               else if (size == 4)
  99 +                       err = put_dbe(value, (u32 *)addr);
 100 +       } else {
 101 +               if (size == 1)
 102 +                       err = get_dbe(value, (u8 *)addr);
 103 +               else if (size == 2)
 104 +                       err = get_dbe(value, (u16 *)addr);
 105 +               else if (size == 4)
 106 +                       err = get_dbe(value, (u32 *)addr);
 107 +               if (err)
 108 +                       *ptr = 0xffffffff;
 109 +               else
 110 +                       *ptr = value;
 111 +       }
 112 +
 113 +       /* Select Memory access */
 114 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 115 +
 116 +       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 117 +}
 118 +
 119 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
 120 +                              int where, int size, u32 *value)
 121 +{
 122 +       return ar2315_pci_cfg_access(devfn, where, size, value, 0);
 123 +}
 124 +
 125 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
 126 +                               int where, int size, u32 value)
 127 +{
 128 +       return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
 129 +}
 130 +
 131 +static struct pci_ops ar2315_pci_ops = {
 132 +       .read   = ar2315_pci_cfg_read,
 133 +       .write  = ar2315_pci_cfg_write,
 134 +};
 135 +
 136 +static struct resource ar2315_mem_resource = {
 137 +       .name   = "ar2315-pci-mem",
 138 +       .start  = AR2315_MEM_BASE,
 139 +       .end    = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
 140 +                 0x4000000,
 141 +       .flags  = IORESOURCE_MEM,
 142 +};
 143 +
 144 +static struct resource ar2315_io_resource = {
 145 +       .name   = "ar2315-pci-io",
 146 +       .start  = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
 147 +       .end    = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
 148 +       .flags  = IORESOURCE_IO,
 149 +};
 150 +
 151 +static struct pci_controller ar2315_pci_controller = {
 152 +       .pci_ops        = &ar2315_pci_ops,
 153 +       .mem_resource   = &ar2315_mem_resource,
 154 +       .io_resource    = &ar2315_io_resource,
 155 +       .mem_offset     = 0x00000000UL,
 156 +       .io_offset      = 0x00000000UL,
 157 +};
 158 +
 159 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 160 +{
 161 +       return AR2315_IRQ_LCBUS_PCI;
 162 +}
 163 +
 164 +int pcibios_plat_dev_init(struct pci_dev *dev)
 165 +{
 166 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
 167 +       pci_write_config_word(dev, 0x40, 0);
 168 +
 169 +       /* Clear any pending Abort or external Interrupts
 170 +        * and enable interrupt processing */
 171 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
 172 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT |
 173 +                        AR2315_PCI_EXT_INT));
 174 +       ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT |
 175 +                        AR2315_PCI_EXT_INT));
 176 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
 177 +
 178 +       return 0;
 179 +}
 180 +
 181 +static void
 182 +ar2315_pci_fixup(struct pci_dev *dev)
 183 +{
 184 +       unsigned int devfn = dev->devfn;
 185 +
 186 +       if (dev->bus->number != 0)
 187 +               return;
 188 +
 189 +       /* Only fix up the PCI host settings */
 190 +       if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
 191 +               return;
 192 +
 193 +       /* Fix up MBARs */
 194 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
 195 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
 196 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
 197 +       pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
 198 +                              PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 199 +                              PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 200 +                              PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 201 +}
 202 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
 203 +
 204 +static int __init
 205 +ar2315_pci_init(void)
 206 +{
 207 +       u32 reg;
 208 +
 209 +       if (ar231x_devtype != DEV_TYPE_AR2315)
 210 +               return -ENODEV;
 211 +
 212 +       /* Remap PCI config space */
 213 +       configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT,
 214 +                                                    1 * 1024 * 1024);
 215 +       ar2315_pci_controller.io_map_base =
 216 +                       (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
 217 +                       AR2315_MEM_SIZE, AR2315_IO_SIZE);
 218 +       set_io_port_base(ar2315_pci_controller.io_map_base); /* PCI I/O space*/
 219 +
 220 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 221 +       msleep(20);
 222 +
 223 +       reg &= ~AR2315_RESET_PCIDMA;
 224 +       ar231x_write_reg(AR2315_RESET, reg);
 225 +       msleep(20);
 226 +
 227 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 228 +                       AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 229 +
 230 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 231 +                        (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 232 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 233 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 234 +                       AR2315_IF_PCI | AR2315_IF_PCI_HOST |
 235 +                       AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 236 +                                             AR2315_IF_PCI_CLK_SHIFT));
 237 +
 238 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 239 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 240 +                       AR2315_PCIRST_LOW);
 241 +       msleep(100);
 242 +
 243 +       /* Bring the PCI out of reset */
 244 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 245 +                       AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 246 +
 247 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 248 +                        0x1E | /* 1GB uncached */
 249 +                        (1 << 5) | /* Enable uncached */
 250 +                        (0x2 << 30) /* Base: 0x80000000 */);
 251 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 252 +
 253 +       msleep(500);
 254 +
 255 +       /* dirty hack - anyone with a datasheet that knows the memory map ? */
 256 +       ioport_resource.start = 0x10000000;
 257 +       ioport_resource.end = 0xffffffff;
 258 +
 259 +       register_pci_controller(&ar2315_pci_controller);
 260 +
 261 +       return 0;
 262 +}
 263 +
 264 +arch_initcall(ar2315_pci_init);
 265 --- a/arch/mips/ar231x/Kconfig
 266 +++ b/arch/mips/ar231x/Kconfig
 267 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
 268         bool "Atheros 2315+ support"
 269         depends on ATHEROS_AR231X
 270         default y
 271 +
 272 +config ATHEROS_AR2315_PCI
 273 +       bool "PCI support"
 274 +       depends on ATHEROS_AR2315
 275 +       select HW_HAS_PCI
 276 +       select PCI
 277 +       default y
 278 --- a/arch/mips/ar231x/ar2315.c
 279 +++ b/arch/mips/ar231x/ar2315.c
 280 @@ -87,6 +87,28 @@ static void ar2315_misc_irq_handler(unsi
 281                 do_IRQ(AR2315_MISC_IRQ_NONE);
 282  }
 283
 284 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 285 +static inline void pci_abort_irq(void)
 286 +{
 287 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
 288 +}
 289 +
 290 +static inline void pci_ack_irq(void)
 291 +{
 292 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
 293 +}
 294 +
 295 +static void ar2315_pci_irq(int irq)
 296 +{
 297 +       if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
 298 +               pci_abort_irq();
 299 +       else {
 300 +               do_IRQ(irq);
 301 +               pci_ack_irq();
 302 +       }
 303 +}
 304 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
 305 +
 306  /*
 307   * Called when an interrupt is received, this function
 308   * determines exactly which interrupt it was, and it
 309 @@ -104,6 +126,10 @@ ar2315_irq_dispatch(void)
 310                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 311         else if (pending & CAUSEF_IP4)
 312                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 313 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 314 +       else if (pending & CAUSEF_IP5)
 315 +               ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
 316 +#endif
 317         else if (pending & CAUSEF_IP2)
 318                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 319         else if (pending & CAUSEF_IP7)