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generic: ar8216: add get_port_link callback
[openwrt/staging/yousong.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37
38 #include "ar8216.h"
39
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 struct ar8xxx_priv;
48
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51
52 enum {
53 AR8XXX_VER_AR8216 = 0x01,
54 AR8XXX_VER_AR8236 = 0x03,
55 AR8XXX_VER_AR8316 = 0x10,
56 AR8XXX_VER_AR8327 = 0x12,
57 };
58
59 struct ar8xxx_mib_desc {
60 unsigned int size;
61 unsigned int offset;
62 const char *name;
63 };
64
65 struct ar8xxx_chip {
66 unsigned long caps;
67
68 int (*hw_init)(struct ar8xxx_priv *priv);
69 void (*init_globals)(struct ar8xxx_priv *priv);
70 void (*init_port)(struct ar8xxx_priv *priv, int port);
71 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
72 u32 ingress, u32 members, u32 pvid);
73 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
74 int (*atu_flush)(struct ar8xxx_priv *priv);
75 void (*vtu_flush)(struct ar8xxx_priv *priv);
76 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
77
78 const struct ar8xxx_mib_desc *mib_decs;
79 unsigned num_mibs;
80 };
81
82 struct ar8327_data {
83 u32 port0_status;
84 u32 port6_status;
85 };
86
87 struct ar8xxx_priv {
88 struct switch_dev dev;
89 struct mii_bus *mii_bus;
90 struct phy_device *phy;
91
92 u32 (*read)(struct ar8xxx_priv *priv, int reg);
93 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
94
95 int (*get_port_link)(unsigned port);
96
97 const struct net_device_ops *ndo_old;
98 struct net_device_ops ndo;
99 struct mutex reg_mutex;
100 u8 chip_ver;
101 u8 chip_rev;
102 const struct ar8xxx_chip *chip;
103 union {
104 struct ar8327_data ar8327;
105 } chip_data;
106 bool initialized;
107 bool port4_phy;
108 char buf[2048];
109
110 bool init;
111 bool mii_lo_first;
112
113 struct mutex mib_lock;
114 struct delayed_work mib_work;
115 int mib_next_port;
116 u64 *mib_stats;
117
118 struct list_head list;
119 unsigned int use_count;
120
121 /* all fields below are cleared on reset */
122 bool vlan;
123 u16 vlan_id[AR8X16_MAX_VLANS];
124 u8 vlan_table[AR8X16_MAX_VLANS];
125 u8 vlan_tagged;
126 u16 pvid[AR8X16_MAX_PORTS];
127
128 /* mirroring */
129 bool mirror_rx;
130 bool mirror_tx;
131 int source_port;
132 int monitor_port;
133 };
134
135 #define MIB_DESC(_s , _o, _n) \
136 { \
137 .size = (_s), \
138 .offset = (_o), \
139 .name = (_n), \
140 }
141
142 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
143 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
144 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
145 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
146 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
147 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
148 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
149 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
150 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
151 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
152 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
153 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
154 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
155 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
156 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
157 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
158 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
159 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
160 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
161 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
162 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
163 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
164 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
165 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
166 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
167 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
168 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
169 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
170 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
171 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
172 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
173 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
174 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
175 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
176 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
177 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
178 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
179 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
180 };
181
182 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
183 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
184 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
185 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
186 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
187 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
188 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
189 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
190 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
191 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
192 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
193 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
194 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
195 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
196 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
197 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
198 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
199 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
200 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
201 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
202 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
203 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
204 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
205 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
206 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
207 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
208 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
209 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
210 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
211 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
212 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
213 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
214 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
215 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
216 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
217 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
218 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
219 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
220 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
221 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
222 };
223
224 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
225 static LIST_HEAD(ar8xxx_dev_list);
226
227 static inline struct ar8xxx_priv *
228 swdev_to_ar8xxx(struct switch_dev *swdev)
229 {
230 return container_of(swdev, struct ar8xxx_priv, dev);
231 }
232
233 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
234 {
235 return priv->chip->caps & AR8XXX_CAP_GIGE;
236 }
237
238 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
239 {
240 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
241 }
242
243 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
244 {
245 return priv->chip_ver == AR8XXX_VER_AR8216;
246 }
247
248 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
249 {
250 return priv->chip_ver == AR8XXX_VER_AR8236;
251 }
252
253 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
254 {
255 return priv->chip_ver == AR8XXX_VER_AR8316;
256 }
257
258 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
259 {
260 return priv->chip_ver == AR8XXX_VER_AR8327;
261 }
262
263 static inline void
264 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
265 {
266 regaddr >>= 1;
267 *r1 = regaddr & 0x1e;
268
269 regaddr >>= 5;
270 *r2 = regaddr & 0x7;
271
272 regaddr >>= 3;
273 *page = regaddr & 0x1ff;
274 }
275
276 static u32
277 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
278 {
279 struct mii_bus *bus = priv->mii_bus;
280 u16 r1, r2, page;
281 u16 lo, hi;
282
283 split_addr((u32) reg, &r1, &r2, &page);
284
285 mutex_lock(&bus->mdio_lock);
286
287 bus->write(bus, 0x18, 0, page);
288 usleep_range(1000, 2000); /* wait for the page switch to propagate */
289 lo = bus->read(bus, 0x10 | r2, r1);
290 hi = bus->read(bus, 0x10 | r2, r1 + 1);
291
292 mutex_unlock(&bus->mdio_lock);
293
294 return (hi << 16) | lo;
295 }
296
297 static void
298 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
299 {
300 struct mii_bus *bus = priv->mii_bus;
301 u16 r1, r2, r3;
302 u16 lo, hi;
303
304 split_addr((u32) reg, &r1, &r2, &r3);
305 lo = val & 0xffff;
306 hi = (u16) (val >> 16);
307
308 mutex_lock(&bus->mdio_lock);
309
310 bus->write(bus, 0x18, 0, r3);
311 usleep_range(1000, 2000); /* wait for the page switch to propagate */
312 if (priv->mii_lo_first) {
313 bus->write(bus, 0x10 | r2, r1, lo);
314 bus->write(bus, 0x10 | r2, r1 + 1, hi);
315 } else {
316 bus->write(bus, 0x10 | r2, r1 + 1, hi);
317 bus->write(bus, 0x10 | r2, r1, lo);
318 }
319
320 mutex_unlock(&bus->mdio_lock);
321 }
322
323 static void
324 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
325 u16 dbg_addr, u16 dbg_data)
326 {
327 struct mii_bus *bus = priv->mii_bus;
328
329 mutex_lock(&bus->mdio_lock);
330 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
331 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
332 mutex_unlock(&bus->mdio_lock);
333 }
334
335 static void
336 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
337 {
338 struct mii_bus *bus = priv->mii_bus;
339
340 mutex_lock(&bus->mdio_lock);
341 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
342 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
343 mutex_unlock(&bus->mdio_lock);
344 }
345
346 static u32
347 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
348 {
349 u32 v;
350
351 lockdep_assert_held(&priv->reg_mutex);
352
353 v = priv->read(priv, reg);
354 v &= ~mask;
355 v |= val;
356 priv->write(priv, reg, v);
357
358 return v;
359 }
360
361 static inline void
362 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
363 {
364 u32 v;
365
366 lockdep_assert_held(&priv->reg_mutex);
367
368 v = priv->read(priv, reg);
369 v |= val;
370 priv->write(priv, reg, v);
371 }
372
373 static int
374 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
375 unsigned timeout)
376 {
377 int i;
378
379 for (i = 0; i < timeout; i++) {
380 u32 t;
381
382 t = priv->read(priv, reg);
383 if ((t & mask) == val)
384 return 0;
385
386 usleep_range(1000, 2000);
387 }
388
389 return -ETIMEDOUT;
390 }
391
392 static int
393 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
394 {
395 unsigned mib_func;
396 int ret;
397
398 lockdep_assert_held(&priv->mib_lock);
399
400 if (chip_is_ar8327(priv))
401 mib_func = AR8327_REG_MIB_FUNC;
402 else
403 mib_func = AR8216_REG_MIB_FUNC;
404
405 mutex_lock(&priv->reg_mutex);
406 /* Capture the hardware statistics for all ports */
407 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
408 mutex_unlock(&priv->reg_mutex);
409
410 /* Wait for the capturing to complete. */
411 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
412 if (ret)
413 goto out;
414
415 ret = 0;
416
417 out:
418 return ret;
419 }
420
421 static int
422 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
423 {
424 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
425 }
426
427 static int
428 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
429 {
430 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
431 }
432
433 static void
434 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
435 {
436 unsigned int base;
437 u64 *mib_stats;
438 int i;
439
440 WARN_ON(port >= priv->dev.ports);
441
442 lockdep_assert_held(&priv->mib_lock);
443
444 if (chip_is_ar8327(priv))
445 base = AR8327_REG_PORT_STATS_BASE(port);
446 else if (chip_is_ar8236(priv) ||
447 chip_is_ar8316(priv))
448 base = AR8236_REG_PORT_STATS_BASE(port);
449 else
450 base = AR8216_REG_PORT_STATS_BASE(port);
451
452 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
453 for (i = 0; i < priv->chip->num_mibs; i++) {
454 const struct ar8xxx_mib_desc *mib;
455 u64 t;
456
457 mib = &priv->chip->mib_decs[i];
458 t = priv->read(priv, base + mib->offset);
459 if (mib->size == 2) {
460 u64 hi;
461
462 hi = priv->read(priv, base + mib->offset + 4);
463 t |= hi << 32;
464 }
465
466 if (flush)
467 mib_stats[i] = 0;
468 else
469 mib_stats[i] += t;
470 }
471 }
472
473 static void
474 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
475 struct switch_port_link *link)
476 {
477 u32 status;
478 u32 speed;
479
480 memset(link, '\0', sizeof(*link));
481
482 status = priv->chip->read_port_status(priv, port);
483
484 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
485 if (link->aneg) {
486 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
487 } else {
488 link->link = true;
489
490 if (priv->get_port_link) {
491 int err;
492
493 err = priv->get_port_link(port);
494 if (err >= 0)
495 link->link = !!err;
496 }
497 }
498
499 if (!link->link)
500 return;
501
502 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
503 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
504 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
505
506 speed = (status & AR8216_PORT_STATUS_SPEED) >>
507 AR8216_PORT_STATUS_SPEED_S;
508
509 switch (speed) {
510 case AR8216_PORT_SPEED_10M:
511 link->speed = SWITCH_PORT_SPEED_10;
512 break;
513 case AR8216_PORT_SPEED_100M:
514 link->speed = SWITCH_PORT_SPEED_100;
515 break;
516 case AR8216_PORT_SPEED_1000M:
517 link->speed = SWITCH_PORT_SPEED_1000;
518 break;
519 default:
520 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
521 break;
522 }
523 }
524
525 static struct sk_buff *
526 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
527 {
528 struct ar8xxx_priv *priv = dev->phy_ptr;
529 unsigned char *buf;
530
531 if (unlikely(!priv))
532 goto error;
533
534 if (!priv->vlan)
535 goto send;
536
537 if (unlikely(skb_headroom(skb) < 2)) {
538 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
539 goto error;
540 }
541
542 buf = skb_push(skb, 2);
543 buf[0] = 0x10;
544 buf[1] = 0x80;
545
546 send:
547 return skb;
548
549 error:
550 dev_kfree_skb_any(skb);
551 return NULL;
552 }
553
554 static void
555 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
556 {
557 struct ar8xxx_priv *priv;
558 unsigned char *buf;
559 int port, vlan;
560
561 priv = dev->phy_ptr;
562 if (!priv)
563 return;
564
565 /* don't strip the header if vlan mode is disabled */
566 if (!priv->vlan)
567 return;
568
569 /* strip header, get vlan id */
570 buf = skb->data;
571 skb_pull(skb, 2);
572
573 /* check for vlan header presence */
574 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
575 return;
576
577 port = buf[0] & 0xf;
578
579 /* no need to fix up packets coming from a tagged source */
580 if (priv->vlan_tagged & (1 << port))
581 return;
582
583 /* lookup port vid from local table, the switch passes an invalid vlan id */
584 vlan = priv->vlan_id[priv->pvid[port]];
585
586 buf[14 + 2] &= 0xf0;
587 buf[14 + 2] |= vlan >> 8;
588 buf[15 + 2] = vlan & 0xff;
589 }
590
591 static int
592 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
593 {
594 int timeout = 20;
595 u32 t = 0;
596
597 while (1) {
598 t = priv->read(priv, reg);
599 if ((t & mask) == val)
600 return 0;
601
602 if (timeout-- <= 0)
603 break;
604
605 udelay(10);
606 }
607
608 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
609 (unsigned int) reg, t, mask, val);
610 return -ETIMEDOUT;
611 }
612
613 static void
614 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
615 {
616 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
617 return;
618 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
619 val &= AR8216_VTUDATA_MEMBER;
620 val |= AR8216_VTUDATA_VALID;
621 priv->write(priv, AR8216_REG_VTU_DATA, val);
622 }
623 op |= AR8216_VTU_ACTIVE;
624 priv->write(priv, AR8216_REG_VTU, op);
625 }
626
627 static void
628 ar8216_vtu_flush(struct ar8xxx_priv *priv)
629 {
630 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
631 }
632
633 static void
634 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
635 {
636 u32 op;
637
638 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
639 ar8216_vtu_op(priv, op, port_mask);
640 }
641
642 static int
643 ar8216_atu_flush(struct ar8xxx_priv *priv)
644 {
645 int ret;
646
647 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
648 if (!ret)
649 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
650
651 return ret;
652 }
653
654 static u32
655 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
656 {
657 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
658 }
659
660 static void
661 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
662 u32 members, u32 pvid)
663 {
664 u32 header;
665
666 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
667 header = AR8216_PORT_CTRL_HEADER;
668 else
669 header = 0;
670
671 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
672 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
673 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
674 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
675 AR8216_PORT_CTRL_LEARN | header |
676 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
677 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
678
679 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
680 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
681 AR8216_PORT_VLAN_DEFAULT_ID,
682 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
683 (ingress << AR8216_PORT_VLAN_MODE_S) |
684 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
685 }
686
687 static int
688 ar8216_hw_init(struct ar8xxx_priv *priv)
689 {
690 return 0;
691 }
692
693 static void
694 ar8216_init_globals(struct ar8xxx_priv *priv)
695 {
696 /* standard atheros magic */
697 priv->write(priv, 0x38, 0xc000050e);
698
699 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
700 AR8216_GCTRL_MTU, 1518 + 8 + 2);
701 }
702
703 static void
704 ar8216_init_port(struct ar8xxx_priv *priv, int port)
705 {
706 /* Enable port learning and tx */
707 priv->write(priv, AR8216_REG_PORT_CTRL(port),
708 AR8216_PORT_CTRL_LEARN |
709 (4 << AR8216_PORT_CTRL_STATE_S));
710
711 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
712
713 if (port == AR8216_PORT_CPU) {
714 priv->write(priv, AR8216_REG_PORT_STATUS(port),
715 AR8216_PORT_STATUS_LINK_UP |
716 (ar8xxx_has_gige(priv) ?
717 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
718 AR8216_PORT_STATUS_TXMAC |
719 AR8216_PORT_STATUS_RXMAC |
720 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
721 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
722 AR8216_PORT_STATUS_DUPLEX);
723 } else {
724 priv->write(priv, AR8216_REG_PORT_STATUS(port),
725 AR8216_PORT_STATUS_LINK_AUTO);
726 }
727 }
728
729 static const struct ar8xxx_chip ar8216_chip = {
730 .caps = AR8XXX_CAP_MIB_COUNTERS,
731
732 .hw_init = ar8216_hw_init,
733 .init_globals = ar8216_init_globals,
734 .init_port = ar8216_init_port,
735 .setup_port = ar8216_setup_port,
736 .read_port_status = ar8216_read_port_status,
737 .atu_flush = ar8216_atu_flush,
738 .vtu_flush = ar8216_vtu_flush,
739 .vtu_load_vlan = ar8216_vtu_load_vlan,
740
741 .num_mibs = ARRAY_SIZE(ar8216_mibs),
742 .mib_decs = ar8216_mibs,
743 };
744
745 static void
746 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
747 u32 members, u32 pvid)
748 {
749 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
750 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
751 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
752 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
753 AR8216_PORT_CTRL_LEARN |
754 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
755 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
756
757 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
758 AR8236_PORT_VLAN_DEFAULT_ID,
759 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
760
761 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
762 AR8236_PORT_VLAN2_VLAN_MODE |
763 AR8236_PORT_VLAN2_MEMBER,
764 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
765 (members << AR8236_PORT_VLAN2_MEMBER_S));
766 }
767
768 static int
769 ar8236_hw_init(struct ar8xxx_priv *priv)
770 {
771 int i;
772 struct mii_bus *bus;
773
774 if (priv->initialized)
775 return 0;
776
777 /* Initialize the PHYs */
778 bus = priv->mii_bus;
779 for (i = 0; i < 5; i++) {
780 mdiobus_write(bus, i, MII_ADVERTISE,
781 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
782 ADVERTISE_PAUSE_ASYM);
783 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
784 }
785 msleep(1000);
786
787 priv->initialized = true;
788 return 0;
789 }
790
791 static void
792 ar8236_init_globals(struct ar8xxx_priv *priv)
793 {
794 /* enable jumbo frames */
795 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
796 AR8316_GCTRL_MTU, 9018 + 8 + 2);
797
798 /* Enable MIB counters */
799 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
800 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
801 AR8236_MIB_EN);
802 }
803
804 static const struct ar8xxx_chip ar8236_chip = {
805 .caps = AR8XXX_CAP_MIB_COUNTERS,
806 .hw_init = ar8236_hw_init,
807 .init_globals = ar8236_init_globals,
808 .init_port = ar8216_init_port,
809 .setup_port = ar8236_setup_port,
810 .read_port_status = ar8216_read_port_status,
811 .atu_flush = ar8216_atu_flush,
812 .vtu_flush = ar8216_vtu_flush,
813 .vtu_load_vlan = ar8216_vtu_load_vlan,
814
815 .num_mibs = ARRAY_SIZE(ar8236_mibs),
816 .mib_decs = ar8236_mibs,
817 };
818
819 static int
820 ar8316_hw_init(struct ar8xxx_priv *priv)
821 {
822 int i;
823 u32 val, newval;
824 struct mii_bus *bus;
825
826 val = priv->read(priv, AR8316_REG_POSTRIP);
827
828 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
829 if (priv->port4_phy) {
830 /* value taken from Ubiquiti RouterStation Pro */
831 newval = 0x81461bea;
832 pr_info("ar8316: Using port 4 as PHY\n");
833 } else {
834 newval = 0x01261be2;
835 pr_info("ar8316: Using port 4 as switch port\n");
836 }
837 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
838 /* value taken from AVM Fritz!Box 7390 sources */
839 newval = 0x010e5b71;
840 } else {
841 /* no known value for phy interface */
842 pr_err("ar8316: unsupported mii mode: %d.\n",
843 priv->phy->interface);
844 return -EINVAL;
845 }
846
847 if (val == newval)
848 goto out;
849
850 priv->write(priv, AR8316_REG_POSTRIP, newval);
851
852 if (priv->port4_phy &&
853 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
854 /* work around for phy4 rgmii mode */
855 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
856 /* rx delay */
857 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
858 /* tx delay */
859 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
860 msleep(1000);
861 }
862
863 /* Initialize the ports */
864 bus = priv->mii_bus;
865 for (i = 0; i < 5; i++) {
866 /* initialize the port itself */
867 mdiobus_write(bus, i, MII_ADVERTISE,
868 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
869 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
870 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
871 }
872
873 msleep(1000);
874
875 out:
876 priv->initialized = true;
877 return 0;
878 }
879
880 static void
881 ar8316_init_globals(struct ar8xxx_priv *priv)
882 {
883 /* standard atheros magic */
884 priv->write(priv, 0x38, 0xc000050e);
885
886 /* enable cpu port to receive multicast and broadcast frames */
887 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
888
889 /* enable jumbo frames */
890 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
891 AR8316_GCTRL_MTU, 9018 + 8 + 2);
892
893 /* Enable MIB counters */
894 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
895 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
896 AR8236_MIB_EN);
897 }
898
899 static const struct ar8xxx_chip ar8316_chip = {
900 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
901 .hw_init = ar8316_hw_init,
902 .init_globals = ar8316_init_globals,
903 .init_port = ar8216_init_port,
904 .setup_port = ar8216_setup_port,
905 .read_port_status = ar8216_read_port_status,
906 .atu_flush = ar8216_atu_flush,
907 .vtu_flush = ar8216_vtu_flush,
908 .vtu_load_vlan = ar8216_vtu_load_vlan,
909
910 .num_mibs = ARRAY_SIZE(ar8236_mibs),
911 .mib_decs = ar8236_mibs,
912 };
913
914 static u32
915 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
916 {
917 u32 t;
918
919 if (!cfg)
920 return 0;
921
922 t = 0;
923 switch (cfg->mode) {
924 case AR8327_PAD_NC:
925 break;
926
927 case AR8327_PAD_MAC2MAC_MII:
928 t = AR8327_PAD_MAC_MII_EN;
929 if (cfg->rxclk_sel)
930 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
931 if (cfg->txclk_sel)
932 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
933 break;
934
935 case AR8327_PAD_MAC2MAC_GMII:
936 t = AR8327_PAD_MAC_GMII_EN;
937 if (cfg->rxclk_sel)
938 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
939 if (cfg->txclk_sel)
940 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
941 break;
942
943 case AR8327_PAD_MAC_SGMII:
944 t = AR8327_PAD_SGMII_EN;
945
946 /*
947 * WAR for the QUalcomm Atheros AP136 board.
948 * It seems that RGMII TX/RX delay settings needs to be
949 * applied for SGMII mode as well, The ethernet is not
950 * reliable without this.
951 */
952 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
953 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
954 if (cfg->rxclk_delay_en)
955 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
956 if (cfg->txclk_delay_en)
957 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
958
959 if (cfg->sgmii_delay_en)
960 t |= AR8327_PAD_SGMII_DELAY_EN;
961
962 break;
963
964 case AR8327_PAD_MAC2PHY_MII:
965 t = AR8327_PAD_PHY_MII_EN;
966 if (cfg->rxclk_sel)
967 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
968 if (cfg->txclk_sel)
969 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
970 break;
971
972 case AR8327_PAD_MAC2PHY_GMII:
973 t = AR8327_PAD_PHY_GMII_EN;
974 if (cfg->pipe_rxclk_sel)
975 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
976 if (cfg->rxclk_sel)
977 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
978 if (cfg->txclk_sel)
979 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
980 break;
981
982 case AR8327_PAD_MAC_RGMII:
983 t = AR8327_PAD_RGMII_EN;
984 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
985 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
986 if (cfg->rxclk_delay_en)
987 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
988 if (cfg->txclk_delay_en)
989 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
990 break;
991
992 case AR8327_PAD_PHY_GMII:
993 t = AR8327_PAD_PHYX_GMII_EN;
994 break;
995
996 case AR8327_PAD_PHY_RGMII:
997 t = AR8327_PAD_PHYX_RGMII_EN;
998 break;
999
1000 case AR8327_PAD_PHY_MII:
1001 t = AR8327_PAD_PHYX_MII_EN;
1002 break;
1003 }
1004
1005 return t;
1006 }
1007
1008 static void
1009 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1010 {
1011 switch (priv->chip_rev) {
1012 case 1:
1013 /* For 100M waveform */
1014 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1015 /* Turn on Gigabit clock */
1016 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1017 break;
1018
1019 case 2:
1020 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1021 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1022 /* fallthrough */
1023 case 4:
1024 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1025 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1026
1027 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1028 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1029 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1030 break;
1031 }
1032 }
1033
1034 static u32
1035 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1036 {
1037 u32 t;
1038
1039 if (!cfg->force_link)
1040 return AR8216_PORT_STATUS_LINK_AUTO;
1041
1042 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1043 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1044 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1045 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1046
1047 switch (cfg->speed) {
1048 case AR8327_PORT_SPEED_10:
1049 t |= AR8216_PORT_SPEED_10M;
1050 break;
1051 case AR8327_PORT_SPEED_100:
1052 t |= AR8216_PORT_SPEED_100M;
1053 break;
1054 case AR8327_PORT_SPEED_1000:
1055 t |= AR8216_PORT_SPEED_1000M;
1056 break;
1057 }
1058
1059 return t;
1060 }
1061
1062 static int
1063 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1064 struct ar8327_platform_data *pdata)
1065 {
1066 struct ar8327_led_cfg *led_cfg;
1067 struct ar8327_data *data;
1068 u32 pos, new_pos;
1069 u32 t;
1070
1071 if (!pdata)
1072 return -EINVAL;
1073
1074 priv->get_port_link = pdata->get_port_link;
1075
1076 data = &priv->chip_data.ar8327;
1077
1078 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1079 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1080
1081 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1082 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1083 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1084 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1085 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1086 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1087
1088 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1089 new_pos = pos;
1090
1091 led_cfg = pdata->led_cfg;
1092 if (led_cfg) {
1093 if (led_cfg->open_drain)
1094 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1095 else
1096 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1097
1098 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1099 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1100 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1101 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1102 }
1103
1104 if (new_pos != pos) {
1105 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1106 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1107 }
1108
1109 return 0;
1110 }
1111
1112 #ifdef CONFIG_OF
1113 static int
1114 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1115 {
1116 const __be32 *paddr;
1117 int len;
1118 int i;
1119
1120 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1121 if (!paddr || len < (2 * sizeof(*paddr)))
1122 return -EINVAL;
1123
1124 len /= sizeof(*paddr);
1125
1126 for (i = 0; i < len - 1; i += 2) {
1127 u32 reg;
1128 u32 val;
1129
1130 reg = be32_to_cpup(paddr + i);
1131 val = be32_to_cpup(paddr + i + 1);
1132
1133 switch (reg) {
1134 case AR8327_REG_PORT_STATUS(0):
1135 priv->chip_data.ar8327.port0_status = val;
1136 break;
1137 case AR8327_REG_PORT_STATUS(6):
1138 priv->chip_data.ar8327.port6_status = val;
1139 break;
1140 default:
1141 priv->write(priv, reg, val);
1142 break;
1143 }
1144 }
1145
1146 return 0;
1147 }
1148 #else
1149 static inline int
1150 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1151 {
1152 return -EINVAL;
1153 }
1154 #endif
1155
1156 static int
1157 ar8327_hw_init(struct ar8xxx_priv *priv)
1158 {
1159 struct mii_bus *bus;
1160 int ret;
1161 int i;
1162
1163 if (priv->phy->dev.of_node)
1164 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1165 else
1166 ret = ar8327_hw_config_pdata(priv,
1167 priv->phy->dev.platform_data);
1168
1169 if (ret)
1170 return ret;
1171
1172 bus = priv->mii_bus;
1173 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1174 ar8327_phy_fixup(priv, i);
1175
1176 /* start aneg on the PHY */
1177 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1178 ADVERTISE_PAUSE_CAP |
1179 ADVERTISE_PAUSE_ASYM);
1180 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1181 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1182 }
1183
1184 msleep(1000);
1185
1186 return 0;
1187 }
1188
1189 static void
1190 ar8327_init_globals(struct ar8xxx_priv *priv)
1191 {
1192 u32 t;
1193
1194 /* enable CPU port and disable mirror port */
1195 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1196 AR8327_FWD_CTRL0_MIRROR_PORT;
1197 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1198
1199 /* forward multicast and broadcast frames to CPU */
1200 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1201 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1202 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1203 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1204
1205 /* setup MTU */
1206 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1207 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1208
1209 /* Enable MIB counters */
1210 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1211 AR8327_MODULE_EN_MIB);
1212 }
1213
1214 static void
1215 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1216 {
1217 u32 t;
1218
1219 if (port == AR8216_PORT_CPU)
1220 t = priv->chip_data.ar8327.port0_status;
1221 else if (port == 6)
1222 t = priv->chip_data.ar8327.port6_status;
1223 else
1224 t = AR8216_PORT_STATUS_LINK_AUTO;
1225
1226 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1227 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1228
1229 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1230 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1231 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1232
1233 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1234 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1235
1236 t = AR8327_PORT_LOOKUP_LEARN;
1237 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1238 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1239 }
1240
1241 static u32
1242 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1243 {
1244 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1245 }
1246
1247 static int
1248 ar8327_atu_flush(struct ar8xxx_priv *priv)
1249 {
1250 int ret;
1251
1252 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1253 AR8327_ATU_FUNC_BUSY, 0);
1254 if (!ret)
1255 priv->write(priv, AR8327_REG_ATU_FUNC,
1256 AR8327_ATU_FUNC_OP_FLUSH);
1257
1258 return ret;
1259 }
1260
1261 static void
1262 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1263 {
1264 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1265 AR8327_VTU_FUNC1_BUSY, 0))
1266 return;
1267
1268 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1269 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1270
1271 op |= AR8327_VTU_FUNC1_BUSY;
1272 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1273 }
1274
1275 static void
1276 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1277 {
1278 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1279 }
1280
1281 static void
1282 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1283 {
1284 u32 op;
1285 u32 val;
1286 int i;
1287
1288 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1289 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1290 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1291 u32 mode;
1292
1293 if ((port_mask & BIT(i)) == 0)
1294 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1295 else if (priv->vlan == 0)
1296 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1297 else if (priv->vlan_tagged & BIT(i))
1298 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1299 else
1300 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1301
1302 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1303 }
1304 ar8327_vtu_op(priv, op, val);
1305 }
1306
1307 static void
1308 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1309 u32 members, u32 pvid)
1310 {
1311 u32 t;
1312 u32 mode;
1313
1314 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1315 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1316 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1317
1318 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1319 switch (egress) {
1320 case AR8216_OUT_KEEP:
1321 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1322 break;
1323 case AR8216_OUT_STRIP_VLAN:
1324 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1325 break;
1326 case AR8216_OUT_ADD_VLAN:
1327 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1328 break;
1329 }
1330
1331 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1332 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1333 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1334
1335 t = members;
1336 t |= AR8327_PORT_LOOKUP_LEARN;
1337 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1338 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1339 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1340 }
1341
1342 static const struct ar8xxx_chip ar8327_chip = {
1343 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1344 .hw_init = ar8327_hw_init,
1345 .init_globals = ar8327_init_globals,
1346 .init_port = ar8327_init_port,
1347 .setup_port = ar8327_setup_port,
1348 .read_port_status = ar8327_read_port_status,
1349 .atu_flush = ar8327_atu_flush,
1350 .vtu_flush = ar8327_vtu_flush,
1351 .vtu_load_vlan = ar8327_vtu_load_vlan,
1352
1353 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1354 .mib_decs = ar8236_mibs,
1355 };
1356
1357 static int
1358 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1359 struct switch_val *val)
1360 {
1361 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1362 priv->vlan = !!val->value.i;
1363 return 0;
1364 }
1365
1366 static int
1367 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1368 struct switch_val *val)
1369 {
1370 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1371 val->value.i = priv->vlan;
1372 return 0;
1373 }
1374
1375
1376 static int
1377 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1378 {
1379 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1380
1381 /* make sure no invalid PVIDs get set */
1382
1383 if (vlan >= dev->vlans)
1384 return -EINVAL;
1385
1386 priv->pvid[port] = vlan;
1387 return 0;
1388 }
1389
1390 static int
1391 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1392 {
1393 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1394 *vlan = priv->pvid[port];
1395 return 0;
1396 }
1397
1398 static int
1399 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1400 struct switch_val *val)
1401 {
1402 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1403 priv->vlan_id[val->port_vlan] = val->value.i;
1404 return 0;
1405 }
1406
1407 static int
1408 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1409 struct switch_val *val)
1410 {
1411 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1412 val->value.i = priv->vlan_id[val->port_vlan];
1413 return 0;
1414 }
1415
1416 static int
1417 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1418 struct switch_port_link *link)
1419 {
1420 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1421
1422 ar8216_read_port_link(priv, port, link);
1423 return 0;
1424 }
1425
1426 static int
1427 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1428 {
1429 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1430 u8 ports = priv->vlan_table[val->port_vlan];
1431 int i;
1432
1433 val->len = 0;
1434 for (i = 0; i < dev->ports; i++) {
1435 struct switch_port *p;
1436
1437 if (!(ports & (1 << i)))
1438 continue;
1439
1440 p = &val->value.ports[val->len++];
1441 p->id = i;
1442 if (priv->vlan_tagged & (1 << i))
1443 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1444 else
1445 p->flags = 0;
1446 }
1447 return 0;
1448 }
1449
1450 static int
1451 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1452 {
1453 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1454 u8 *vt = &priv->vlan_table[val->port_vlan];
1455 int i, j;
1456
1457 *vt = 0;
1458 for (i = 0; i < val->len; i++) {
1459 struct switch_port *p = &val->value.ports[i];
1460
1461 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1462 priv->vlan_tagged |= (1 << p->id);
1463 } else {
1464 priv->vlan_tagged &= ~(1 << p->id);
1465 priv->pvid[p->id] = val->port_vlan;
1466
1467 /* make sure that an untagged port does not
1468 * appear in other vlans */
1469 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1470 if (j == val->port_vlan)
1471 continue;
1472 priv->vlan_table[j] &= ~(1 << p->id);
1473 }
1474 }
1475
1476 *vt |= 1 << p->id;
1477 }
1478 return 0;
1479 }
1480
1481 static void
1482 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1483 {
1484 int port;
1485
1486 /* reset all mirror registers */
1487 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1488 AR8327_FWD_CTRL0_MIRROR_PORT,
1489 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1490 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1491 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1492 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1493 0);
1494
1495 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1496 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1497 0);
1498 }
1499
1500 /* now enable mirroring if necessary */
1501 if (priv->source_port >= AR8327_NUM_PORTS ||
1502 priv->monitor_port >= AR8327_NUM_PORTS ||
1503 priv->source_port == priv->monitor_port) {
1504 return;
1505 }
1506
1507 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1508 AR8327_FWD_CTRL0_MIRROR_PORT,
1509 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1510
1511 if (priv->mirror_rx)
1512 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1513 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1514 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1515
1516 if (priv->mirror_tx)
1517 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1518 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1519 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1520 }
1521
1522 static void
1523 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1524 {
1525 int port;
1526
1527 /* reset all mirror registers */
1528 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1529 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1530 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1531 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1532 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1533 AR8216_PORT_CTRL_MIRROR_RX,
1534 0);
1535
1536 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1537 AR8216_PORT_CTRL_MIRROR_TX,
1538 0);
1539 }
1540
1541 /* now enable mirroring if necessary */
1542 if (priv->source_port >= AR8216_NUM_PORTS ||
1543 priv->monitor_port >= AR8216_NUM_PORTS ||
1544 priv->source_port == priv->monitor_port) {
1545 return;
1546 }
1547
1548 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1549 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1550 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1551
1552 if (priv->mirror_rx)
1553 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1554 AR8216_PORT_CTRL_MIRROR_RX,
1555 AR8216_PORT_CTRL_MIRROR_RX);
1556
1557 if (priv->mirror_tx)
1558 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1559 AR8216_PORT_CTRL_MIRROR_TX,
1560 AR8216_PORT_CTRL_MIRROR_TX);
1561 }
1562
1563 static void
1564 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1565 {
1566 if (chip_is_ar8327(priv)) {
1567 ar8327_set_mirror_regs(priv);
1568 } else {
1569 ar8216_set_mirror_regs(priv);
1570 }
1571 }
1572
1573 static int
1574 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1575 {
1576 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1577 u8 portmask[AR8X16_MAX_PORTS];
1578 int i, j;
1579
1580 mutex_lock(&priv->reg_mutex);
1581 /* flush all vlan translation unit entries */
1582 priv->chip->vtu_flush(priv);
1583
1584 memset(portmask, 0, sizeof(portmask));
1585 if (!priv->init) {
1586 /* calculate the port destination masks and load vlans
1587 * into the vlan translation unit */
1588 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1589 u8 vp = priv->vlan_table[j];
1590
1591 if (!vp)
1592 continue;
1593
1594 for (i = 0; i < dev->ports; i++) {
1595 u8 mask = (1 << i);
1596 if (vp & mask)
1597 portmask[i] |= vp & ~mask;
1598 }
1599
1600 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1601 priv->vlan_table[j]);
1602 }
1603 } else {
1604 /* vlan disabled:
1605 * isolate all ports, but connect them to the cpu port */
1606 for (i = 0; i < dev->ports; i++) {
1607 if (i == AR8216_PORT_CPU)
1608 continue;
1609
1610 portmask[i] = 1 << AR8216_PORT_CPU;
1611 portmask[AR8216_PORT_CPU] |= (1 << i);
1612 }
1613 }
1614
1615 /* update the port destination mask registers and tag settings */
1616 for (i = 0; i < dev->ports; i++) {
1617 int egress, ingress;
1618 int pvid;
1619
1620 if (priv->vlan) {
1621 pvid = priv->vlan_id[priv->pvid[i]];
1622 if (priv->vlan_tagged & (1 << i))
1623 egress = AR8216_OUT_ADD_VLAN;
1624 else
1625 egress = AR8216_OUT_STRIP_VLAN;
1626 ingress = AR8216_IN_SECURE;
1627 } else {
1628 pvid = i;
1629 egress = AR8216_OUT_KEEP;
1630 ingress = AR8216_IN_PORT_ONLY;
1631 }
1632
1633 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1634 pvid);
1635 }
1636
1637 ar8xxx_set_mirror_regs(priv);
1638
1639 mutex_unlock(&priv->reg_mutex);
1640 return 0;
1641 }
1642
1643 static int
1644 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1645 {
1646 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1647 int i;
1648
1649 mutex_lock(&priv->reg_mutex);
1650 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1651 offsetof(struct ar8xxx_priv, vlan));
1652
1653 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1654 priv->vlan_id[i] = i;
1655
1656 /* Configure all ports */
1657 for (i = 0; i < dev->ports; i++)
1658 priv->chip->init_port(priv, i);
1659
1660 priv->mirror_rx = false;
1661 priv->mirror_tx = false;
1662 priv->source_port = 0;
1663 priv->monitor_port = 0;
1664
1665 priv->chip->init_globals(priv);
1666
1667 mutex_unlock(&priv->reg_mutex);
1668
1669 return ar8xxx_sw_hw_apply(dev);
1670 }
1671
1672 static int
1673 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1674 const struct switch_attr *attr,
1675 struct switch_val *val)
1676 {
1677 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1678 unsigned int len;
1679 int ret;
1680
1681 if (!ar8xxx_has_mib_counters(priv))
1682 return -EOPNOTSUPP;
1683
1684 mutex_lock(&priv->mib_lock);
1685
1686 len = priv->dev.ports * priv->chip->num_mibs *
1687 sizeof(*priv->mib_stats);
1688 memset(priv->mib_stats, '\0', len);
1689 ret = ar8xxx_mib_flush(priv);
1690 if (ret)
1691 goto unlock;
1692
1693 ret = 0;
1694
1695 unlock:
1696 mutex_unlock(&priv->mib_lock);
1697 return ret;
1698 }
1699
1700 static int
1701 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1702 const struct switch_attr *attr,
1703 struct switch_val *val)
1704 {
1705 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1706
1707 mutex_lock(&priv->reg_mutex);
1708 priv->mirror_rx = !!val->value.i;
1709 ar8xxx_set_mirror_regs(priv);
1710 mutex_unlock(&priv->reg_mutex);
1711
1712 return 0;
1713 }
1714
1715 static int
1716 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1717 const struct switch_attr *attr,
1718 struct switch_val *val)
1719 {
1720 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1721 val->value.i = priv->mirror_rx;
1722 return 0;
1723 }
1724
1725 static int
1726 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1727 const struct switch_attr *attr,
1728 struct switch_val *val)
1729 {
1730 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1731
1732 mutex_lock(&priv->reg_mutex);
1733 priv->mirror_tx = !!val->value.i;
1734 ar8xxx_set_mirror_regs(priv);
1735 mutex_unlock(&priv->reg_mutex);
1736
1737 return 0;
1738 }
1739
1740 static int
1741 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1742 const struct switch_attr *attr,
1743 struct switch_val *val)
1744 {
1745 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1746 val->value.i = priv->mirror_tx;
1747 return 0;
1748 }
1749
1750 static int
1751 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1752 const struct switch_attr *attr,
1753 struct switch_val *val)
1754 {
1755 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1756
1757 mutex_lock(&priv->reg_mutex);
1758 priv->monitor_port = val->value.i;
1759 ar8xxx_set_mirror_regs(priv);
1760 mutex_unlock(&priv->reg_mutex);
1761
1762 return 0;
1763 }
1764
1765 static int
1766 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1767 const struct switch_attr *attr,
1768 struct switch_val *val)
1769 {
1770 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1771 val->value.i = priv->monitor_port;
1772 return 0;
1773 }
1774
1775 static int
1776 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1777 const struct switch_attr *attr,
1778 struct switch_val *val)
1779 {
1780 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1781
1782 mutex_lock(&priv->reg_mutex);
1783 priv->source_port = val->value.i;
1784 ar8xxx_set_mirror_regs(priv);
1785 mutex_unlock(&priv->reg_mutex);
1786
1787 return 0;
1788 }
1789
1790 static int
1791 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1792 const struct switch_attr *attr,
1793 struct switch_val *val)
1794 {
1795 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1796 val->value.i = priv->source_port;
1797 return 0;
1798 }
1799
1800 static int
1801 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1802 const struct switch_attr *attr,
1803 struct switch_val *val)
1804 {
1805 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1806 int port;
1807 int ret;
1808
1809 if (!ar8xxx_has_mib_counters(priv))
1810 return -EOPNOTSUPP;
1811
1812 port = val->port_vlan;
1813 if (port >= dev->ports)
1814 return -EINVAL;
1815
1816 mutex_lock(&priv->mib_lock);
1817 ret = ar8xxx_mib_capture(priv);
1818 if (ret)
1819 goto unlock;
1820
1821 ar8xxx_mib_fetch_port_stat(priv, port, true);
1822
1823 ret = 0;
1824
1825 unlock:
1826 mutex_unlock(&priv->mib_lock);
1827 return ret;
1828 }
1829
1830 static int
1831 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1832 const struct switch_attr *attr,
1833 struct switch_val *val)
1834 {
1835 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1836 const struct ar8xxx_chip *chip = priv->chip;
1837 u64 *mib_stats;
1838 int port;
1839 int ret;
1840 char *buf = priv->buf;
1841 int i, len = 0;
1842
1843 if (!ar8xxx_has_mib_counters(priv))
1844 return -EOPNOTSUPP;
1845
1846 port = val->port_vlan;
1847 if (port >= dev->ports)
1848 return -EINVAL;
1849
1850 mutex_lock(&priv->mib_lock);
1851 ret = ar8xxx_mib_capture(priv);
1852 if (ret)
1853 goto unlock;
1854
1855 ar8xxx_mib_fetch_port_stat(priv, port, false);
1856
1857 len += snprintf(buf + len, sizeof(priv->buf) - len,
1858 "Port %d MIB counters\n",
1859 port);
1860
1861 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1862 for (i = 0; i < chip->num_mibs; i++)
1863 len += snprintf(buf + len, sizeof(priv->buf) - len,
1864 "%-12s: %llu\n",
1865 chip->mib_decs[i].name,
1866 mib_stats[i]);
1867
1868 val->value.s = buf;
1869 val->len = len;
1870
1871 ret = 0;
1872
1873 unlock:
1874 mutex_unlock(&priv->mib_lock);
1875 return ret;
1876 }
1877
1878 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1879 {
1880 .type = SWITCH_TYPE_INT,
1881 .name = "enable_vlan",
1882 .description = "Enable VLAN mode",
1883 .set = ar8xxx_sw_set_vlan,
1884 .get = ar8xxx_sw_get_vlan,
1885 .max = 1
1886 },
1887 {
1888 .type = SWITCH_TYPE_NOVAL,
1889 .name = "reset_mibs",
1890 .description = "Reset all MIB counters",
1891 .set = ar8xxx_sw_set_reset_mibs,
1892 },
1893 {
1894 .type = SWITCH_TYPE_INT,
1895 .name = "enable_mirror_rx",
1896 .description = "Enable mirroring of RX packets",
1897 .set = ar8xxx_sw_set_mirror_rx_enable,
1898 .get = ar8xxx_sw_get_mirror_rx_enable,
1899 .max = 1
1900 },
1901 {
1902 .type = SWITCH_TYPE_INT,
1903 .name = "enable_mirror_tx",
1904 .description = "Enable mirroring of TX packets",
1905 .set = ar8xxx_sw_set_mirror_tx_enable,
1906 .get = ar8xxx_sw_get_mirror_tx_enable,
1907 .max = 1
1908 },
1909 {
1910 .type = SWITCH_TYPE_INT,
1911 .name = "mirror_monitor_port",
1912 .description = "Mirror monitor port",
1913 .set = ar8xxx_sw_set_mirror_monitor_port,
1914 .get = ar8xxx_sw_get_mirror_monitor_port,
1915 .max = AR8216_NUM_PORTS - 1
1916 },
1917 {
1918 .type = SWITCH_TYPE_INT,
1919 .name = "mirror_source_port",
1920 .description = "Mirror source port",
1921 .set = ar8xxx_sw_set_mirror_source_port,
1922 .get = ar8xxx_sw_get_mirror_source_port,
1923 .max = AR8216_NUM_PORTS - 1
1924 },
1925 };
1926
1927 static struct switch_attr ar8327_sw_attr_globals[] = {
1928 {
1929 .type = SWITCH_TYPE_INT,
1930 .name = "enable_vlan",
1931 .description = "Enable VLAN mode",
1932 .set = ar8xxx_sw_set_vlan,
1933 .get = ar8xxx_sw_get_vlan,
1934 .max = 1
1935 },
1936 {
1937 .type = SWITCH_TYPE_NOVAL,
1938 .name = "reset_mibs",
1939 .description = "Reset all MIB counters",
1940 .set = ar8xxx_sw_set_reset_mibs,
1941 },
1942 {
1943 .type = SWITCH_TYPE_INT,
1944 .name = "enable_mirror_rx",
1945 .description = "Enable mirroring of RX packets",
1946 .set = ar8xxx_sw_set_mirror_rx_enable,
1947 .get = ar8xxx_sw_get_mirror_rx_enable,
1948 .max = 1
1949 },
1950 {
1951 .type = SWITCH_TYPE_INT,
1952 .name = "enable_mirror_tx",
1953 .description = "Enable mirroring of TX packets",
1954 .set = ar8xxx_sw_set_mirror_tx_enable,
1955 .get = ar8xxx_sw_get_mirror_tx_enable,
1956 .max = 1
1957 },
1958 {
1959 .type = SWITCH_TYPE_INT,
1960 .name = "mirror_monitor_port",
1961 .description = "Mirror monitor port",
1962 .set = ar8xxx_sw_set_mirror_monitor_port,
1963 .get = ar8xxx_sw_get_mirror_monitor_port,
1964 .max = AR8327_NUM_PORTS - 1
1965 },
1966 {
1967 .type = SWITCH_TYPE_INT,
1968 .name = "mirror_source_port",
1969 .description = "Mirror source port",
1970 .set = ar8xxx_sw_set_mirror_source_port,
1971 .get = ar8xxx_sw_get_mirror_source_port,
1972 .max = AR8327_NUM_PORTS - 1
1973 },
1974 };
1975
1976 static struct switch_attr ar8xxx_sw_attr_port[] = {
1977 {
1978 .type = SWITCH_TYPE_NOVAL,
1979 .name = "reset_mib",
1980 .description = "Reset single port MIB counters",
1981 .set = ar8xxx_sw_set_port_reset_mib,
1982 },
1983 {
1984 .type = SWITCH_TYPE_STRING,
1985 .name = "mib",
1986 .description = "Get port's MIB counters",
1987 .set = NULL,
1988 .get = ar8xxx_sw_get_port_mib,
1989 },
1990 };
1991
1992 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1993 {
1994 .type = SWITCH_TYPE_INT,
1995 .name = "vid",
1996 .description = "VLAN ID (0-4094)",
1997 .set = ar8xxx_sw_set_vid,
1998 .get = ar8xxx_sw_get_vid,
1999 .max = 4094,
2000 },
2001 };
2002
2003 static const struct switch_dev_ops ar8xxx_sw_ops = {
2004 .attr_global = {
2005 .attr = ar8xxx_sw_attr_globals,
2006 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2007 },
2008 .attr_port = {
2009 .attr = ar8xxx_sw_attr_port,
2010 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2011 },
2012 .attr_vlan = {
2013 .attr = ar8xxx_sw_attr_vlan,
2014 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2015 },
2016 .get_port_pvid = ar8xxx_sw_get_pvid,
2017 .set_port_pvid = ar8xxx_sw_set_pvid,
2018 .get_vlan_ports = ar8xxx_sw_get_ports,
2019 .set_vlan_ports = ar8xxx_sw_set_ports,
2020 .apply_config = ar8xxx_sw_hw_apply,
2021 .reset_switch = ar8xxx_sw_reset_switch,
2022 .get_port_link = ar8xxx_sw_get_port_link,
2023 };
2024
2025 static const struct switch_dev_ops ar8327_sw_ops = {
2026 .attr_global = {
2027 .attr = ar8327_sw_attr_globals,
2028 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2029 },
2030 .attr_port = {
2031 .attr = ar8xxx_sw_attr_port,
2032 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2033 },
2034 .attr_vlan = {
2035 .attr = ar8xxx_sw_attr_vlan,
2036 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2037 },
2038 .get_port_pvid = ar8xxx_sw_get_pvid,
2039 .set_port_pvid = ar8xxx_sw_set_pvid,
2040 .get_vlan_ports = ar8xxx_sw_get_ports,
2041 .set_vlan_ports = ar8xxx_sw_set_ports,
2042 .apply_config = ar8xxx_sw_hw_apply,
2043 .reset_switch = ar8xxx_sw_reset_switch,
2044 .get_port_link = ar8xxx_sw_get_port_link,
2045 };
2046
2047 static int
2048 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2049 {
2050 u32 val;
2051 u16 id;
2052 int i;
2053
2054 val = priv->read(priv, AR8216_REG_CTRL);
2055 if (val == ~0)
2056 return -ENODEV;
2057
2058 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2059 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2060 u16 t;
2061
2062 val = priv->read(priv, AR8216_REG_CTRL);
2063 if (val == ~0)
2064 return -ENODEV;
2065
2066 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2067 if (t != id)
2068 return -ENODEV;
2069 }
2070
2071 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2072 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2073
2074 switch (priv->chip_ver) {
2075 case AR8XXX_VER_AR8216:
2076 priv->chip = &ar8216_chip;
2077 break;
2078 case AR8XXX_VER_AR8236:
2079 priv->chip = &ar8236_chip;
2080 break;
2081 case AR8XXX_VER_AR8316:
2082 priv->chip = &ar8316_chip;
2083 break;
2084 case AR8XXX_VER_AR8327:
2085 priv->mii_lo_first = true;
2086 priv->chip = &ar8327_chip;
2087 break;
2088 default:
2089 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2090 priv->chip_ver, priv->chip_rev);
2091
2092 return -ENODEV;
2093 }
2094
2095 return 0;
2096 }
2097
2098 static void
2099 ar8xxx_mib_work_func(struct work_struct *work)
2100 {
2101 struct ar8xxx_priv *priv;
2102 int err;
2103
2104 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2105
2106 mutex_lock(&priv->mib_lock);
2107
2108 err = ar8xxx_mib_capture(priv);
2109 if (err)
2110 goto next_port;
2111
2112 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2113
2114 next_port:
2115 priv->mib_next_port++;
2116 if (priv->mib_next_port >= priv->dev.ports)
2117 priv->mib_next_port = 0;
2118
2119 mutex_unlock(&priv->mib_lock);
2120 schedule_delayed_work(&priv->mib_work,
2121 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2122 }
2123
2124 static int
2125 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2126 {
2127 unsigned int len;
2128
2129 if (!ar8xxx_has_mib_counters(priv))
2130 return 0;
2131
2132 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2133
2134 len = priv->dev.ports * priv->chip->num_mibs *
2135 sizeof(*priv->mib_stats);
2136 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2137
2138 if (!priv->mib_stats)
2139 return -ENOMEM;
2140
2141 return 0;
2142 }
2143
2144 static void
2145 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2146 {
2147 if (!ar8xxx_has_mib_counters(priv))
2148 return;
2149
2150 schedule_delayed_work(&priv->mib_work,
2151 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2152 }
2153
2154 static void
2155 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2156 {
2157 if (!ar8xxx_has_mib_counters(priv))
2158 return;
2159
2160 cancel_delayed_work(&priv->mib_work);
2161 }
2162
2163 static struct ar8xxx_priv *
2164 ar8xxx_create(void)
2165 {
2166 struct ar8xxx_priv *priv;
2167
2168 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2169 if (priv == NULL)
2170 return NULL;
2171
2172 mutex_init(&priv->reg_mutex);
2173 mutex_init(&priv->mib_lock);
2174 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2175
2176 return priv;
2177 }
2178
2179 static void
2180 ar8xxx_free(struct ar8xxx_priv *priv)
2181 {
2182 kfree(priv->mib_stats);
2183 kfree(priv);
2184 }
2185
2186 static struct ar8xxx_priv *
2187 ar8xxx_create_mii(struct mii_bus *bus)
2188 {
2189 struct ar8xxx_priv *priv;
2190
2191 priv = ar8xxx_create();
2192 if (priv) {
2193 priv->mii_bus = bus;
2194 priv->read = ar8xxx_mii_read;
2195 priv->write = ar8xxx_mii_write;
2196 }
2197
2198 return priv;
2199 }
2200
2201 static int
2202 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2203 {
2204 struct switch_dev *swdev;
2205 int ret;
2206
2207 ret = ar8xxx_id_chip(priv);
2208 if (ret)
2209 return ret;
2210
2211 swdev = &priv->dev;
2212 swdev->cpu_port = AR8216_PORT_CPU;
2213 swdev->ops = &ar8xxx_sw_ops;
2214
2215 if (chip_is_ar8316(priv)) {
2216 swdev->name = "Atheros AR8316";
2217 swdev->vlans = AR8X16_MAX_VLANS;
2218 swdev->ports = AR8216_NUM_PORTS;
2219 } else if (chip_is_ar8236(priv)) {
2220 swdev->name = "Atheros AR8236";
2221 swdev->vlans = AR8216_NUM_VLANS;
2222 swdev->ports = AR8216_NUM_PORTS;
2223 } else if (chip_is_ar8327(priv)) {
2224 swdev->name = "Atheros AR8327";
2225 swdev->vlans = AR8X16_MAX_VLANS;
2226 swdev->ports = AR8327_NUM_PORTS;
2227 swdev->ops = &ar8327_sw_ops;
2228 } else {
2229 swdev->name = "Atheros AR8216";
2230 swdev->vlans = AR8216_NUM_VLANS;
2231 swdev->ports = AR8216_NUM_PORTS;
2232 }
2233
2234 ret = ar8xxx_mib_init(priv);
2235 if (ret)
2236 return ret;
2237
2238 return 0;
2239 }
2240
2241 static int
2242 ar8xxx_start(struct ar8xxx_priv *priv)
2243 {
2244 int ret;
2245
2246 priv->init = true;
2247
2248 ret = priv->chip->hw_init(priv);
2249 if (ret)
2250 return ret;
2251
2252 ret = ar8xxx_sw_reset_switch(&priv->dev);
2253 if (ret)
2254 return ret;
2255
2256 priv->init = false;
2257
2258 ar8xxx_mib_start(priv);
2259
2260 return 0;
2261 }
2262
2263 static int
2264 ar8xxx_phy_config_init(struct phy_device *phydev)
2265 {
2266 struct ar8xxx_priv *priv = phydev->priv;
2267 struct net_device *dev = phydev->attached_dev;
2268 int ret;
2269
2270 if (WARN_ON(!priv))
2271 return -ENODEV;
2272
2273 if (chip_is_ar8327(priv))
2274 return 0;
2275
2276 priv->phy = phydev;
2277
2278 if (phydev->addr != 0) {
2279 if (chip_is_ar8316(priv)) {
2280 /* switch device has been initialized, reinit */
2281 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2282 priv->initialized = false;
2283 priv->port4_phy = true;
2284 ar8316_hw_init(priv);
2285 return 0;
2286 }
2287
2288 return 0;
2289 }
2290
2291 ret = ar8xxx_start(priv);
2292 if (ret)
2293 return ret;
2294
2295 /* VID fixup only needed on ar8216 */
2296 if (chip_is_ar8216(priv)) {
2297 dev->phy_ptr = priv;
2298 dev->priv_flags |= IFF_NO_IP_ALIGN;
2299 dev->eth_mangle_rx = ar8216_mangle_rx;
2300 dev->eth_mangle_tx = ar8216_mangle_tx;
2301 }
2302
2303 return 0;
2304 }
2305
2306 static int
2307 ar8xxx_phy_read_status(struct phy_device *phydev)
2308 {
2309 struct ar8xxx_priv *priv = phydev->priv;
2310 struct switch_port_link link;
2311 int ret;
2312
2313 if (phydev->addr != 0)
2314 return genphy_read_status(phydev);
2315
2316 ar8216_read_port_link(priv, phydev->addr, &link);
2317 phydev->link = !!link.link;
2318 if (!phydev->link)
2319 return 0;
2320
2321 switch (link.speed) {
2322 case SWITCH_PORT_SPEED_10:
2323 phydev->speed = SPEED_10;
2324 break;
2325 case SWITCH_PORT_SPEED_100:
2326 phydev->speed = SPEED_100;
2327 break;
2328 case SWITCH_PORT_SPEED_1000:
2329 phydev->speed = SPEED_1000;
2330 break;
2331 default:
2332 phydev->speed = 0;
2333 }
2334 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2335
2336 /* flush the address translation unit */
2337 mutex_lock(&priv->reg_mutex);
2338 ret = priv->chip->atu_flush(priv);
2339 mutex_unlock(&priv->reg_mutex);
2340
2341 phydev->state = PHY_RUNNING;
2342 netif_carrier_on(phydev->attached_dev);
2343 phydev->adjust_link(phydev->attached_dev);
2344
2345 return ret;
2346 }
2347
2348 static int
2349 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2350 {
2351 if (phydev->addr == 0)
2352 return 0;
2353
2354 return genphy_config_aneg(phydev);
2355 }
2356
2357 static const u32 ar8xxx_phy_ids[] = {
2358 0x004dd033,
2359 0x004dd034,
2360 0x004dd041,
2361 0x004dd042,
2362 };
2363
2364 static bool
2365 ar8xxx_phy_match(u32 phy_id)
2366 {
2367 int i;
2368
2369 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2370 if (phy_id == ar8xxx_phy_ids[i])
2371 return true;
2372
2373 return false;
2374 }
2375
2376 static bool
2377 ar8xxx_is_possible(struct mii_bus *bus)
2378 {
2379 unsigned i;
2380
2381 for (i = 0; i < 4; i++) {
2382 u32 phy_id;
2383
2384 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2385 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2386 if (!ar8xxx_phy_match(phy_id)) {
2387 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2388 dev_name(&bus->dev), i, phy_id);
2389 return false;
2390 }
2391 }
2392
2393 return true;
2394 }
2395
2396 static int
2397 ar8xxx_phy_probe(struct phy_device *phydev)
2398 {
2399 struct ar8xxx_priv *priv;
2400 struct switch_dev *swdev;
2401 int ret;
2402
2403 /* skip PHYs at unused adresses */
2404 if (phydev->addr != 0 && phydev->addr != 4)
2405 return -ENODEV;
2406
2407 if (!ar8xxx_is_possible(phydev->bus))
2408 return -ENODEV;
2409
2410 mutex_lock(&ar8xxx_dev_list_lock);
2411 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2412 if (priv->mii_bus == phydev->bus)
2413 goto found;
2414
2415 priv = ar8xxx_create_mii(phydev->bus);
2416 if (priv == NULL) {
2417 ret = -ENOMEM;
2418 goto unlock;
2419 }
2420
2421 ret = ar8xxx_probe_switch(priv);
2422 if (ret)
2423 goto free_priv;
2424
2425 swdev = &priv->dev;
2426 swdev->alias = dev_name(&priv->mii_bus->dev);
2427 ret = register_switch(swdev, NULL);
2428 if (ret)
2429 goto free_priv;
2430
2431 pr_info("%s: %s rev. %u switch registered on %s\n",
2432 swdev->devname, swdev->name, priv->chip_rev,
2433 dev_name(&priv->mii_bus->dev));
2434
2435 found:
2436 priv->use_count++;
2437
2438 if (phydev->addr == 0) {
2439 if (ar8xxx_has_gige(priv)) {
2440 phydev->supported = SUPPORTED_1000baseT_Full;
2441 phydev->advertising = ADVERTISED_1000baseT_Full;
2442 } else {
2443 phydev->supported = SUPPORTED_100baseT_Full;
2444 phydev->advertising = ADVERTISED_100baseT_Full;
2445 }
2446
2447 if (chip_is_ar8327(priv)) {
2448 priv->phy = phydev;
2449
2450 ret = ar8xxx_start(priv);
2451 if (ret)
2452 goto err_unregister_switch;
2453 }
2454 } else {
2455 if (ar8xxx_has_gige(priv)) {
2456 phydev->supported |= SUPPORTED_1000baseT_Full;
2457 phydev->advertising |= ADVERTISED_1000baseT_Full;
2458 }
2459 }
2460
2461 phydev->priv = priv;
2462
2463 list_add(&priv->list, &ar8xxx_dev_list);
2464
2465 mutex_unlock(&ar8xxx_dev_list_lock);
2466
2467 return 0;
2468
2469 err_unregister_switch:
2470 if (--priv->use_count)
2471 goto unlock;
2472
2473 unregister_switch(&priv->dev);
2474
2475 free_priv:
2476 ar8xxx_free(priv);
2477 unlock:
2478 mutex_unlock(&ar8xxx_dev_list_lock);
2479 return ret;
2480 }
2481
2482 static void
2483 ar8xxx_phy_detach(struct phy_device *phydev)
2484 {
2485 struct net_device *dev = phydev->attached_dev;
2486
2487 if (!dev)
2488 return;
2489
2490 dev->phy_ptr = NULL;
2491 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2492 dev->eth_mangle_rx = NULL;
2493 dev->eth_mangle_tx = NULL;
2494 }
2495
2496 static void
2497 ar8xxx_phy_remove(struct phy_device *phydev)
2498 {
2499 struct ar8xxx_priv *priv = phydev->priv;
2500
2501 if (WARN_ON(!priv))
2502 return;
2503
2504 phydev->priv = NULL;
2505 if (--priv->use_count > 0)
2506 return;
2507
2508 mutex_lock(&ar8xxx_dev_list_lock);
2509 list_del(&priv->list);
2510 mutex_unlock(&ar8xxx_dev_list_lock);
2511
2512 unregister_switch(&priv->dev);
2513 ar8xxx_mib_stop(priv);
2514 ar8xxx_free(priv);
2515 }
2516
2517 static struct phy_driver ar8xxx_phy_driver = {
2518 .phy_id = 0x004d0000,
2519 .name = "Atheros AR8216/AR8236/AR8316",
2520 .phy_id_mask = 0xffff0000,
2521 .features = PHY_BASIC_FEATURES,
2522 .probe = ar8xxx_phy_probe,
2523 .remove = ar8xxx_phy_remove,
2524 .detach = ar8xxx_phy_detach,
2525 .config_init = ar8xxx_phy_config_init,
2526 .config_aneg = ar8xxx_phy_config_aneg,
2527 .read_status = ar8xxx_phy_read_status,
2528 .driver = { .owner = THIS_MODULE },
2529 };
2530
2531 int __init
2532 ar8xxx_init(void)
2533 {
2534 return phy_driver_register(&ar8xxx_phy_driver);
2535 }
2536
2537 void __exit
2538 ar8xxx_exit(void)
2539 {
2540 phy_driver_unregister(&ar8xxx_phy_driver);
2541 }
2542
2543 module_init(ar8xxx_init);
2544 module_exit(ar8xxx_exit);
2545 MODULE_LICENSE("GPL");
2546
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