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net: ar8327: remove unnecessary spinlocks
[openwrt/staging/yousong.git] / target / linux / generic / files / drivers / net / phy / ar8327.c
1 /*
2 * ar8327.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
29
30 #include "ar8216.h"
31 #include "ar8327.h"
32
33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
35
36 static u32
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
38 {
39 u32 t;
40
41 if (!cfg)
42 return 0;
43
44 t = 0;
45 switch (cfg->mode) {
46 case AR8327_PAD_NC:
47 break;
48
49 case AR8327_PAD_MAC2MAC_MII:
50 t = AR8327_PAD_MAC_MII_EN;
51 if (cfg->rxclk_sel)
52 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
53 if (cfg->txclk_sel)
54 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
55 break;
56
57 case AR8327_PAD_MAC2MAC_GMII:
58 t = AR8327_PAD_MAC_GMII_EN;
59 if (cfg->rxclk_sel)
60 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
61 if (cfg->txclk_sel)
62 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
63 break;
64
65 case AR8327_PAD_MAC_SGMII:
66 t = AR8327_PAD_SGMII_EN;
67
68 /*
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
73 */
74 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
75 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
76 if (cfg->rxclk_delay_en)
77 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
78 if (cfg->txclk_delay_en)
79 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
80
81 if (cfg->sgmii_delay_en)
82 t |= AR8327_PAD_SGMII_DELAY_EN;
83
84 break;
85
86 case AR8327_PAD_MAC2PHY_MII:
87 t = AR8327_PAD_PHY_MII_EN;
88 if (cfg->rxclk_sel)
89 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
90 if (cfg->txclk_sel)
91 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
92 break;
93
94 case AR8327_PAD_MAC2PHY_GMII:
95 t = AR8327_PAD_PHY_GMII_EN;
96 if (cfg->pipe_rxclk_sel)
97 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
98 if (cfg->rxclk_sel)
99 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
100 if (cfg->txclk_sel)
101 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
102 break;
103
104 case AR8327_PAD_MAC_RGMII:
105 t = AR8327_PAD_RGMII_EN;
106 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
107 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
108 if (cfg->rxclk_delay_en)
109 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
110 if (cfg->txclk_delay_en)
111 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
112 break;
113
114 case AR8327_PAD_PHY_GMII:
115 t = AR8327_PAD_PHYX_GMII_EN;
116 break;
117
118 case AR8327_PAD_PHY_RGMII:
119 t = AR8327_PAD_PHYX_RGMII_EN;
120 break;
121
122 case AR8327_PAD_PHY_MII:
123 t = AR8327_PAD_PHYX_MII_EN;
124 break;
125 }
126
127 return t;
128 }
129
130 static void
131 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
132 {
133 switch (priv->chip_rev) {
134 case 1:
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
139 break;
140
141 case 2:
142 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);
143 /* fallthrough */
144 case 4:
145 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
149 break;
150 }
151 }
152
153 static u32
154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
155 {
156 u32 t;
157
158 if (!cfg->force_link)
159 return AR8216_PORT_STATUS_LINK_AUTO;
160
161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
165
166 switch (cfg->speed) {
167 case AR8327_PORT_SPEED_10:
168 t |= AR8216_PORT_SPEED_10M;
169 break;
170 case AR8327_PORT_SPEED_100:
171 t |= AR8216_PORT_SPEED_100M;
172 break;
173 case AR8327_PORT_SPEED_1000:
174 t |= AR8216_PORT_SPEED_1000M;
175 break;
176 }
177
178 return t;
179 }
180
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
183
184 static const struct ar8327_led_entry
185 ar8327_led_map[AR8327_NUM_LEDS] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
189
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
193
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
197
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
201
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
205 };
206
207 static void
208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
209 enum ar8327_led_pattern pattern)
210 {
211 const struct ar8327_led_entry *entry;
212
213 entry = &ar8327_led_map[led_num];
214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
215 (3 << entry->shift), pattern << entry->shift);
216 }
217
218 static void
219 ar8327_led_work_func(struct work_struct *work)
220 {
221 struct ar8327_led *aled;
222 u8 pattern;
223
224 aled = container_of(work, struct ar8327_led, led_work);
225
226 pattern = aled->pattern;
227
228 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
229 pattern);
230 }
231
232 static void
233 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
234 {
235 if (aled->pattern == pattern)
236 return;
237
238 aled->pattern = pattern;
239 schedule_work(&aled->led_work);
240 }
241
242 static inline struct ar8327_led *
243 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
244 {
245 return container_of(led_cdev, struct ar8327_led, cdev);
246 }
247
248 static int
249 ar8327_led_blink_set(struct led_classdev *led_cdev,
250 unsigned long *delay_on,
251 unsigned long *delay_off)
252 {
253 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
254
255 if (*delay_on == 0 && *delay_off == 0) {
256 *delay_on = 125;
257 *delay_off = 125;
258 }
259
260 if (*delay_on != 125 || *delay_off != 125) {
261 /*
262 * The hardware only supports blinking at 4Hz. Fall back
263 * to software implementation in other cases.
264 */
265 return -EINVAL;
266 }
267
268 spin_lock(&aled->lock);
269
270 aled->enable_hw_mode = false;
271 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
272
273 spin_unlock(&aled->lock);
274
275 return 0;
276 }
277
278 static void
279 ar8327_led_set_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281 {
282 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
283 u8 pattern;
284 bool active;
285
286 active = (brightness != LED_OFF);
287 active ^= aled->active_low;
288
289 pattern = (active) ? AR8327_LED_PATTERN_ON :
290 AR8327_LED_PATTERN_OFF;
291
292 spin_lock(&aled->lock);
293
294 aled->enable_hw_mode = false;
295 ar8327_led_schedule_change(aled, pattern);
296
297 spin_unlock(&aled->lock);
298 }
299
300 static ssize_t
301 ar8327_led_enable_hw_mode_show(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304 {
305 struct led_classdev *led_cdev = dev_get_drvdata(dev);
306 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
307 ssize_t ret = 0;
308
309 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
310
311 return ret;
312 }
313
314 static ssize_t
315 ar8327_led_enable_hw_mode_store(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf,
318 size_t size)
319 {
320 struct led_classdev *led_cdev = dev_get_drvdata(dev);
321 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
322 u8 pattern;
323 u8 value;
324 int ret;
325
326 ret = kstrtou8(buf, 10, &value);
327 if (ret < 0)
328 return -EINVAL;
329
330 spin_lock(&aled->lock);
331
332 aled->enable_hw_mode = !!value;
333 if (aled->enable_hw_mode)
334 pattern = AR8327_LED_PATTERN_RULE;
335 else
336 pattern = AR8327_LED_PATTERN_OFF;
337
338 ar8327_led_schedule_change(aled, pattern);
339
340 spin_unlock(&aled->lock);
341
342 return size;
343 }
344
345 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
346 ar8327_led_enable_hw_mode_show,
347 ar8327_led_enable_hw_mode_store);
348
349 static int
350 ar8327_led_register(struct ar8327_led *aled)
351 {
352 int ret;
353
354 ret = led_classdev_register(NULL, &aled->cdev);
355 if (ret < 0)
356 return ret;
357
358 if (aled->mode == AR8327_LED_MODE_HW) {
359 ret = device_create_file(aled->cdev.dev,
360 &dev_attr_enable_hw_mode);
361 if (ret)
362 goto err_unregister;
363 }
364
365 return 0;
366
367 err_unregister:
368 led_classdev_unregister(&aled->cdev);
369 return ret;
370 }
371
372 static void
373 ar8327_led_unregister(struct ar8327_led *aled)
374 {
375 if (aled->mode == AR8327_LED_MODE_HW)
376 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
377
378 led_classdev_unregister(&aled->cdev);
379 cancel_work_sync(&aled->led_work);
380 }
381
382 static int
383 ar8327_led_create(struct ar8xxx_priv *priv,
384 const struct ar8327_led_info *led_info)
385 {
386 struct ar8327_data *data = priv->chip_data;
387 struct ar8327_led *aled;
388 int ret;
389
390 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
391 return 0;
392
393 if (!led_info->name)
394 return -EINVAL;
395
396 if (led_info->led_num >= AR8327_NUM_LEDS)
397 return -EINVAL;
398
399 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
400 GFP_KERNEL);
401 if (!aled)
402 return -ENOMEM;
403
404 aled->sw_priv = priv;
405 aled->led_num = led_info->led_num;
406 aled->active_low = led_info->active_low;
407 aled->mode = led_info->mode;
408
409 if (aled->mode == AR8327_LED_MODE_HW)
410 aled->enable_hw_mode = true;
411
412 aled->name = (char *)(aled + 1);
413 strcpy(aled->name, led_info->name);
414
415 aled->cdev.name = aled->name;
416 aled->cdev.brightness_set = ar8327_led_set_brightness;
417 aled->cdev.blink_set = ar8327_led_blink_set;
418 aled->cdev.default_trigger = led_info->default_trigger;
419
420 spin_lock_init(&aled->lock);
421 mutex_init(&aled->mutex);
422 INIT_WORK(&aled->led_work, ar8327_led_work_func);
423
424 ret = ar8327_led_register(aled);
425 if (ret)
426 goto err_free;
427
428 data->leds[data->num_leds++] = aled;
429
430 return 0;
431
432 err_free:
433 kfree(aled);
434 return ret;
435 }
436
437 static void
438 ar8327_led_destroy(struct ar8327_led *aled)
439 {
440 ar8327_led_unregister(aled);
441 kfree(aled);
442 }
443
444 static void
445 ar8327_leds_init(struct ar8xxx_priv *priv)
446 {
447 struct ar8327_data *data = priv->chip_data;
448 unsigned i;
449
450 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
451 return;
452
453 for (i = 0; i < data->num_leds; i++) {
454 struct ar8327_led *aled;
455
456 aled = data->leds[i];
457
458 if (aled->enable_hw_mode)
459 aled->pattern = AR8327_LED_PATTERN_RULE;
460 else
461 aled->pattern = AR8327_LED_PATTERN_OFF;
462
463 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
464 }
465 }
466
467 static void
468 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
469 {
470 struct ar8327_data *data = priv->chip_data;
471 unsigned i;
472
473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
474 return;
475
476 for (i = 0; i < data->num_leds; i++) {
477 struct ar8327_led *aled;
478
479 aled = data->leds[i];
480 ar8327_led_destroy(aled);
481 }
482
483 kfree(data->leds);
484 }
485
486 static int
487 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
488 struct ar8327_platform_data *pdata)
489 {
490 struct ar8327_led_cfg *led_cfg;
491 struct ar8327_data *data = priv->chip_data;
492 u32 pos, new_pos;
493 u32 t;
494
495 if (!pdata)
496 return -EINVAL;
497
498 priv->get_port_link = pdata->get_port_link;
499
500 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
501 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
502
503 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
504 if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
505 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
506 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
507
508 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
509 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
510 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
511 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
512
513 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
514 new_pos = pos;
515
516 led_cfg = pdata->led_cfg;
517 if (led_cfg) {
518 if (led_cfg->open_drain)
519 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
520 else
521 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
522
523 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
524 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
525 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
526 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
527
528 if (new_pos != pos)
529 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
530 }
531
532 if (pdata->sgmii_cfg) {
533 t = pdata->sgmii_cfg->sgmii_ctrl;
534 if (priv->chip_rev == 1)
535 t |= AR8327_SGMII_CTRL_EN_PLL |
536 AR8327_SGMII_CTRL_EN_RX |
537 AR8327_SGMII_CTRL_EN_TX;
538 else
539 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
540 AR8327_SGMII_CTRL_EN_RX |
541 AR8327_SGMII_CTRL_EN_TX);
542
543 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
544
545 if (pdata->sgmii_cfg->serdes_aen)
546 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
547 else
548 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
549 }
550
551 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
552
553 if (pdata->leds && pdata->num_leds) {
554 int i;
555
556 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
557 GFP_KERNEL);
558 if (!data->leds)
559 return -ENOMEM;
560
561 for (i = 0; i < pdata->num_leds; i++)
562 ar8327_led_create(priv, &pdata->leds[i]);
563 }
564
565 return 0;
566 }
567
568 #ifdef CONFIG_OF
569 static int
570 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
571 {
572 struct ar8327_data *data = priv->chip_data;
573 const __be32 *paddr;
574 int len;
575 int i;
576
577 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
578 if (!paddr || len < (2 * sizeof(*paddr)))
579 return -EINVAL;
580
581 len /= sizeof(*paddr);
582
583 for (i = 0; i < len - 1; i += 2) {
584 u32 reg;
585 u32 val;
586
587 reg = be32_to_cpup(paddr + i);
588 val = be32_to_cpup(paddr + i + 1);
589
590 switch (reg) {
591 case AR8327_REG_PORT_STATUS(0):
592 data->port0_status = val;
593 break;
594 case AR8327_REG_PORT_STATUS(6):
595 data->port6_status = val;
596 break;
597 default:
598 ar8xxx_write(priv, reg, val);
599 break;
600 }
601 }
602
603 return 0;
604 }
605 #else
606 static inline int
607 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
608 {
609 return -EINVAL;
610 }
611 #endif
612
613 static int
614 ar8327_hw_init(struct ar8xxx_priv *priv)
615 {
616 int ret;
617
618 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
619 if (!priv->chip_data)
620 return -ENOMEM;
621
622 if (priv->phy->dev.of_node)
623 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
624 else
625 ret = ar8327_hw_config_pdata(priv,
626 priv->phy->dev.platform_data);
627
628 if (ret)
629 return ret;
630
631 ar8327_leds_init(priv);
632
633 ar8xxx_phy_init(priv);
634
635 return 0;
636 }
637
638 static void
639 ar8327_cleanup(struct ar8xxx_priv *priv)
640 {
641 ar8327_leds_cleanup(priv);
642 }
643
644 static void
645 ar8327_init_globals(struct ar8xxx_priv *priv)
646 {
647 struct ar8327_data *data = priv->chip_data;
648 u32 t;
649 int i;
650
651 /* enable CPU port and disable mirror port */
652 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
653 AR8327_FWD_CTRL0_MIRROR_PORT;
654 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
655
656 /* forward multicast and broadcast frames to CPU */
657 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
658 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
659 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
660 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
661
662 /* enable jumbo frames */
663 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
664 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
665
666 /* Enable MIB counters */
667 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
668 AR8327_MODULE_EN_MIB);
669
670 /* Disable EEE on all phy's due to stability issues */
671 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
672 data->eee[i] = false;
673 }
674
675 static void
676 ar8327_init_port(struct ar8xxx_priv *priv, int port)
677 {
678 struct ar8327_data *data = priv->chip_data;
679 u32 t;
680
681 if (port == AR8216_PORT_CPU)
682 t = data->port0_status;
683 else if (port == 6)
684 t = data->port6_status;
685 else
686 t = AR8216_PORT_STATUS_LINK_AUTO;
687
688 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
689 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
690
691 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
692 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
693 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
694
695 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
696 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
697
698 t = AR8327_PORT_LOOKUP_LEARN;
699 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
700 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
701 }
702
703 static u32
704 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
705 {
706 u32 t;
707
708 t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
709 /* map the flow control autoneg result bits to the flow control bits
710 * used in forced mode to allow ar8216_read_port_link detect
711 * flow control properly if autoneg is used
712 */
713 if (t & AR8216_PORT_STATUS_LINK_UP &&
714 t & AR8216_PORT_STATUS_LINK_AUTO) {
715 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
716 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
717 t |= AR8216_PORT_STATUS_TXFLOW;
718 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
719 t |= AR8216_PORT_STATUS_RXFLOW;
720 }
721
722 return t;
723 }
724
725 static u32
726 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
727 {
728 int phy;
729 u16 t;
730
731 if (port >= priv->dev.ports)
732 return 0;
733
734 if (port == 0 || port == 6)
735 return 0;
736
737 phy = port - 1;
738
739 /* EEE Ability Auto-negotiation Result */
740 t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);
741
742 return mmd_eee_adv_to_ethtool_adv_t(t);
743 }
744
745 static int
746 ar8327_atu_flush(struct ar8xxx_priv *priv)
747 {
748 int ret;
749
750 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
751 AR8327_ATU_FUNC_BUSY, 0);
752 if (!ret)
753 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
754 AR8327_ATU_FUNC_OP_FLUSH |
755 AR8327_ATU_FUNC_BUSY);
756
757 return ret;
758 }
759
760 static int
761 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
762 {
763 u32 t;
764 int ret;
765
766 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
767 AR8327_ATU_FUNC_BUSY, 0);
768 if (!ret) {
769 t = (port << AR8327_ATU_PORT_NUM_S);
770 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
771 t |= AR8327_ATU_FUNC_BUSY;
772 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
773 }
774
775 return ret;
776 }
777
778 static int
779 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
780 {
781 u32 fwd_ctrl, frame_ack;
782
783 fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
784 frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
785 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
786 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
787 AR8327_FRAME_ACK_CTRL_S(port));
788
789 return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
790 fwd_ctrl) == fwd_ctrl &&
791 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
792 frame_ack) == frame_ack;
793 }
794
795 static void
796 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
797 {
798 int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
799 u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
800 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
801 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
802 AR8327_FRAME_ACK_CTRL_S(port);
803
804 if (enable) {
805 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
806 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
807 BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
808 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
809 } else {
810 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
811 BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
812 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
813 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
814 }
815 }
816
817 static void
818 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
819 {
820 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
821 AR8327_VTU_FUNC1_BUSY, 0))
822 return;
823
824 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
825 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
826
827 op |= AR8327_VTU_FUNC1_BUSY;
828 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
829 }
830
831 static void
832 ar8327_vtu_flush(struct ar8xxx_priv *priv)
833 {
834 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
835 }
836
837 static void
838 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
839 {
840 u32 op;
841 u32 val;
842 int i;
843
844 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
845 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
846 for (i = 0; i < AR8327_NUM_PORTS; i++) {
847 u32 mode;
848
849 if ((port_mask & BIT(i)) == 0)
850 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
851 else if (priv->vlan == 0)
852 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
853 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
854 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
855 else
856 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
857
858 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
859 }
860 ar8327_vtu_op(priv, op, val);
861 }
862
863 static void
864 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
865 {
866 u32 t;
867 u32 egress, ingress;
868 u32 pvid = priv->vlan_id[priv->pvid[port]];
869
870 if (priv->vlan) {
871 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
872 ingress = AR8216_IN_SECURE;
873 } else {
874 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
875 ingress = AR8216_IN_PORT_ONLY;
876 }
877
878 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
879 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
880 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
881
882 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
883 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
884 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
885
886 t = members;
887 t |= AR8327_PORT_LOOKUP_LEARN;
888 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
889 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
890 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
891 }
892
893 static int
894 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
895 {
896 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
897 u8 ports = priv->vlan_table[val->port_vlan];
898 int i;
899
900 val->len = 0;
901 for (i = 0; i < dev->ports; i++) {
902 struct switch_port *p;
903
904 if (!(ports & (1 << i)))
905 continue;
906
907 p = &val->value.ports[val->len++];
908 p->id = i;
909 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
910 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
911 else
912 p->flags = 0;
913 }
914 return 0;
915 }
916
917 static int
918 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
919 {
920 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
921 u8 *vt = &priv->vlan_table[val->port_vlan];
922 int i;
923
924 *vt = 0;
925 for (i = 0; i < val->len; i++) {
926 struct switch_port *p = &val->value.ports[i];
927
928 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
929 if (val->port_vlan == priv->pvid[p->id]) {
930 priv->vlan_tagged |= (1 << p->id);
931 }
932 } else {
933 priv->vlan_tagged &= ~(1 << p->id);
934 priv->pvid[p->id] = val->port_vlan;
935 }
936
937 *vt |= 1 << p->id;
938 }
939 return 0;
940 }
941
942 static void
943 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
944 {
945 int port;
946
947 /* reset all mirror registers */
948 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
949 AR8327_FWD_CTRL0_MIRROR_PORT,
950 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
951 for (port = 0; port < AR8327_NUM_PORTS; port++) {
952 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
953 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
954
955 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
956 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
957 }
958
959 /* now enable mirroring if necessary */
960 if (priv->source_port >= AR8327_NUM_PORTS ||
961 priv->monitor_port >= AR8327_NUM_PORTS ||
962 priv->source_port == priv->monitor_port) {
963 return;
964 }
965
966 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
967 AR8327_FWD_CTRL0_MIRROR_PORT,
968 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
969
970 if (priv->mirror_rx)
971 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
972 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
973
974 if (priv->mirror_tx)
975 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
976 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
977 }
978
979 static int
980 ar8327_sw_set_eee(struct switch_dev *dev,
981 const struct switch_attr *attr,
982 struct switch_val *val)
983 {
984 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
985 struct ar8327_data *data = priv->chip_data;
986 int port = val->port_vlan;
987 int phy;
988
989 if (port >= dev->ports)
990 return -EINVAL;
991 if (port == 0 || port == 6)
992 return -EOPNOTSUPP;
993
994 phy = port - 1;
995
996 data->eee[phy] = !!(val->value.i);
997
998 return 0;
999 }
1000
1001 static int
1002 ar8327_sw_get_eee(struct switch_dev *dev,
1003 const struct switch_attr *attr,
1004 struct switch_val *val)
1005 {
1006 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1007 const struct ar8327_data *data = priv->chip_data;
1008 int port = val->port_vlan;
1009 int phy;
1010
1011 if (port >= dev->ports)
1012 return -EINVAL;
1013 if (port == 0 || port == 6)
1014 return -EOPNOTSUPP;
1015
1016 phy = port - 1;
1017
1018 val->value.i = data->eee[phy];
1019
1020 return 0;
1021 }
1022
1023 static void
1024 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1025 {
1026 int timeout = 20;
1027
1028 while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout)
1029 udelay(10);
1030
1031 if (!timeout)
1032 pr_err("ar8327: timeout waiting for atu to become ready\n");
1033 }
1034
1035 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1036 struct arl_entry *a, u32 *status, enum arl_op op)
1037 {
1038 struct mii_bus *bus = priv->mii_bus;
1039 u16 r2, page;
1040 u16 r1_data0, r1_data1, r1_data2, r1_func;
1041 u32 t, val0, val1, val2;
1042 int i;
1043
1044 split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1045 r2 |= 0x10;
1046
1047 r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1048 r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1049 r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1050
1051 switch (op) {
1052 case AR8XXX_ARL_INITIALIZE:
1053 /* all ATU registers are on the same page
1054 * therefore set page only once
1055 */
1056 bus->write(bus, 0x18, 0, page);
1057 wait_for_page_switch();
1058
1059 ar8327_wait_atu_ready(priv, r2, r1_func);
1060
1061 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1062 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1063 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1064 break;
1065 case AR8XXX_ARL_GET_NEXT:
1066 ar8xxx_mii_write32(priv, r2, r1_func,
1067 AR8327_ATU_FUNC_OP_GET_NEXT |
1068 AR8327_ATU_FUNC_BUSY);
1069 ar8327_wait_atu_ready(priv, r2, r1_func);
1070
1071 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1072 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1073 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1074
1075 *status = val2 & AR8327_ATU_STATUS;
1076 if (!*status)
1077 break;
1078
1079 i = 0;
1080 t = AR8327_ATU_PORT0;
1081 while (!(val1 & t) && ++i < AR8327_NUM_PORTS)
1082 t <<= 1;
1083
1084 a->port = i;
1085 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1086 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1087 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1088 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1089 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1090 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1091 break;
1092 }
1093 }
1094
1095 static int
1096 ar8327_sw_hw_apply(struct switch_dev *dev)
1097 {
1098 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1099 const struct ar8327_data *data = priv->chip_data;
1100 int ret, i;
1101
1102 ret = ar8xxx_sw_hw_apply(dev);
1103 if (ret)
1104 return ret;
1105
1106 for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1107 if (data->eee[i])
1108 ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1109 AR8327_EEE_CTRL_DISABLE_PHY(i));
1110 else
1111 ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1112 AR8327_EEE_CTRL_DISABLE_PHY(i));
1113 }
1114
1115 return 0;
1116 }
1117
1118 int
1119 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1120 const struct switch_attr *attr,
1121 struct switch_val *val)
1122 {
1123 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1124 int port = val->port_vlan;
1125
1126 if (port >= dev->ports)
1127 return -EINVAL;
1128
1129 mutex_lock(&priv->reg_mutex);
1130 val->value.i = ar8327_get_port_igmp(priv, port);
1131 mutex_unlock(&priv->reg_mutex);
1132
1133 return 0;
1134 }
1135
1136 int
1137 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1138 const struct switch_attr *attr,
1139 struct switch_val *val)
1140 {
1141 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1142 int port = val->port_vlan;
1143
1144 if (port >= dev->ports)
1145 return -EINVAL;
1146
1147 mutex_lock(&priv->reg_mutex);
1148 ar8327_set_port_igmp(priv, port, val->value.i);
1149 mutex_unlock(&priv->reg_mutex);
1150
1151 return 0;
1152 }
1153
1154 int
1155 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1156 const struct switch_attr *attr,
1157 struct switch_val *val)
1158 {
1159 int port;
1160
1161 for (port = 0; port < dev->ports; port++) {
1162 val->port_vlan = port;
1163 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1164 !val->value.i)
1165 break;
1166 }
1167
1168 return 0;
1169 }
1170
1171 int
1172 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1173 const struct switch_attr *attr,
1174 struct switch_val *val)
1175 {
1176 int port;
1177
1178 for (port = 0; port < dev->ports; port++) {
1179 val->port_vlan = port;
1180 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1181 break;
1182 }
1183
1184 return 0;
1185 }
1186
1187 int
1188 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1189 const struct switch_attr *attr,
1190 struct switch_val *val)
1191 {
1192 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1193 u32 val_reg;
1194
1195 mutex_lock(&priv->reg_mutex);
1196 val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1197 val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1198 mutex_unlock(&priv->reg_mutex);
1199
1200 return 0;
1201 }
1202
1203 int
1204 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1205 const struct switch_attr *attr,
1206 struct switch_val *val)
1207 {
1208 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1209
1210 mutex_lock(&priv->reg_mutex);
1211 if (val->value.i)
1212 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1213 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1214 else
1215 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1216 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1217 mutex_unlock(&priv->reg_mutex);
1218
1219 return 0;
1220 }
1221
1222 static const struct switch_attr ar8327_sw_attr_globals[] = {
1223 {
1224 .type = SWITCH_TYPE_INT,
1225 .name = "enable_vlan",
1226 .description = "Enable VLAN mode",
1227 .set = ar8xxx_sw_set_vlan,
1228 .get = ar8xxx_sw_get_vlan,
1229 .max = 1
1230 },
1231 {
1232 .type = SWITCH_TYPE_NOVAL,
1233 .name = "reset_mibs",
1234 .description = "Reset all MIB counters",
1235 .set = ar8xxx_sw_set_reset_mibs,
1236 },
1237 {
1238 .type = SWITCH_TYPE_INT,
1239 .name = "enable_mirror_rx",
1240 .description = "Enable mirroring of RX packets",
1241 .set = ar8xxx_sw_set_mirror_rx_enable,
1242 .get = ar8xxx_sw_get_mirror_rx_enable,
1243 .max = 1
1244 },
1245 {
1246 .type = SWITCH_TYPE_INT,
1247 .name = "enable_mirror_tx",
1248 .description = "Enable mirroring of TX packets",
1249 .set = ar8xxx_sw_set_mirror_tx_enable,
1250 .get = ar8xxx_sw_get_mirror_tx_enable,
1251 .max = 1
1252 },
1253 {
1254 .type = SWITCH_TYPE_INT,
1255 .name = "mirror_monitor_port",
1256 .description = "Mirror monitor port",
1257 .set = ar8xxx_sw_set_mirror_monitor_port,
1258 .get = ar8xxx_sw_get_mirror_monitor_port,
1259 .max = AR8327_NUM_PORTS - 1
1260 },
1261 {
1262 .type = SWITCH_TYPE_INT,
1263 .name = "mirror_source_port",
1264 .description = "Mirror source port",
1265 .set = ar8xxx_sw_set_mirror_source_port,
1266 .get = ar8xxx_sw_get_mirror_source_port,
1267 .max = AR8327_NUM_PORTS - 1
1268 },
1269 {
1270 .type = SWITCH_TYPE_INT,
1271 .name = "arl_age_time",
1272 .description = "ARL age time (secs)",
1273 .set = ar8xxx_sw_set_arl_age_time,
1274 .get = ar8xxx_sw_get_arl_age_time,
1275 },
1276 {
1277 .type = SWITCH_TYPE_STRING,
1278 .name = "arl_table",
1279 .description = "Get ARL table",
1280 .set = NULL,
1281 .get = ar8xxx_sw_get_arl_table,
1282 },
1283 {
1284 .type = SWITCH_TYPE_NOVAL,
1285 .name = "flush_arl_table",
1286 .description = "Flush ARL table",
1287 .set = ar8xxx_sw_set_flush_arl_table,
1288 },
1289 {
1290 .type = SWITCH_TYPE_INT,
1291 .name = "igmp_snooping",
1292 .description = "Enable IGMP Snooping",
1293 .set = ar8327_sw_set_igmp_snooping,
1294 .get = ar8327_sw_get_igmp_snooping,
1295 .max = 1
1296 },
1297 {
1298 .type = SWITCH_TYPE_INT,
1299 .name = "igmp_v3",
1300 .description = "Enable IGMPv3 support",
1301 .set = ar8327_sw_set_igmp_v3,
1302 .get = ar8327_sw_get_igmp_v3,
1303 .max = 1
1304 },
1305 };
1306
1307 static const struct switch_attr ar8327_sw_attr_port[] = {
1308 {
1309 .type = SWITCH_TYPE_NOVAL,
1310 .name = "reset_mib",
1311 .description = "Reset single port MIB counters",
1312 .set = ar8xxx_sw_set_port_reset_mib,
1313 },
1314 {
1315 .type = SWITCH_TYPE_STRING,
1316 .name = "mib",
1317 .description = "Get port's MIB counters",
1318 .set = NULL,
1319 .get = ar8xxx_sw_get_port_mib,
1320 },
1321 {
1322 .type = SWITCH_TYPE_INT,
1323 .name = "enable_eee",
1324 .description = "Enable EEE PHY sleep mode",
1325 .set = ar8327_sw_set_eee,
1326 .get = ar8327_sw_get_eee,
1327 .max = 1,
1328 },
1329 {
1330 .type = SWITCH_TYPE_NOVAL,
1331 .name = "flush_arl_table",
1332 .description = "Flush port's ARL table entries",
1333 .set = ar8xxx_sw_set_flush_port_arl_table,
1334 },
1335 {
1336 .type = SWITCH_TYPE_INT,
1337 .name = "igmp_snooping",
1338 .description = "Enable port's IGMP Snooping",
1339 .set = ar8327_sw_set_port_igmp_snooping,
1340 .get = ar8327_sw_get_port_igmp_snooping,
1341 .max = 1
1342 },
1343 };
1344
1345 static const struct switch_dev_ops ar8327_sw_ops = {
1346 .attr_global = {
1347 .attr = ar8327_sw_attr_globals,
1348 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1349 },
1350 .attr_port = {
1351 .attr = ar8327_sw_attr_port,
1352 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1353 },
1354 .attr_vlan = {
1355 .attr = ar8xxx_sw_attr_vlan,
1356 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1357 },
1358 .get_port_pvid = ar8xxx_sw_get_pvid,
1359 .set_port_pvid = ar8xxx_sw_set_pvid,
1360 .get_vlan_ports = ar8327_sw_get_ports,
1361 .set_vlan_ports = ar8327_sw_set_ports,
1362 .apply_config = ar8327_sw_hw_apply,
1363 .reset_switch = ar8xxx_sw_reset_switch,
1364 .get_port_link = ar8xxx_sw_get_port_link,
1365 };
1366
1367 const struct ar8xxx_chip ar8327_chip = {
1368 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1369 .config_at_probe = true,
1370 .mii_lo_first = true,
1371
1372 .name = "Atheros AR8327",
1373 .ports = AR8327_NUM_PORTS,
1374 .vlans = AR8X16_MAX_VLANS,
1375 .swops = &ar8327_sw_ops,
1376
1377 .reg_port_stats_start = 0x1000,
1378 .reg_port_stats_length = 0x100,
1379 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1380
1381 .hw_init = ar8327_hw_init,
1382 .cleanup = ar8327_cleanup,
1383 .init_globals = ar8327_init_globals,
1384 .init_port = ar8327_init_port,
1385 .setup_port = ar8327_setup_port,
1386 .read_port_status = ar8327_read_port_status,
1387 .read_port_eee_status = ar8327_read_port_eee_status,
1388 .atu_flush = ar8327_atu_flush,
1389 .atu_flush_port = ar8327_atu_flush_port,
1390 .vtu_flush = ar8327_vtu_flush,
1391 .vtu_load_vlan = ar8327_vtu_load_vlan,
1392 .phy_fixup = ar8327_phy_fixup,
1393 .set_mirror_regs = ar8327_set_mirror_regs,
1394 .get_arl_entry = ar8327_get_arl_entry,
1395 .sw_hw_apply = ar8327_sw_hw_apply,
1396
1397 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1398 .mib_decs = ar8236_mibs,
1399 .mib_func = AR8327_REG_MIB_FUNC
1400 };
1401
1402 const struct ar8xxx_chip ar8337_chip = {
1403 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1404 .config_at_probe = true,
1405 .mii_lo_first = true,
1406
1407 .name = "Atheros AR8337",
1408 .ports = AR8327_NUM_PORTS,
1409 .vlans = AR8X16_MAX_VLANS,
1410 .swops = &ar8327_sw_ops,
1411
1412 .reg_port_stats_start = 0x1000,
1413 .reg_port_stats_length = 0x100,
1414 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1415
1416 .hw_init = ar8327_hw_init,
1417 .cleanup = ar8327_cleanup,
1418 .init_globals = ar8327_init_globals,
1419 .init_port = ar8327_init_port,
1420 .setup_port = ar8327_setup_port,
1421 .read_port_status = ar8327_read_port_status,
1422 .read_port_eee_status = ar8327_read_port_eee_status,
1423 .atu_flush = ar8327_atu_flush,
1424 .atu_flush_port = ar8327_atu_flush_port,
1425 .vtu_flush = ar8327_vtu_flush,
1426 .vtu_load_vlan = ar8327_vtu_load_vlan,
1427 .phy_fixup = ar8327_phy_fixup,
1428 .set_mirror_regs = ar8327_set_mirror_regs,
1429 .get_arl_entry = ar8327_get_arl_entry,
1430 .sw_hw_apply = ar8327_sw_hw_apply,
1431
1432 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1433 .mib_decs = ar8236_mibs,
1434 .mib_func = AR8327_REG_MIB_FUNC
1435 };
1436
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