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a27cc8545eff5e2d77a3a7b9d0af2f2fd980ba75
[openwrt/staging/yousong.git] / target / linux / generic / patches-3.14 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -1,8 +1,10 @@
4 bcma-y += main.o scan.o core.o sprom.o
5 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
6 +bcma-y += driver_chipcommon_b.o
7 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
8 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
9 bcma-y += driver_pci.o
10 +bcma-y += driver_pcie2.o
11 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
12 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
13 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
14 --- a/drivers/bcma/driver_chipcommon_pmu.c
15 +++ b/drivers/bcma/driver_chipcommon_pmu.c
16 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
17 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
18 break;
19
20 + case BCMA_CHIP_ID_BCM43131:
21 + case BCMA_CHIP_ID_BCM43217:
22 case BCMA_CHIP_ID_BCM43227:
23 case BCMA_CHIP_ID_BCM43228:
24 case BCMA_CHIP_ID_BCM43428:
25 --- a/drivers/bcma/driver_gpio.c
26 +++ b/drivers/bcma/driver_gpio.c
27 @@ -76,7 +76,7 @@ static void bcma_gpio_free(struct gpio_c
28 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
29 }
30
31 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
32 +#if IS_BUILTIN(CONFIG_BCM47XX)
33 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
34 {
35 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
36 @@ -215,10 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
37 chip->set = bcma_gpio_set_value;
38 chip->direction_input = bcma_gpio_direction_input;
39 chip->direction_output = bcma_gpio_direction_output;
40 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
41 +#if IS_BUILTIN(CONFIG_BCM47XX)
42 chip->to_irq = bcma_gpio_to_irq;
43 #endif
44 - chip->ngpio = 16;
45 +#if IS_BUILTIN(CONFIG_OF)
46 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
47 + chip->of_node = cc->core->dev.of_node;
48 +#endif
49 + switch (cc->core->bus->chipinfo.id) {
50 + case BCMA_CHIP_ID_BCM5357:
51 + case BCMA_CHIP_ID_BCM53572:
52 + chip->ngpio = 32;
53 + break;
54 + default:
55 + chip->ngpio = 16;
56 + }
57 +
58 /* There is just one SoC in one device and its GPIO addresses should be
59 * deterministic to address them more easily. The other buses could get
60 * a random base number. */
61 --- /dev/null
62 +++ b/drivers/bcma/driver_pcie2.c
63 @@ -0,0 +1,175 @@
64 +/*
65 + * Broadcom specific AMBA
66 + * PCIe Gen 2 Core
67 + *
68 + * Copyright 2014, Broadcom Corporation
69 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
70 + *
71 + * Licensed under the GNU/GPL. See COPYING for details.
72 + */
73 +
74 +#include "bcma_private.h"
75 +#include <linux/bcma/bcma.h>
76 +
77 +/**************************************************
78 + * R/W ops.
79 + **************************************************/
80 +
81 +#if 0
82 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
83 +{
84 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
85 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
86 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
87 +}
88 +#endif
89 +
90 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
91 + u32 val)
92 +{
93 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
94 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
95 +}
96 +
97 +/**************************************************
98 + * Init.
99 + **************************************************/
100 +
101 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
102 + bool enable)
103 +{
104 + u32 val;
105 +
106 + /* restore back to default */
107 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
108 + val |= PCIE2_CLKC_DLYPERST;
109 + val &= ~PCIE2_CLKC_DISSPROMLD;
110 + if (enable) {
111 + val &= ~PCIE2_CLKC_DLYPERST;
112 + val |= PCIE2_CLKC_DISSPROMLD;
113 + }
114 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
115 + /* flush */
116 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
117 +}
118 +
119 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
120 +{
121 + /* LTR0 */
122 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
123 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
124 + /* LTR1 */
125 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
126 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
127 + /* LTR2 */
128 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
129 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
130 +}
131 +
132 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
133 +{
134 + u8 core_rev = pcie2->core->id.rev;
135 + u32 devstsctr2;
136 +
137 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
138 + return;
139 +
140 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
141 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
142 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
143 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
144 + /* force the right LTR values */
145 + bcma_core_pcie2_set_ltr_vals(pcie2);
146 +
147 + /* TODO:
148 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
149 +
150 + /* enable the LTR */
151 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
152 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
153 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
154 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
155 +
156 + /* set the LTR state to be active */
157 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
158 + PCIE2_LTR_ACTIVE);
159 + usleep_range(1000, 2000);
160 +
161 + /* set the LTR state to be sleep */
162 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
163 + PCIE2_LTR_SLEEP);
164 + usleep_range(1000, 2000);
165 + }
166 +}
167 +
168 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
169 +{
170 + u8 core_rev = pcie2->core->id.rev;
171 + bool pciewar160, pciewar162;
172 +
173 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
174 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
175 + core_rev == 9 || core_rev == 11;
176 +
177 + if (!pciewar160 && !pciewar162)
178 + return;
179 +
180 +/* TODO */
181 +#if 0
182 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
183 + PCIE_DISABLE_L1CLK_GATING);
184 +#if 0
185 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
186 + PCIEGEN2_COE_PVT_TL_CTRL_0);
187 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
188 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
189 +#endif
190 +#endif
191 +}
192 +
193 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
194 +{
195 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
196 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
197 +}
198 +
199 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
200 +{
201 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
202 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
203 +}
204 +
205 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
206 +{
207 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
208 + u8 core_rev = pcie2->core->id.rev;
209 + u32 alp_khz, pm_value;
210 +
211 + if (core_rev <= 13) {
212 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
213 + pm_value = (1000000 * 2) / alp_khz;
214 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
215 + PCIE2_PVT_REG_PM_CLK_PERIOD);
216 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
217 + }
218 +}
219 +
220 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
221 +{
222 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
223 + u32 tmp;
224 +
225 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
226 + if ((tmp & 0xe) >> 1 == 2)
227 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
228 +
229 + /* TODO: Do we need pcie_reqsize? */
230 +
231 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
232 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
233 + bcma_core_pcie2_hw_ltr_war(pcie2);
234 + pciedev_crwlpciegen2(pcie2);
235 + pciedev_reg_pm_clk_period(pcie2);
236 + pciedev_crwlpciegen2_180(pcie2);
237 + pciedev_crwlpciegen2_182(pcie2);
238 +}
239 --- a/drivers/bcma/host_pci.c
240 +++ b/drivers/bcma/host_pci.c
241 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
242 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
243 bus->boardinfo.type = bus->host_pci->subsystem_device;
244
245 + /* Initialize struct, detect chip */
246 + bcma_init_bus(bus);
247 +
248 /* Register */
249 err = bcma_bus_register(bus);
250 if (err)
251 @@ -272,14 +275,18 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
252 static const struct pci_device_id bcma_pci_bridge_tbl[] = {
253 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
254 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
255 - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
256 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
257 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
258 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
259 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
260 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
261 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
262 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
263 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
264 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
265 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
266 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
267 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
268 { 0, },
269 };
270 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
271 --- a/drivers/bcma/main.c
272 +++ b/drivers/bcma/main.c
273 @@ -10,6 +10,7 @@
274 #include <linux/platform_device.h>
275 #include <linux/bcma/bcma.h>
276 #include <linux/slab.h>
277 +#include <linux/of_address.h>
278
279 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
280 MODULE_LICENSE("GPL");
281 @@ -120,56 +121,124 @@ static void bcma_release_core_dev(struct
282 kfree(core);
283 }
284
285 -static int bcma_register_cores(struct bcma_bus *bus)
286 +static bool bcma_is_core_needed_early(u16 core_id)
287 +{
288 + switch (core_id) {
289 + case BCMA_CORE_NS_NAND:
290 + case BCMA_CORE_NS_QSPI:
291 + return true;
292 + }
293 +
294 + return false;
295 +}
296 +
297 +#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS)
298 +static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
299 + struct bcma_device *core)
300 +{
301 + struct device_node *node;
302 + u64 size;
303 + const __be32 *reg;
304 +
305 + if (!parent || !parent->dev.of_node)
306 + return NULL;
307 +
308 + for_each_child_of_node(parent->dev.of_node, node) {
309 + reg = of_get_address(node, 0, &size, NULL);
310 + if (!reg)
311 + continue;
312 + if (of_translate_address(node, reg) == core->addr)
313 + return node;
314 + }
315 + return NULL;
316 +}
317 +
318 +static void bcma_of_fill_device(struct platform_device *parent,
319 + struct bcma_device *core)
320 +{
321 + struct device_node *node;
322 +
323 + node = bcma_of_find_child_device(parent, core);
324 + if (node)
325 + core->dev.of_node = node;
326 +}
327 +#else
328 +static void bcma_of_fill_device(struct platform_device *parent,
329 + struct bcma_device *core)
330 +{
331 +}
332 +#endif /* CONFIG_OF */
333 +
334 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)
335 +{
336 + core->dev.release = bcma_release_core_dev;
337 + core->dev.bus = &bcma_bus_type;
338 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
339 +
340 + switch (bus->hosttype) {
341 + case BCMA_HOSTTYPE_PCI:
342 + core->dev.parent = &bus->host_pci->dev;
343 + core->dma_dev = &bus->host_pci->dev;
344 + core->irq = bus->host_pci->irq;
345 + break;
346 + case BCMA_HOSTTYPE_SOC:
347 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
348 + if (bus->host_pdev) {
349 + core->dma_dev = &bus->host_pdev->dev;
350 + core->dev.parent = &bus->host_pdev->dev;
351 + bcma_of_fill_device(bus->host_pdev, core);
352 + } else {
353 + core->dma_dev = &core->dev;
354 + }
355 + break;
356 + case BCMA_HOSTTYPE_SDIO:
357 + break;
358 + }
359 +}
360 +
361 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
362 +{
363 + int err;
364 +
365 + err = device_register(&core->dev);
366 + if (err) {
367 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
368 + core->id.id);
369 + put_device(&core->dev);
370 + return;
371 + }
372 + core->dev_registered = true;
373 +}
374 +
375 +static int bcma_register_devices(struct bcma_bus *bus)
376 {
377 struct bcma_device *core;
378 - int err, dev_id = 0;
379 + int err;
380
381 list_for_each_entry(core, &bus->cores, list) {
382 /* We support that cores ourself */
383 switch (core->id.id) {
384 case BCMA_CORE_4706_CHIPCOMMON:
385 case BCMA_CORE_CHIPCOMMON:
386 + case BCMA_CORE_NS_CHIPCOMMON_B:
387 case BCMA_CORE_PCI:
388 case BCMA_CORE_PCIE:
389 + case BCMA_CORE_PCIE2:
390 case BCMA_CORE_MIPS_74K:
391 case BCMA_CORE_4706_MAC_GBIT_COMMON:
392 continue;
393 }
394
395 + /* Early cores were already registered */
396 + if (bcma_is_core_needed_early(core->id.id))
397 + continue;
398 +
399 /* Only first GMAC core on BCM4706 is connected and working */
400 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
401 core->core_unit > 0)
402 continue;
403
404 - core->dev.release = bcma_release_core_dev;
405 - core->dev.bus = &bcma_bus_type;
406 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
407 -
408 - switch (bus->hosttype) {
409 - case BCMA_HOSTTYPE_PCI:
410 - core->dev.parent = &bus->host_pci->dev;
411 - core->dma_dev = &bus->host_pci->dev;
412 - core->irq = bus->host_pci->irq;
413 - break;
414 - case BCMA_HOSTTYPE_SOC:
415 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
416 - core->dma_dev = &core->dev;
417 - break;
418 - case BCMA_HOSTTYPE_SDIO:
419 - break;
420 - }
421 -
422 - err = device_register(&core->dev);
423 - if (err) {
424 - bcma_err(bus,
425 - "Could not register dev for core 0x%03X\n",
426 - core->id.id);
427 - put_device(&core->dev);
428 - continue;
429 - }
430 - core->dev_registered = true;
431 - dev_id++;
432 + bcma_register_core(bus, core);
433 }
434
435 #ifdef CONFIG_BCMA_DRIVER_MIPS
436 @@ -246,6 +315,12 @@ int bcma_bus_register(struct bcma_bus *b
437 bcma_core_chipcommon_early_init(&bus->drv_cc);
438 }
439
440 + /* Cores providing flash access go before SPROM init */
441 + list_for_each_entry(core, &bus->cores, list) {
442 + if (bcma_is_core_needed_early(core->id.id))
443 + bcma_register_core(bus, core);
444 + }
445 +
446 /* Try to get SPROM */
447 err = bcma_sprom_get(bus);
448 if (err == -ENOENT) {
449 @@ -260,6 +335,13 @@ int bcma_bus_register(struct bcma_bus *b
450 bcma_core_chipcommon_init(&bus->drv_cc);
451 }
452
453 + /* Init CC core */
454 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
455 + if (core) {
456 + bus->drv_cc_b.core = core;
457 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
458 + }
459 +
460 /* Init MIPS core */
461 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
462 if (core) {
463 @@ -281,6 +363,13 @@ int bcma_bus_register(struct bcma_bus *b
464 bcma_core_pci_init(&bus->drv_pci[1]);
465 }
466
467 + /* Init PCIe Gen 2 core */
468 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
469 + if (core) {
470 + bus->drv_pcie2.core = core;
471 + bcma_core_pcie2_init(&bus->drv_pcie2);
472 + }
473 +
474 /* Init GBIT MAC COMMON core */
475 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
476 if (core) {
477 @@ -289,7 +378,7 @@ int bcma_bus_register(struct bcma_bus *b
478 }
479
480 /* Register found cores */
481 - bcma_register_cores(bus);
482 + bcma_register_devices(bus);
483
484 bcma_info(bus, "Bus registered\n");
485
486 @@ -307,6 +396,8 @@ void bcma_bus_unregister(struct bcma_bus
487 else if (err)
488 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
489
490 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
491 +
492 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
493 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
494 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
495 @@ -326,8 +417,6 @@ int __init bcma_bus_early_register(struc
496 struct bcma_device *core;
497 struct bcma_device_id match;
498
499 - bcma_init_bus(bus);
500 -
501 match.manuf = BCMA_MANUF_BCM;
502 match.id = bcma_cc_core_id(bus);
503 match.class = BCMA_CL_SIM;
504 @@ -486,6 +575,11 @@ static int __init bcma_modinit(void)
505 if (err)
506 return err;
507
508 + err = bcma_host_soc_register_driver();
509 + if (err) {
510 + pr_err("SoC host initialization failed\n");
511 + err = 0;
512 + }
513 #ifdef CONFIG_BCMA_HOST_PCI
514 err = bcma_host_pci_init();
515 if (err) {
516 @@ -503,6 +597,7 @@ static void __exit bcma_modexit(void)
517 #ifdef CONFIG_BCMA_HOST_PCI
518 bcma_host_pci_exit();
519 #endif
520 + bcma_host_soc_unregister_driver();
521 bus_unregister(&bcma_bus_type);
522 }
523 module_exit(bcma_modexit)
524 --- a/drivers/bcma/sprom.c
525 +++ b/drivers/bcma/sprom.c
526 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
527 SPEX(_field[7], _offset + 14, _mask, _shift); \
528 } while (0)
529
530 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
531 +{
532 + u16 v;
533 + u8 gain;
534 +
535 + v = in[SPOFF(offset)];
536 + gain = (v & mask) >> shift;
537 + if (gain == 0xFF) {
538 + gain = 8; /* If unset use 2dBm */
539 + } else {
540 + /* Q5.2 Fractional part is stored in 0xC0 */
541 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
542 + }
543 +
544 + return (s8)gain;
545 +}
546 +
547 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
548 {
549 u16 v, o;
550 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
551 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
552
553 /* Extract the antenna gain values. */
554 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
555 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
556 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
557 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
558 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
559 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
560 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
561 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
562 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
563 + SSB_SPROM8_AGAIN01,
564 + SSB_SPROM8_AGAIN0,
565 + SSB_SPROM8_AGAIN0_SHIFT);
566 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
567 + SSB_SPROM8_AGAIN01,
568 + SSB_SPROM8_AGAIN1,
569 + SSB_SPROM8_AGAIN1_SHIFT);
570 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
571 + SSB_SPROM8_AGAIN23,
572 + SSB_SPROM8_AGAIN2,
573 + SSB_SPROM8_AGAIN2_SHIFT);
574 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
575 + SSB_SPROM8_AGAIN23,
576 + SSB_SPROM8_AGAIN3,
577 + SSB_SPROM8_AGAIN3_SHIFT);
578
579 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
580 SSB_SPROM8_LEDDC_ON_SHIFT);
581 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
582 /* for these chips OTP is always available */
583 present = true;
584 break;
585 + case BCMA_CHIP_ID_BCM43131:
586 + case BCMA_CHIP_ID_BCM43217:
587 case BCMA_CHIP_ID_BCM43227:
588 case BCMA_CHIP_ID_BCM43228:
589 case BCMA_CHIP_ID_BCM43428:
590 --- a/include/linux/bcma/bcma.h
591 +++ b/include/linux/bcma/bcma.h
592 @@ -6,6 +6,7 @@
593
594 #include <linux/bcma/bcma_driver_chipcommon.h>
595 #include <linux/bcma/bcma_driver_pci.h>
596 +#include <linux/bcma/bcma_driver_pcie2.h>
597 #include <linux/bcma/bcma_driver_mips.h>
598 #include <linux/bcma/bcma_driver_gmac_cmn.h>
599 #include <linux/ssb/ssb.h> /* SPROM sharing */
600 @@ -72,17 +73,17 @@ struct bcma_host_ops {
601 /* Core-ID values. */
602 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
603 #define BCMA_CORE_4706_CHIPCOMMON 0x500
604 -#define BCMA_CORE_PCIEG2 0x501
605 -#define BCMA_CORE_DMA 0x502
606 -#define BCMA_CORE_SDIO3 0x503
607 -#define BCMA_CORE_USB20 0x504
608 -#define BCMA_CORE_USB30 0x505
609 -#define BCMA_CORE_A9JTAG 0x506
610 -#define BCMA_CORE_DDR23 0x507
611 -#define BCMA_CORE_ROM 0x508
612 -#define BCMA_CORE_NAND 0x509
613 -#define BCMA_CORE_QSPI 0x50A
614 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
615 +#define BCMA_CORE_NS_PCIEG2 0x501
616 +#define BCMA_CORE_NS_DMA 0x502
617 +#define BCMA_CORE_NS_SDIO3 0x503
618 +#define BCMA_CORE_NS_USB20 0x504
619 +#define BCMA_CORE_NS_USB30 0x505
620 +#define BCMA_CORE_NS_A9JTAG 0x506
621 +#define BCMA_CORE_NS_DDR23 0x507
622 +#define BCMA_CORE_NS_ROM 0x508
623 +#define BCMA_CORE_NS_NAND 0x509
624 +#define BCMA_CORE_NS_QSPI 0x50A
625 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
626 #define BCMA_CORE_4706_SOC_RAM 0x50E
627 #define BCMA_CORE_ARMCA9 0x510
628 #define BCMA_CORE_4706_MAC_GBIT 0x52D
629 @@ -157,6 +158,9 @@ struct bcma_host_ops {
630 /* Chip IDs of PCIe devices */
631 #define BCMA_CHIP_ID_BCM4313 0x4313
632 #define BCMA_CHIP_ID_BCM43142 43142
633 +#define BCMA_CHIP_ID_BCM43131 43131
634 +#define BCMA_CHIP_ID_BCM43217 43217
635 +#define BCMA_CHIP_ID_BCM43222 43222
636 #define BCMA_CHIP_ID_BCM43224 43224
637 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
638 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
639 @@ -263,7 +267,7 @@ struct bcma_device {
640 u8 core_unit;
641
642 u32 addr;
643 - u32 addr1;
644 + u32 addr_s[8];
645 u32 wrap;
646
647 void __iomem *io_addr;
648 @@ -319,6 +323,8 @@ struct bcma_bus {
649 struct pci_dev *host_pci;
650 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
651 struct sdio_func *host_sdio;
652 + /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
653 + struct platform_device *host_pdev;
654 };
655
656 struct bcma_chipinfo chipinfo;
657 @@ -328,11 +334,12 @@ struct bcma_bus {
658 struct bcma_device *mapped_core;
659 struct list_head cores;
660 u8 nr_cores;
661 - u8 init_done:1;
662 u8 num;
663
664 struct bcma_drv_cc drv_cc;
665 + struct bcma_drv_cc_b drv_cc_b;
666 struct bcma_drv_pci drv_pci[2];
667 + struct bcma_drv_pcie2 drv_pcie2;
668 struct bcma_drv_mips drv_mips;
669 struct bcma_drv_gmac_cmn drv_gmac_cmn;
670
671 --- /dev/null
672 +++ b/include/linux/bcma/bcma_driver_pcie2.h
673 @@ -0,0 +1,158 @@
674 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
675 +#define LINUX_BCMA_DRIVER_PCIE2_H_
676 +
677 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
678 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
679 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
680 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
681 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
682 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
683 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
684 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
685 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
686 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
687 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
688 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
689 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
690 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
691 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
692 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
693 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
694 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
695 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
696 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
697 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
698 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
699 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
700 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
701 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
702 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
703 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
704 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
705 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
706 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
707 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
708 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
709 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
710 +#define PCIE2_LTR_ACTIVE 2
711 +#define PCIE2_LTR_ACTIVE_IDLE 1
712 +#define PCIE2_LTR_SLEEP 0
713 +#define PCIE2_LTR_FINAL_MASK 0x300
714 +#define PCIE2_LTR_FINAL_SHIFT 8
715 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
716 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
717 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
718 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
719 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
720 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
721 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
722 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
723 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
724 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
725 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
726 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
727 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
728 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
729 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
730 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
731 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
732 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
733 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
734 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
735 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
736 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
737 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
738 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
739 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
740 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
741 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
742 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
743 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
744 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
745 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
746 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
747 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
748 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
749 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
750 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
751 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
752 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
753 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
754 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
755 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
756 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
757 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
758 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
759 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
760 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
761 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
762 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
763 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
764 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
765 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
766 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
767 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
768 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
769 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
770 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
771 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
772 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
773 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
774 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
775 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
776 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
777 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
778 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
779 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
780 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
781 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
782 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
783 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
784 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
785 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
786 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
787 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
788 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
789 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
790 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
791 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
792 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
793 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
794 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
795 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
796 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
797 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
798 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
799 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
800 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
801 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
802 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
803 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
804 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
805 +
806 +/* PCIE gen2 config regs */
807 +#define PCIE2_INTSTATUS 0x090
808 +#define PCIE2_INTMASK 0x094
809 +#define PCIE2_SBMBX 0x098
810 +
811 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
812 +
813 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
814 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
815 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
816 +
817 +struct bcma_drv_pcie2 {
818 + struct bcma_device *core;
819 +};
820 +
821 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
822 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
823 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
824 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
825 +
826 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
827 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
828 +
829 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
830 +
831 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
832 --- a/drivers/bcma/scan.c
833 +++ b/drivers/bcma/scan.c
834 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
835 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
836 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
837 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
838 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
839 - { BCMA_CORE_DMA, "DMA" },
840 - { BCMA_CORE_SDIO3, "SDIO3" },
841 - { BCMA_CORE_USB20, "USB 2.0" },
842 - { BCMA_CORE_USB30, "USB 3.0" },
843 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
844 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
845 - { BCMA_CORE_ROM, "ROM" },
846 - { BCMA_CORE_NAND, "NAND flash controller" },
847 - { BCMA_CORE_QSPI, "SPI flash controller" },
848 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
849 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
850 + { BCMA_CORE_NS_DMA, "DMA" },
851 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
852 + { BCMA_CORE_NS_USB20, "USB 2.0" },
853 + { BCMA_CORE_NS_USB30, "USB 3.0" },
854 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
855 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
856 + { BCMA_CORE_NS_ROM, "ROM" },
857 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
858 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
859 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
860 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
861 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
862 { BCMA_CORE_ALTA, "ALTA (I2S)" },
863 @@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
864 struct bcma_device *core)
865 {
866 u32 tmp;
867 - u8 i, j;
868 + u8 i, j, k;
869 s32 cia, cib;
870 u8 ports[2], wrappers[2];
871
872 @@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
873 /* Some specific cores don't need wrappers */
874 switch (core->id.id) {
875 case BCMA_CORE_4706_MAC_GBIT_COMMON:
876 + case BCMA_CORE_NS_CHIPCOMMON_B:
877 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
878 break;
879 default:
880 @@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm
881 core->addr = tmp;
882
883 /* get & parse slave ports */
884 + k = 0;
885 for (i = 0; i < ports[1]; i++) {
886 for (j = 0; ; j++) {
887 tmp = bcma_erom_get_addr_desc(bus, eromptr,
888 @@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm
889 /* pr_debug("erom: slave port %d "
890 * "has %d descriptors\n", i, j); */
891 break;
892 - } else {
893 - if (i == 0 && j == 0)
894 - core->addr1 = tmp;
895 + } else if (k < ARRAY_SIZE(core->addr_s)) {
896 + core->addr_s[k] = tmp;
897 + k++;
898 }
899 }
900 }
901 @@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm
902 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
903 if (!core->io_addr)
904 return -ENOMEM;
905 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
906 - if (!core->io_wrap) {
907 - iounmap(core->io_addr);
908 - return -ENOMEM;
909 + if (core->wrap) {
910 + core->io_wrap = ioremap_nocache(core->wrap,
911 + BCMA_CORE_SIZE);
912 + if (!core->io_wrap) {
913 + iounmap(core->io_addr);
914 + return -ENOMEM;
915 + }
916 }
917 }
918 return 0;
919 @@ -434,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
920 {
921 s32 tmp;
922 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
923 -
924 - if (bus->init_done)
925 - return;
926 + char chip_id[8];
927
928 INIT_LIST_HEAD(&bus->cores);
929 bus->nr_cores = 0;
930 @@ -447,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
931 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
932 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
933 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
934 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
935 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
936
937 - bus->init_done = true;
938 + snprintf(chip_id, ARRAY_SIZE(chip_id),
939 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
940 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
941 + chip_id, chipinfo->rev, chipinfo->pkg);
942 }
943
944 int bcma_bus_scan(struct bcma_bus *bus)
945 @@ -460,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
946
947 int err, core_num = 0;
948
949 - bcma_init_bus(bus);
950 -
951 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
952 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
953 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
954 @@ -503,6 +505,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
955 bus->nr_cores++;
956 other_core = bcma_find_core_reverse(bus, core->id.id);
957 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
958 + bcma_prepare_core(bus, core);
959
960 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
961 core->core_index, bcma_device_name(&core->id),
962 --- a/drivers/bcma/host_soc.c
963 +++ b/drivers/bcma/host_soc.c
964 @@ -7,6 +7,9 @@
965
966 #include "bcma_private.h"
967 #include "scan.h"
968 +#include <linux/slab.h>
969 +#include <linux/module.h>
970 +#include <linux/of_address.h>
971 #include <linux/bcma/bcma.h>
972 #include <linux/bcma/bcma_soc.h>
973
974 @@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st
975
976 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
977 {
978 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
979 + return ~0;
980 return readl(core->io_wrap + offset);
981 }
982
983 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
984 u32 value)
985 {
986 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
987 + return;
988 writel(value, core->io_wrap + offset);
989 }
990
991 @@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h
992 int __init bcma_host_soc_register(struct bcma_soc *soc)
993 {
994 struct bcma_bus *bus = &soc->bus;
995 - int err;
996
997 /* iomap only first core. We have to read some register on this core
998 * to scan the bus.
999 @@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct
1000 /* Host specific */
1001 bus->hosttype = BCMA_HOSTTYPE_SOC;
1002 bus->ops = &bcma_host_soc_ops;
1003 + bus->host_pdev = NULL;
1004
1005 - /* Register */
1006 + /* Initialize struct, detect chip */
1007 + bcma_init_bus(bus);
1008 +
1009 + return 0;
1010 +}
1011 +
1012 +int __init bcma_host_soc_init(struct bcma_soc *soc)
1013 +{
1014 + struct bcma_bus *bus = &soc->bus;
1015 + int err;
1016 +
1017 + /* Scan bus and initialize it */
1018 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
1019 if (err)
1020 iounmap(bus->mmio);
1021
1022 return err;
1023 }
1024 +
1025 +#ifdef CONFIG_OF
1026 +static int bcma_host_soc_probe(struct platform_device *pdev)
1027 +{
1028 + struct device *dev = &pdev->dev;
1029 + struct device_node *np = dev->of_node;
1030 + struct bcma_bus *bus;
1031 + int err;
1032 +
1033 + /* Alloc */
1034 + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
1035 + if (!bus)
1036 + return -ENOMEM;
1037 +
1038 + /* Map MMIO */
1039 + bus->mmio = of_iomap(np, 0);
1040 + if (!bus->mmio)
1041 + return -ENOMEM;
1042 +
1043 + /* Host specific */
1044 + bus->hosttype = BCMA_HOSTTYPE_SOC;
1045 + bus->ops = &bcma_host_soc_ops;
1046 + bus->host_pdev = pdev;
1047 +
1048 + /* Initialize struct, detect chip */
1049 + bcma_init_bus(bus);
1050 +
1051 + /* Register */
1052 + err = bcma_bus_register(bus);
1053 + if (err)
1054 + goto err_unmap_mmio;
1055 +
1056 + platform_set_drvdata(pdev, bus);
1057 +
1058 + return err;
1059 +
1060 +err_unmap_mmio:
1061 + iounmap(bus->mmio);
1062 + return err;
1063 +}
1064 +
1065 +static int bcma_host_soc_remove(struct platform_device *pdev)
1066 +{
1067 + struct bcma_bus *bus = platform_get_drvdata(pdev);
1068 +
1069 + bcma_bus_unregister(bus);
1070 + iounmap(bus->mmio);
1071 + platform_set_drvdata(pdev, NULL);
1072 +
1073 + return 0;
1074 +}
1075 +
1076 +static const struct of_device_id bcma_host_soc_of_match[] = {
1077 + { .compatible = "brcm,bus-axi", },
1078 + {},
1079 +};
1080 +MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
1081 +
1082 +static struct platform_driver bcma_host_soc_driver = {
1083 + .driver = {
1084 + .name = "bcma-host-soc",
1085 + .of_match_table = bcma_host_soc_of_match,
1086 + },
1087 + .probe = bcma_host_soc_probe,
1088 + .remove = bcma_host_soc_remove,
1089 +};
1090 +
1091 +int __init bcma_host_soc_register_driver(void)
1092 +{
1093 + return platform_driver_register(&bcma_host_soc_driver);
1094 +}
1095 +
1096 +void __exit bcma_host_soc_unregister_driver(void)
1097 +{
1098 + platform_driver_unregister(&bcma_host_soc_driver);
1099 +}
1100 +#endif /* CONFIG_OF */
1101 --- a/drivers/bcma/driver_mips.c
1102 +++ b/drivers/bcma/driver_mips.c
1103 @@ -21,6 +21,14 @@
1104 #include <linux/serial_reg.h>
1105 #include <linux/time.h>
1106
1107 +enum bcma_boot_dev {
1108 + BCMA_BOOT_DEV_UNK = 0,
1109 + BCMA_BOOT_DEV_ROM,
1110 + BCMA_BOOT_DEV_PARALLEL,
1111 + BCMA_BOOT_DEV_SERIAL,
1112 + BCMA_BOOT_DEV_NAND,
1113 +};
1114 +
1115 static const char * const part_probes[] = { "bcm47xxpart", NULL };
1116
1117 static struct physmap_flash_data bcma_pflash_data = {
1118 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1119 }
1120 EXPORT_SYMBOL(bcma_cpu_clock);
1121
1122 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
1123 +{
1124 + struct bcma_drv_cc *cc = &bus->drv_cc;
1125 + u8 cc_rev = cc->core->id.rev;
1126 +
1127 + if (cc_rev == 42) {
1128 + struct bcma_device *core;
1129 +
1130 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
1131 + if (core) {
1132 + switch (bcma_aread32(core, BCMA_IOST) &
1133 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
1134 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
1135 + return BCMA_BOOT_DEV_SERIAL;
1136 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
1137 + return BCMA_BOOT_DEV_NAND;
1138 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
1139 + default:
1140 + return BCMA_BOOT_DEV_ROM;
1141 + }
1142 + }
1143 + } else {
1144 + if (cc_rev == 38) {
1145 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
1146 + return BCMA_BOOT_DEV_NAND;
1147 + else if (cc->status & BIT(5))
1148 + return BCMA_BOOT_DEV_ROM;
1149 + }
1150 +
1151 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
1152 + BCMA_CC_FLASHT_PARA)
1153 + return BCMA_BOOT_DEV_PARALLEL;
1154 + else
1155 + return BCMA_BOOT_DEV_SERIAL;
1156 + }
1157 +
1158 + return BCMA_BOOT_DEV_SERIAL;
1159 +}
1160 +
1161 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1162 {
1163 struct bcma_bus *bus = mcore->core->bus;
1164 struct bcma_drv_cc *cc = &bus->drv_cc;
1165 struct bcma_pflash *pflash = &cc->pflash;
1166 + enum bcma_boot_dev boot_dev;
1167
1168 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1169 case BCMA_CC_FLASHT_STSER:
1170 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
1171 bcma_nflash_init(cc);
1172 }
1173 }
1174 +
1175 + /* Determine flash type this SoC boots from */
1176 + boot_dev = bcma_boot_dev(bus);
1177 + switch (boot_dev) {
1178 + case BCMA_BOOT_DEV_PARALLEL:
1179 + case BCMA_BOOT_DEV_SERIAL:
1180 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
1181 + break;
1182 + case BCMA_BOOT_DEV_NAND:
1183 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
1184 + break;
1185 + default:
1186 + break;
1187 + }
1188 }
1189
1190 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1191 --- a/include/linux/bcma/bcma_regs.h
1192 +++ b/include/linux/bcma/bcma_regs.h
1193 @@ -39,6 +39,11 @@
1194 #define BCMA_RESET_CTL_RESET 0x0001
1195 #define BCMA_RESET_ST 0x0804
1196
1197 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
1198 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
1199 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
1200 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
1201 +
1202 /* BCMA PCI config space registers. */
1203 #define BCMA_PCI_PMCSR 0x44
1204 #define BCMA_PCI_PE 0x100
1205 --- a/drivers/usb/host/bcma-hcd.c
1206 +++ b/drivers/usb/host/bcma-hcd.c
1207 @@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
1208 bcma_hcd_init_chip(dev);
1209
1210 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
1211 - ohci_addr = dev->addr1;
1212 + ohci_addr = dev->addr_s[0];
1213 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
1214 && chipinfo->rev == 0)
1215 ohci_addr = 0x18009000;
1216 --- a/drivers/bcma/bcma_private.h
1217 +++ b/drivers/bcma/bcma_private.h
1218 @@ -24,6 +24,7 @@ struct bcma_bus;
1219 /* main.c */
1220 bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1221 int timeout);
1222 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core);
1223 int bcma_bus_register(struct bcma_bus *bus);
1224 void bcma_bus_unregister(struct bcma_bus *bus);
1225 int __init bcma_bus_early_register(struct bcma_bus *bus,
1226 @@ -50,6 +51,10 @@ void bcma_chipco_serial_init(struct bcma
1227 extern struct platform_device bcma_pflash_dev;
1228 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1229
1230 +/* driver_chipcommon_b.c */
1231 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
1232 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
1233 +
1234 /* driver_chipcommon_pmu.c */
1235 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
1236 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
1237 @@ -84,6 +89,20 @@ extern int __init bcma_host_pci_init(voi
1238 extern void __exit bcma_host_pci_exit(void);
1239 #endif /* CONFIG_BCMA_HOST_PCI */
1240
1241 +/* host_soc.c */
1242 +#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF)
1243 +extern int __init bcma_host_soc_register_driver(void);
1244 +extern void __exit bcma_host_soc_unregister_driver(void);
1245 +#else
1246 +static inline int __init bcma_host_soc_register_driver(void)
1247 +{
1248 + return 0;
1249 +}
1250 +static inline void __exit bcma_host_soc_unregister_driver(void)
1251 +{
1252 +}
1253 +#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
1254 +
1255 /* driver_pci.c */
1256 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
1257
1258 --- /dev/null
1259 +++ b/drivers/bcma/driver_chipcommon_b.c
1260 @@ -0,0 +1,61 @@
1261 +/*
1262 + * Broadcom specific AMBA
1263 + * ChipCommon B Unit driver
1264 + *
1265 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
1266 + *
1267 + * Licensed under the GNU/GPL. See COPYING for details.
1268 + */
1269 +
1270 +#include "bcma_private.h"
1271 +#include <linux/export.h>
1272 +#include <linux/bcma/bcma.h>
1273 +
1274 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
1275 + u32 value, int timeout)
1276 +{
1277 + unsigned long deadline = jiffies + timeout;
1278 + u32 val;
1279 +
1280 + do {
1281 + val = readl(addr);
1282 + if ((val & mask) == value)
1283 + return true;
1284 + cpu_relax();
1285 + udelay(10);
1286 + } while (!time_after_eq(jiffies, deadline));
1287 +
1288 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
1289 +
1290 + return false;
1291 +}
1292 +
1293 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
1294 +{
1295 + struct bcma_bus *bus = ccb->core->bus;
1296 +
1297 + writel(offset, ccb->mii + 0x00);
1298 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1299 + writel(value, ccb->mii + 0x04);
1300 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1301 +}
1302 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
1303 +
1304 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
1305 +{
1306 + if (ccb->setup_done)
1307 + return 0;
1308 +
1309 + ccb->setup_done = 1;
1310 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
1311 + if (!ccb->mii)
1312 + return -ENOMEM;
1313 +
1314 + return 0;
1315 +}
1316 +
1317 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
1318 +{
1319 + if (ccb->mii)
1320 + iounmap(ccb->mii);
1321 +}
1322 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1323 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1324 @@ -644,6 +644,12 @@ struct bcma_drv_cc {
1325 #endif
1326 };
1327
1328 +struct bcma_drv_cc_b {
1329 + struct bcma_device *core;
1330 + u8 setup_done:1;
1331 + void __iomem *mii;
1332 +};
1333 +
1334 /* Register access */
1335 #define bcma_cc_read32(cc, offset) \
1336 bcma_read32((cc)->core, offset)
1337 @@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1338
1339 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1340
1341 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1342 +
1343 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1344 --- a/arch/mips/bcm47xx/setup.c
1345 +++ b/arch/mips/bcm47xx/setup.c
1346 @@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma
1347
1348 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
1349 if (err)
1350 + panic("Failed to register BCMA bus (err %d)", err);
1351 +
1352 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
1353 + if (err)
1354 panic("Failed to initialize BCMA bus (err %d)", err);
1355
1356 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
1357 --- a/include/linux/bcma/bcma_soc.h
1358 +++ b/include/linux/bcma/bcma_soc.h
1359 @@ -10,6 +10,7 @@ struct bcma_soc {
1360 };
1361
1362 int __init bcma_host_soc_register(struct bcma_soc *soc);
1363 +int __init bcma_host_soc_init(struct bcma_soc *soc);
1364
1365 int bcma_bus_register(struct bcma_bus *bus);
1366
1367 --- /dev/null
1368 +++ b/Documentation/devicetree/bindings/bus/bcma.txt
1369 @@ -0,0 +1,32 @@
1370 +Driver for ARM AXI Bus with Broadcom Plugins (bcma)
1371 +
1372 +Required properties:
1373 +
1374 +- compatible : brcm,bus-axi
1375 +
1376 +- reg : iomem address range of chipcommon core
1377 +
1378 +The cores on the AXI bus are automatically detected by bcma with the
1379 +memory ranges they are using and they get registered afterwards.
1380 +
1381 +The top-level axi bus may contain children representing attached cores
1382 +(devices). This is needed since some hardware details can't be auto
1383 +detected (e.g. IRQ numbers). Also some of the cores may be responsible
1384 +for extra things, e.g. ChipCommon providing access to the GPIO chip.
1385 +
1386 +Example:
1387 +
1388 + axi@18000000 {
1389 + compatible = "brcm,bus-axi";
1390 + reg = <0x18000000 0x1000>;
1391 + ranges = <0x00000000 0x18000000 0x00100000>;
1392 + #address-cells = <1>;
1393 + #size-cells = <1>;
1394 +
1395 + chipcommon {
1396 + reg = <0x00000000 0x1000>;
1397 +
1398 + gpio-controller;
1399 + #gpio-cells = <2>;
1400 + };
1401 + };
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