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[openwrt/staging/yousong.git] / target / linux / ppc40x / patches / 008-openrb-medium.patch
1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
3 @@ -71,7 +71,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
4 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
5 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
6 cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c \
7 - cuboot-openrb-light.c
8 + cuboot-openrb-light.c cuboot-openrb-medium.c
9 src-boot := $(src-wlib) $(src-plat) empty.c
10
11 src-boot := $(addprefix $(obj)/, $(src-boot))
12 @@ -218,6 +218,7 @@ image-$(CONFIG_ACADIA) += cuImage.acad
13 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
14 image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
15 image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light
16 +image-$(CONFIG_OPENRB_MEDIUM) += cuImage.openrb-medium
17
18 # Board ports in arch/powerpc/platform/44x/Kconfig
19 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
20 --- a/arch/powerpc/platforms/40x/Kconfig
21 +++ b/arch/powerpc/platforms/40x/Kconfig
22 @@ -89,6 +89,16 @@ config OPENRB_LIGHT
23 help
24 This option enables support for the OpenRB Light board.
25
26 +config OPENRB_MEDIUM
27 + bool "OpenRB Medium"
28 + depends on 40x
29 + default n
30 + select PPC40x_SIMPLE
31 + select 405EP
32 + select PCI
33 + help
34 + This option enables support for the OpenRB Medium board.
35 +
36 #config REDWOOD_5
37 # bool "Redwood-5"
38 # depends on 40x
39 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
40 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
41 @@ -55,6 +55,7 @@ static char *board[] __initdata = {
42 "magicboxv1",
43 "magicboxv2",
44 "openrb,light",
45 + "openrb,medium",
46 };
47
48 static int __init ppc40x_probe(void)
49 --- /dev/null
50 +++ b/arch/powerpc/boot/cuboot-openrb-medium.c
51 @@ -0,0 +1,69 @@
52 +/*
53 + * Old U-boot compatibility for OpenRB Medium
54 + *
55 + * Author: Gabor Juhos <juhosg@openwrt.org>
56 + *
57 + * This program is free software; you can redistribute it and/or modify it
58 + * under the terms of the GNU General Public License version 2 as published
59 + * by the Free Software Foundation.
60 + */
61 +
62 +#include "ops.h"
63 +#include "io.h"
64 +#include "dcr.h"
65 +#include "stdio.h"
66 +#include "4xx.h"
67 +#include "44x.h"
68 +#include "cuboot.h"
69 +
70 +#define TARGET_4xx
71 +#define TARGET_405EP
72 +#include "ppcboot.h"
73 +
74 +static bd_t bd;
75 +
76 +static void fixup_cf_card(void)
77 +{
78 +#define DCRN_CPC0_PCI_BASE 0xf9
79 +#define CF_CS0_BASE 0xff100000
80 +#define CF_CS1_BASE 0xff200000
81 +
82 + /* Turn on PerWE instead of PCIsomething */
83 + mtdcr(DCRN_CPC0_PCI_BASE,
84 + mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
85 +
86 + /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
87 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
88 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
89 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
90 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
91 +
92 + /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
93 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
94 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
95 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
96 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
97 +
98 +#undef DCRN_CPC0_PCI_BASE
99 +#undef CF_CS0_BASE
100 +#undef CF_CS1_BASE
101 +}
102 +
103 +static void openrb_light_fixups(void)
104 +{
105 + fixup_cf_card();
106 + ibm405ep_fixup_clocks(33333000);
107 + ibm4xx_sdram_fixup_memsize();
108 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
109 +}
110 +
111 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
112 + unsigned long r6, unsigned long r7)
113 +{
114 + CUBOOT_INIT();
115 + platform_ops.fixups = openrb_light_fixups;
116 + platform_ops.exit = ibm40x_dbcr_reset;
117 + fdt_init(_dtb_start);
118 + serial_console_init();
119 +}
120 +
121 --- /dev/null
122 +++ b/arch/powerpc/boot/dts/openrb-medium.dts
123 @@ -0,0 +1,281 @@
124 +/*
125 + * Device Tree Source for OpenRB Medium board
126 + *
127 + * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
128 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
129 + *
130 + * Based on walnut.dts
131 + *
132 + * This file is licensed under the terms of the GNU General Public
133 + * License version 2. This program is licensed "as is" without
134 + * any warranty of any kind, whether express or implied.
135 + */
136 +
137 +/dts-v1/;
138 +
139 +/ {
140 + #address-cells = <1>;
141 + #size-cells = <1>;
142 + model = "openrb,medium";
143 + compatible = "openrb,medium";
144 + dcr-parent = <&{/cpus/cpu@0}>;
145 +
146 + aliases {
147 + ethernet0 = &EMAC0;
148 + ethernet1 = &EMAC1;
149 + serial0 = &UART0;
150 + serial1 = &UART1;
151 + };
152 +
153 + cpus {
154 + #address-cells = <1>;
155 + #size-cells = <0>;
156 +
157 + cpu@0 {
158 + device_type = "cpu";
159 + model = "PowerPC,405EP";
160 + reg = <0x00000000>;
161 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
162 + timebase-frequency = <0>; /* Filled in by zImage */
163 + i-cache-line-size = <20>;
164 + d-cache-line-size = <20>;
165 + i-cache-size = <4000>;
166 + d-cache-size = <4000>;
167 + dcr-controller;
168 + dcr-access-method = "native";
169 + };
170 + };
171 +
172 + memory {
173 + device_type = "memory";
174 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
175 + };
176 +
177 + UIC0: interrupt-controller {
178 + compatible = "ibm,uic";
179 + interrupt-controller;
180 + cell-index = <0>;
181 + dcr-reg = <0x0c0 0x009>;
182 + #address-cells = <0>;
183 + #size-cells = <0>;
184 + #interrupt-cells = <2>;
185 + };
186 +
187 + plb {
188 + compatible = "ibm,plb3";
189 + #address-cells = <1>;
190 + #size-cells = <1>;
191 + ranges;
192 + clock-frequency = <0>; /* Filled in by zImage */
193 +
194 + SDRAM0: memory-controller {
195 + compatible = "ibm,sdram-405ep";
196 + dcr-reg = <0x010 0x002>;
197 + };
198 +
199 + MAL: mcmal {
200 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
201 + dcr-reg = <0x180 0x062>;
202 + num-tx-chans = <4>;
203 + num-rx-chans = <2>;
204 + interrupt-parent = <&UIC0>;
205 + interrupts = <
206 + 0xb 0x4 /* TXEOB */
207 + 0xc 0x4 /* RXEOB */
208 + 0xa 0x4 /* SERR */
209 + 0xd 0x4 /* TXDE */
210 + 0xe 0x4 /* RXDE */>;
211 + };
212 +
213 + POB0: opb {
214 + compatible = "ibm,opb-405ep", "ibm,opb";
215 + #address-cells = <1>;
216 + #size-cells = <1>;
217 + ranges = <0xef600000 0xef600000 0x00a00000>;
218 + dcr-reg = <0x0a0 0x005>;
219 + clock-frequency = <0>; /* Filled in by zImage */
220 +
221 + UART0: serial@ef600300 {
222 + device_type = "serial";
223 + compatible = "ns16550";
224 + reg = <0xef600300 0x00000008>;
225 + virtual-reg = <0xef600300>;
226 + clock-frequency = <0>; /* Filled in by zImage */
227 + current-speed = <115200>;
228 + interrupt-parent = <&UIC0>;
229 + interrupts = <0x0 0x4>;
230 + };
231 +
232 + UART1: serial@ef600400 {
233 + device_type = "serial";
234 + compatible = "ns16550";
235 + reg = <0xef600400 0x00000008>;
236 + virtual-reg = <0xef600400>;
237 + clock-frequency = <0>; /* Filled in by zImage */
238 + current-speed = <115200>;
239 + interrupt-parent = <&UIC0>;
240 + interrupts = <0x1 0x4>;
241 + };
242 +
243 + IIC: i2c@ef600500 {
244 + compatible = "ibm,iic-405ep", "ibm,iic";
245 + #address-cells = <1>;
246 + #size-cells = <0>;
247 + reg = <0xef600500 0x00000011>;
248 + interrupt-parent = <&UIC0>;
249 + interrupts = <0x2 0x4>;
250 +
251 + dtt@48 {
252 + compatible = "national,lm75";
253 + reg = <0x48>;
254 + };
255 +
256 + eeprom@50 {
257 + compatible = "at24,24c16";
258 + reg = <0x50>;
259 + };
260 + };
261 +
262 + GPIO0: gpio-controller@ef600700 {
263 + compatible = "ibm,ppc4xx-gpio";
264 + reg = <0xef600700 0x00000020>;
265 + #gpio-cells = <2>;
266 + gpio-controller;
267 + };
268 +
269 + EMAC0: ethernet@ef600800 {
270 + linux,network-index = <0x0>;
271 + device_type = "network";
272 + compatible = "ibm,emac-405ep", "ibm,emac";
273 + interrupt-parent = <&UIC0>;
274 + interrupts = <
275 + 0xf 0x4 /* Ethernet */
276 + 0x9 0x4 /* Ethernet Wake Up */>;
277 + local-mac-address = [000000000000]; /* Filled in by zImage */
278 + reg = <0xef600800 0x00000070>;
279 + mal-device = <&MAL>;
280 + mal-tx-channel = <0>;
281 + mal-rx-channel = <0>;
282 + cell-index = <0>;
283 + max-frame-size = <0x5dc>;
284 + rx-fifo-size = <0x1000>;
285 + tx-fifo-size = <0x800>;
286 + phy-mode = "mii";
287 + phy-map = <0x00000000>;
288 + };
289 +
290 + EMAC1: ethernet@ef600900 {
291 + linux,network-index = <0x1>;
292 + device_type = "network";
293 + compatible = "ibm,emac-405ep", "ibm,emac";
294 + interrupt-parent = <&UIC0>;
295 + interrupts = <
296 + 0x11 0x4 /* Ethernet */
297 + 0x09 0x4 /* Ethernet Wake Up */>;
298 + local-mac-address = [000000000000]; /* Filled in by zImage */
299 + reg = <0xef600900 0x00000070>;
300 + mal-device = <&MAL>;
301 + mal-tx-channel = <2>;
302 + mal-rx-channel = <1>;
303 + cell-index = <1>;
304 + max-frame-size = <0x5dc>;
305 + rx-fifo-size = <0x1000>;
306 + tx-fifo-size = <0x800>;
307 + mdio-device = <&EMAC0>;
308 + phy-mode = "mii";
309 + phy-map = <0x00000001>;
310 + };
311 +
312 + leds {
313 + compatible = "gpio-leds";
314 + user {
315 + label = "magicbox:red:user";
316 + gpios = <&GPIO0 2 1>;
317 + };
318 + };
319 + };
320 +
321 + EBC0: ebc {
322 + compatible = "ibm,ebc-405ep", "ibm,ebc";
323 + dcr-reg = <0x012 0x002>;
324 + #address-cells = <2>;
325 + #size-cells = <1>;
326 + /* The ranges property is supplied by the bootwrapper
327 + * and is based on the firmware's configuration of the
328 + * EBC bridge
329 + */
330 + clock-frequency = <0>; /* Filled in by zImage */
331 +
332 + cf_card@ff100000 {
333 + compatible = "magicbox-cf", "pata-magicbox-cf";
334 + reg = <0x00000000 0xff100000 0x00001000
335 + 0x00000000 0xff200000 0x00001000>;
336 + interrupt-parent = <&UIC0>;
337 + interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
338 + };
339 +
340 + nor_flash@ffc00000 {
341 + compatible = "cfi-flash";
342 + bank-width = <2>;
343 + reg = <0x00000000 0xffc00000 0x00400000>;
344 + #address-cells = <1>;
345 + #size-cells = <1>;
346 + partition@0 {
347 + label = "linux";
348 + reg = <0x0 0x120000>;
349 + };
350 + partition@120000 {
351 + label = "rootfs";
352 + reg = <0x120000 0x2a0000>;
353 + };
354 + partition@3c0000 {
355 + label = "u-boot";
356 + reg = <0x3c0000 0x30000>;
357 + read-only;
358 + };
359 + };
360 + };
361 +
362 + PCI0: pci@ec000000 {
363 + device_type = "pci";
364 + #interrupt-cells = <1>;
365 + #size-cells = <2>;
366 + #address-cells = <3>;
367 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
368 + primary;
369 + reg = <0xeec00000 0x00000008 /* Config space access */
370 + 0xeed80000 0x00000004 /* IACK */
371 + 0xeed80000 0x00000004 /* Special cycle */
372 + 0xef480000 0x00000040>; /* Internal registers */
373 +
374 + /* Outbound ranges, one memory and one IO,
375 + * later cannot be changed. Chip supports a second
376 + * IO range but we don't use it for now
377 + */
378 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
379 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
380 +
381 + /* Inbound 2GB range starting at 0 */
382 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
383 +
384 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
385 + interrupt-map = <
386 + /* IDSEL 1 */
387 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
388 +
389 + /* IDSEL 2 */
390 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
391 +
392 + /* IDSEL 3 */
393 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
394 +
395 + /* IDSEL 4 */
396 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
397 + >;
398 + };
399 + };
400 +
401 + chosen {
402 + linux,stdout-path = "/plb/opb/serial@ef600300";
403 + };
404 +};
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