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ralink: move ethernet driver to files/
[openwrt/staging/yousong.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * based on Ralink SDK3.3
16 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
17 */
18
19 #ifndef FE_ETH_H
20 #define FE_ETH_H
21
22 #include <linux/mii.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/phy.h>
27 #include <linux/ethtool.h>
28
29 enum fe_reg {
30 FE_REG_PDMA_GLO_CFG = 0,
31 FE_REG_PDMA_RST_CFG,
32 FE_REG_DLY_INT_CFG,
33 FE_REG_TX_BASE_PTR0,
34 FE_REG_TX_MAX_CNT0,
35 FE_REG_TX_CTX_IDX0,
36 FE_REG_RX_BASE_PTR0,
37 FE_REG_RX_MAX_CNT0,
38 FE_REG_RX_CALC_IDX0,
39 FE_REG_FE_INT_ENABLE,
40 FE_REG_FE_INT_STATUS,
41 FE_REG_FE_DMA_VID_BASE,
42 FE_REG_FE_COUNTER_BASE,
43 FE_REG_COUNT
44 };
45
46 #define FE_DRV_VERSION "0.1.0"
47
48 /* power of 2 to let NEXT_TX_DESP_IDX work */
49 #define NUM_DMA_DESC (1 << 7)
50 #define MAX_DMA_DESC 0xfff
51
52 #define FE_DELAY_EN_INT 0x80
53 #define FE_DELAY_MAX_INT 0x04
54 #define FE_DELAY_MAX_TOUT 0x04
55 #define FE_DELAY_TIME 20
56 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
57 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
58 #define FE_PSE_FQFC_CFG_INIT 0x80504000
59 #define FE_PSE_FQFC_CFG_256Q 0xff908000
60
61 /* interrupt bits */
62 #define FE_CNT_PPE_AF BIT(31)
63 #define FE_CNT_GDM_AF BIT(29)
64 #define FE_PSE_P2_FC BIT(26)
65 #define FE_PSE_BUF_DROP BIT(24)
66 #define FE_GDM_OTHER_DROP BIT(23)
67 #define FE_PSE_P1_FC BIT(22)
68 #define FE_PSE_P0_FC BIT(21)
69 #define FE_PSE_FQ_EMPTY BIT(20)
70 #define FE_GE1_STA_CHG BIT(18)
71 #define FE_TX_COHERENT BIT(17)
72 #define FE_RX_COHERENT BIT(16)
73 #define FE_TX_DONE_INT3 BIT(11)
74 #define FE_TX_DONE_INT2 BIT(10)
75 #define FE_TX_DONE_INT1 BIT(9)
76 #define FE_TX_DONE_INT0 BIT(8)
77 #define FE_RX_DONE_INT0 BIT(2)
78 #define FE_TX_DLY_INT BIT(1)
79 #define FE_RX_DLY_INT BIT(0)
80
81 #define RT5350_RX_DLY_INT BIT(30)
82 #define RT5350_TX_DLY_INT BIT(28)
83
84 /* registers */
85 #define FE_FE_OFFSET 0x0000
86 #define FE_GDMA_OFFSET 0x0020
87 #define FE_PSE_OFFSET 0x0040
88 #define FE_GDMA2_OFFSET 0x0060
89 #define FE_CDMA_OFFSET 0x0080
90 #define FE_DMA_VID0 0x00a8
91 #define FE_PDMA_OFFSET 0x0100
92 #define FE_PPE_OFFSET 0x0200
93 #define FE_CMTABLE_OFFSET 0x0400
94 #define FE_POLICYTABLE_OFFSET 0x1000
95
96 #define RT5350_PDMA_OFFSET 0x0800
97 #define RT5350_SDM_OFFSET 0x0c00
98
99 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
100 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
101 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
102 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
103 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
104 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
105 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
106 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
107
108 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
109 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
110 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
111 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
112 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
113
114 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
115 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
116 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
117 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
118 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
119
120 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
121 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
122 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
123 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
124
125 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
126 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
127
128 #define MT7620A_GDMA_OFFSET 0x0600
129 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
130 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
131 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
132 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
133 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
134
135 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
136 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
137 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
138 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
139 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
140 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
141 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
142 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
143 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
144 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
145 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
146 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
147 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
148 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
149 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
150 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
151 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
152 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
153 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
154 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
155 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
156 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
157 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
158 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
159 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
160 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
161 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
162 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
163 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
164 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
165
166 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
167 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
168 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
169 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
170 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
171 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
172 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
173 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
174 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
175 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
176 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
177 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
178 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
179 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
180 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
181 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
182 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
183 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
184 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
185 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
186 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
187 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
188 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
189 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
190 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
191 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
192 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
193 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
194
195 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
196 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
197 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
198 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
199 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
200 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
201 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
202 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
203 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
204 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
205
206 #define RT5350_SDM_ICS_EN BIT(16)
207 #define RT5350_SDM_TCS_EN BIT(17)
208 #define RT5350_SDM_UCS_EN BIT(18)
209
210
211 /* MDIO_CFG register bits */
212 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
213 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
214 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
215 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
216 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
217 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
218 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
219 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
220 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
221 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
222 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
223 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
224 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
225 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
226 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
227 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
228 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
229 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
230 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
231 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
232 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
233 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
234 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
235 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
236 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
237
238 /* uni-cast port */
239 #define FE_GDM1_JMB_LEN_MASK 0xf
240 #define FE_GDM1_JMB_LEN_SHIFT 28
241 #define FE_GDM1_ICS_EN BIT(22)
242 #define FE_GDM1_TCS_EN BIT(21)
243 #define FE_GDM1_UCS_EN BIT(20)
244 #define FE_GDM1_JMB_EN BIT(19)
245 #define FE_GDM1_STRPCRC BIT(16)
246 #define FE_GDM1_UFRC_P_CPU (0 << 12)
247 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
248 #define FE_GDM1_UFRC_P_PPE (6 << 12)
249
250 /* checksums */
251 #define FE_ICS_GEN_EN BIT(2)
252 #define FE_UCS_GEN_EN BIT(1)
253 #define FE_TCS_GEN_EN BIT(0)
254
255 /* dma ring */
256 #define FE_PST_DRX_IDX0 BIT(16)
257 #define FE_PST_DTX_IDX3 BIT(3)
258 #define FE_PST_DTX_IDX2 BIT(2)
259 #define FE_PST_DTX_IDX1 BIT(1)
260 #define FE_PST_DTX_IDX0 BIT(0)
261
262 #define FE_TX_WB_DDONE BIT(6)
263 #define FE_RX_DMA_BUSY BIT(3)
264 #define FE_TX_DMA_BUSY BIT(1)
265 #define FE_RX_DMA_EN BIT(2)
266 #define FE_TX_DMA_EN BIT(0)
267
268 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
269 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
270 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
271
272 #define FE_US_CYC_CNT_MASK 0xff
273 #define FE_US_CYC_CNT_SHIFT 0x8
274 #define FE_US_CYC_CNT_DIVISOR 1000000
275
276 #define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
277 #define RX_DMA_LSO BIT(30)
278 #define RX_DMA_DONE BIT(31)
279 #define RX_DMA_L4VALID BIT(30)
280
281 struct fe_rx_dma {
282 unsigned int rxd1;
283 unsigned int rxd2;
284 unsigned int rxd3;
285 unsigned int rxd4;
286 } __packed __aligned(4);
287
288 #define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
289 #define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
290 #define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
291 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
292 #define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
293 #define TX_DMA_LS1 BIT(14)
294 #define TX_DMA_LS0 BIT(30)
295 #define TX_DMA_DONE BIT(31)
296
297 #define TX_DMA_INS_VLAN BIT(7)
298 #define TX_DMA_INS_PPPOE BIT(12)
299 #define TX_DMA_QN(_x) ((_x) << 16)
300 #define TX_DMA_PN(_x) ((_x) << 24)
301 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
302 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
303 #define TX_DMA_UDF BIT(20)
304 #define TX_DMA_CHKSUM (0x7 << 29)
305 #define TX_DMA_TSO BIT(28)
306
307 /* frame engine counters */
308 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
309 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
310 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
311
312 /* phy device flags */
313 #define FE_PHY_FLAG_PORT BIT(0)
314 #define FE_PHY_FLAG_ATTACH BIT(1)
315
316 struct fe_tx_dma {
317 unsigned int txd1;
318 unsigned int txd2;
319 unsigned int txd3;
320 unsigned int txd4;
321 } __packed __aligned(4);
322
323 struct fe_priv;
324
325 struct fe_phy {
326 struct phy_device *phy[8];
327 struct device_node *phy_node[8];
328 const __be32 *phy_fixed[8];
329 int duplex[8];
330 int speed[8];
331 int tx_fc[8];
332 int rx_fc[8];
333 spinlock_t lock;
334
335 int (*connect)(struct fe_priv *priv);
336 void (*disconnect)(struct fe_priv *priv);
337 void (*start)(struct fe_priv *priv);
338 void (*stop)(struct fe_priv *priv);
339 };
340
341 struct fe_soc_data
342 {
343 unsigned char mac[6];
344 const u32 *reg_table;
345
346 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
347 void (*reset_fe)(void);
348 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
349 int (*fwd_config)(struct fe_priv *priv);
350 void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
351 void (*rx_dma)(struct fe_priv *priv, int idx, int len);
352 int (*switch_init)(struct fe_priv *priv);
353 int (*switch_config)(struct fe_priv *priv);
354 void (*port_init)(struct fe_priv *priv, struct device_node *port);
355 int (*has_carrier)(struct fe_priv *priv);
356 int (*mdio_init)(struct fe_priv *priv);
357 void (*mdio_cleanup)(struct fe_priv *priv);
358 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
359 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
360 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
361
362 void *swpriv;
363 u32 pdma_glo_cfg;
364 u32 rx_dly_int;
365 u32 tx_dly_int;
366 u32 checksum_bit;
367 u32 tx_udf_bit;
368 };
369
370 #define FE_FLAG_PADDING_64B BIT(0)
371 #define FE_FLAG_PADDING_BUG BIT(1)
372 #define FE_FLAG_JUMBO_FRAME BIT(2)
373
374 #define FE_STAT_REG_DECLARE \
375 _FE(tx_bytes) \
376 _FE(tx_packets) \
377 _FE(tx_skip) \
378 _FE(tx_collisions) \
379 _FE(rx_bytes) \
380 _FE(rx_packets) \
381 _FE(rx_overflow) \
382 _FE(rx_fcs_errors) \
383 _FE(rx_short_errors) \
384 _FE(rx_long_errors) \
385 _FE(rx_checksum_errors) \
386 _FE(rx_flow_control_packets)
387
388 struct fe_hw_stats
389 {
390 spinlock_t stats_lock;
391 struct u64_stats_sync syncp;
392 #define _FE(x) u64 x;
393 FE_STAT_REG_DECLARE
394 #undef _FE
395 };
396
397 struct fe_priv
398 {
399 spinlock_t page_lock;
400
401 struct fe_soc_data *soc;
402 struct net_device *netdev;
403 u32 msg_enable;
404 u32 flags;
405
406 struct device *device;
407 unsigned long sysclk;
408
409 u16 frag_size;
410 u16 rx_buf_size;
411 struct fe_rx_dma *rx_dma;
412 u8 **rx_data;
413 dma_addr_t rx_phys;
414 struct napi_struct rx_napi;
415
416 struct fe_tx_dma *tx_dma;
417 struct sk_buff **tx_skb;
418 dma_addr_t tx_phys;
419 unsigned int tx_free_idx;
420
421 struct fe_phy *phy;
422 struct mii_bus *mii_bus;
423 struct phy_device *phy_dev;
424 u32 phy_flags;
425
426 int link[8];
427
428 struct fe_hw_stats *hw_stats;
429 };
430
431 extern const struct of_device_id of_fe_match[];
432
433 void fe_w32(u32 val, unsigned reg);
434 u32 fe_r32(unsigned reg);
435
436 int fe_set_clock_cycle(struct fe_priv *priv);
437 void fe_csum_config(struct fe_priv *priv);
438 void fe_stats_update(struct fe_priv *priv);
439 void fe_fwd_config(struct fe_priv *priv);
440 void fe_reg_w32(u32 val, enum fe_reg reg);
441 u32 fe_reg_r32(enum fe_reg reg);
442
443 static inline void *priv_netdev(struct fe_priv *priv)
444 {
445 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
446 }
447
448 #endif /* FE_ETH_H */
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