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[openwrt/staging/yousong.git] / target / linux / ramips / patches-3.18 / 0012-MIPS-ralink-add-MT7621-support.patch
1 From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 10:57:40 +0100
4 Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/gic.h | 4 +
9 arch/mips/include/asm/mach-ralink/irq.h | 9 +
10 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
11 arch/mips/kernel/vmlinux.lds.S | 1 +
12 arch/mips/ralink/Kconfig | 18 ++
13 arch/mips/ralink/Makefile | 7 +-
14 arch/mips/ralink/Platform | 5 +
15 arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
16 arch/mips/ralink/malta-amon.c | 81 +++++++++
17 arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
18 10 files changed, 617 insertions(+), 1 deletion(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
20 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
21 create mode 100644 arch/mips/ralink/irq-gic.c
22 create mode 100644 arch/mips/ralink/malta-amon.c
23 create mode 100644 arch/mips/ralink/mt7621.c
24
25 --- /dev/null
26 +++ b/arch/mips/include/asm/mach-ralink/irq.h
27 @@ -0,0 +1,9 @@
28 +#ifndef __ASM_MACH_RALINK_IRQ_H
29 +#define __ASM_MACH_RALINK_IRQ_H
30 +
31 +#define GIC_NUM_INTRS 64
32 +#define NR_IRQS 256
33 +
34 +#include_next <irq.h>
35 +
36 +#endif
37 --- /dev/null
38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
39 @@ -0,0 +1,39 @@
40 +/*
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
44 + *
45 + * Parts of this file are based on Ralink's 2.6.21 BSP
46 + *
47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
50 + */
51 +
52 +#ifndef _MT7621_REGS_H_
53 +#define _MT7621_REGS_H_
54 +
55 +#define MT7621_SYSC_BASE 0x1E000000
56 +
57 +#define SYSC_REG_CHIP_NAME0 0x00
58 +#define SYSC_REG_CHIP_NAME1 0x04
59 +#define SYSC_REG_CHIP_REV 0x0c
60 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
61 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
62 +
63 +#define CHIP_REV_PKG_MASK 0x1
64 +#define CHIP_REV_PKG_SHIFT 16
65 +#define CHIP_REV_VER_MASK 0xf
66 +#define CHIP_REV_VER_SHIFT 8
67 +#define CHIP_REV_ECO_MASK 0xf
68 +
69 +#define MT7621_DRAM_BASE 0x0
70 +#define MT7621_DDR2_SIZE_MIN 32
71 +#define MT7621_DDR2_SIZE_MAX 256
72 +
73 +#define MT7621_CHIP_NAME0 0x3637544D
74 +#define MT7621_CHIP_NAME1 0x20203132
75 +
76 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
77 +
78 +#endif
79 --- a/arch/mips/kernel/vmlinux.lds.S
80 +++ b/arch/mips/kernel/vmlinux.lds.S
81 @@ -51,6 +51,7 @@ SECTIONS
82 /* read-only */
83 _text = .; /* Text and read-only data */
84 .text : {
85 + /*. = . + 0x8000; */
86 TEXT_TEXT
87 SCHED_TEXT
88 LOCK_TEXT
89 --- a/arch/mips/ralink/Kconfig
90 +++ b/arch/mips/ralink/Kconfig
91 @@ -7,6 +7,11 @@ config CLKEVT_RT3352
92 select CLKSRC_OF
93 select CLKSRC_MMIO
94
95 +config IRQ_INTC
96 + bool
97 + default y
98 + depends on !SOC_MT7621
99 +
100 choice
101 prompt "Ralink SoC selection"
102 default SOC_RT305X
103 @@ -28,6 +33,15 @@ choice
104 config SOC_MT7620
105 bool "MT7620"
106
107 + config SOC_MT7621
108 + bool "MT7621"
109 + select MIPS_CPU_SCACHE
110 + select SYS_SUPPORTS_MULTITHREADING
111 + select SYS_SUPPORTS_SMP
112 + select SYS_SUPPORTS_MIPS_CMP
113 + select IRQ_GIC
114 + select HW_HAS_PCI
115 +
116 endchoice
117
118 choice
119 @@ -59,6 +73,10 @@ choice
120 depends on SOC_MT7620
121 select BUILTIN_DTB
122
123 + config DTB_MT7621_EVAL
124 + bool "MT7621 eval kit"
125 + depends on SOC_MT7621
126 +
127 endchoice
128
129 endif
130 --- a/arch/mips/ralink/Makefile
131 +++ b/arch/mips/ralink/Makefile
132 @@ -6,16 +6,21 @@
133 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
134 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
135
136 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
137 +obj-y := prom.o of.o reset.o clk.o timer.o
138
139 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
140
141 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
142
143 +obj-$(CONFIG_IRQ_INTC) += irq.o
144 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
145 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
146 +
147 obj-$(CONFIG_SOC_RT288X) += rt288x.o
148 obj-$(CONFIG_SOC_RT305X) += rt305x.o
149 obj-$(CONFIG_SOC_RT3883) += rt3883.o
150 obj-$(CONFIG_SOC_MT7620) += mt7620.o
151 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
152
153 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
154
155 --- a/arch/mips/ralink/Platform
156 +++ b/arch/mips/ralink/Platform
157 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
158 #
159 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
160 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
161 +
162 +# Ralink MT7621
163 +#
164 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
165 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
166 --- /dev/null
167 +++ b/arch/mips/ralink/irq-gic.c
168 @@ -0,0 +1,271 @@
169 +#include <linux/init.h>
170 +#include <linux/sched.h>
171 +#include <linux/slab.h>
172 +#include <linux/interrupt.h>
173 +#include <linux/kernel_stat.h>
174 +#include <linux/hardirq.h>
175 +#include <linux/preempt.h>
176 +#include <linux/irqdomain.h>
177 +#include <linux/of_platform.h>
178 +#include <linux/of_address.h>
179 +#include <linux/of_irq.h>
180 +
181 +#include <asm/irq_cpu.h>
182 +#include <asm/mipsregs.h>
183 +
184 +#include <asm/irq.h>
185 +#include <asm/setup.h>
186 +
187 +#include <asm/gic.h>
188 +#include <asm/gcmpregs.h>
189 +
190 +#include <asm/mach-ralink/mt7621.h>
191 +
192 +unsigned long _gcmp_base;
193 +static int gic_resched_int_base = 56;
194 +static int gic_call_int_base = 60;
195 +static struct irq_chip *irq_gic;
196 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
197 +
198 +#if defined(CONFIG_MIPS_MT_SMP)
199 +static int gic_resched_int_base;
200 +static int gic_call_int_base;
201 +
202 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
203 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
204 +
205 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
206 +{
207 + scheduler_ipi();
208 +
209 + return IRQ_HANDLED;
210 +}
211 +
212 +static irqreturn_t
213 +ipi_call_interrupt(int irq, void *dev_id)
214 +{
215 + smp_call_function_interrupt();
216 +
217 + return IRQ_HANDLED;
218 +}
219 +
220 +static struct irqaction irq_resched = {
221 + .handler = ipi_resched_interrupt,
222 + .flags = IRQF_DISABLED|IRQF_PERCPU,
223 + .name = "ipi resched"
224 +};
225 +
226 +static struct irqaction irq_call = {
227 + .handler = ipi_call_interrupt,
228 + .flags = IRQF_DISABLED|IRQF_PERCPU,
229 + .name = "ipi call"
230 +};
231 +
232 +#endif
233 +
234 +static void __init
235 +gic_fill_map(void)
236 +{
237 + int i;
238 +
239 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
240 + gic_intr_map[i].cpunum = 0;
241 + gic_intr_map[i].pin = GIC_CPU_INT0;
242 + gic_intr_map[i].polarity = GIC_POL_POS;
243 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
244 + gic_intr_map[i].flags = GIC_FLAG_IPI;
245 + }
246 +
247 +#if defined(CONFIG_MIPS_MT_SMP)
248 + {
249 + int cpu;
250 +
251 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
252 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
253 +
254 + i = gic_resched_int_base;
255 +
256 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
257 + gic_intr_map[i + cpu].cpunum = cpu;
258 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
259 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
260 +
261 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
262 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
263 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
264 + }
265 + }
266 +#endif
267 +}
268 +
269 +void
270 +gic_irq_ack(struct irq_data *d)
271 +{
272 + int irq = (d->irq - gic_irq_base);
273 +
274 + GIC_CLR_INTR_MASK(irq);
275 +
276 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
277 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
278 +}
279 +
280 +void
281 +gic_finish_irq(struct irq_data *d)
282 +{
283 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
284 +}
285 +
286 +void __init
287 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
288 +{
289 + irq_gic = irq_controller;
290 +}
291 +
292 +static void
293 +gic_irqdispatch(void)
294 +{
295 + unsigned int irq = gic_get_int();
296 +
297 + if (likely(irq < GIC_NUM_INTRS))
298 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
299 + else {
300 + pr_debug("Spurious GIC Interrupt!\n");
301 + spurious_interrupt();
302 + }
303 +
304 +}
305 +
306 +static void
307 +vi_timer_irqdispatch(void)
308 +{
309 + do_IRQ(cp0_compare_irq);
310 +}
311 +
312 +#if defined(CONFIG_MIPS_MT_SMP)
313 +unsigned int
314 +plat_ipi_call_int_xlate(unsigned int cpu)
315 +{
316 + return GIC_CALL_INT(cpu);
317 +}
318 +
319 +unsigned int
320 +plat_ipi_resched_int_xlate(unsigned int cpu)
321 +{
322 + return GIC_RESCHED_INT(cpu);
323 +}
324 +#endif
325 +
326 +asmlinkage void
327 +plat_irq_dispatch(void)
328 +{
329 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
330 +
331 + if (unlikely(!pending)) {
332 + pr_err("Spurious CP0 Interrupt!\n");
333 + spurious_interrupt();
334 + } else {
335 + if (pending & CAUSEF_IP7)
336 + do_IRQ(cp0_compare_irq);
337 +
338 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
339 + gic_irqdispatch();
340 + }
341 +}
342 +
343 +unsigned int __cpuinit
344 +get_c0_compare_int(void)
345 +{
346 + return CP0_LEGACY_COMPARE_IRQ;
347 +}
348 +
349 +static int
350 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
351 +{
352 + irq_set_chip_and_handler(irq, irq_gic,
353 +#if defined(CONFIG_MIPS_MT_SMP)
354 + (hw >= gic_resched_int_base) ?
355 + handle_percpu_irq :
356 +#endif
357 + handle_level_irq);
358 +
359 + return 0;
360 +}
361 +
362 +static const struct irq_domain_ops irq_domain_ops = {
363 + .xlate = irq_domain_xlate_onecell,
364 + .map = gic_map,
365 +};
366 +
367 +static int __init
368 +of_gic_init(struct device_node *node,
369 + struct device_node *parent)
370 +{
371 + struct irq_domain *domain;
372 + struct resource gcmp = { 0 }, gic = { 0 };
373 + unsigned int gic_rev;
374 + int i;
375 +
376 + if (of_address_to_resource(node, 0, &gic))
377 + panic("Failed to get gic memory range");
378 + if (request_mem_region(gic.start, resource_size(&gic),
379 + gic.name) < 0)
380 + panic("Failed to request gic memory");
381 + if (of_address_to_resource(node, 2, &gcmp))
382 + panic("Failed to get gic memory range");
383 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
384 + gcmp.name) < 0)
385 + panic("Failed to request gcmp memory");
386 +
387 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
388 + if (!_gcmp_base)
389 + panic("Failed to remap gcmp memory\n");
390 +
391 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
392 + panic("Failed to find gcmp core\n");
393 +
394 + /* tell the gcmp where to find the gic */
395 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
396 + gic_present = 1;
397 + if (cpu_has_vint) {
398 + set_vi_handler(2, gic_irqdispatch);
399 + set_vi_handler(3, gic_irqdispatch);
400 + set_vi_handler(4, gic_irqdispatch);
401 + set_vi_handler(7, vi_timer_irqdispatch);
402 + }
403 +
404 + gic_fill_map();
405 +
406 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
407 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
408 +
409 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
410 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
411 +
412 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
413 + 0, &irq_domain_ops, NULL);
414 + if (!domain)
415 + panic("Failed to add irqdomain");
416 +
417 +#if defined(CONFIG_MIPS_MT_SMP)
418 + for (i = 0; i < nr_cpu_ids; i++) {
419 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
420 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
421 + }
422 +#endif
423 +
424 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
425 + STATUSF_IP2);
426 + return 0;
427 +}
428 +
429 +static struct of_device_id __initdata of_irq_ids[] = {
430 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
431 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
432 + {},
433 +};
434 +
435 +void __init
436 +arch_init_irq(void)
437 +{
438 + of_irq_init(of_irq_ids);
439 +}
440 --- /dev/null
441 +++ b/arch/mips/ralink/malta-amon.c
442 @@ -0,0 +1,81 @@
443 +/*
444 + * Copyright (C) 2007 MIPS Technologies, Inc.
445 + * All rights reserved.
446 +
447 + * This program is free software; you can distribute it and/or modify it
448 + * under the terms of the GNU General Public License (Version 2) as
449 + * published by the Free Software Foundation.
450 + *
451 + * This program is distributed in the hope it will be useful, but WITHOUT
452 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
453 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
454 + * for more details.
455 + *
456 + * You should have received a copy of the GNU General Public License along
457 + * with this program; if not, write to the Free Software Foundation, Inc.,
458 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
459 + *
460 + * Arbitrary Monitor interface
461 + */
462 +
463 +#include <linux/kernel.h>
464 +#include <linux/init.h>
465 +#include <linux/smp.h>
466 +
467 +#include <asm/addrspace.h>
468 +#include <asm/mips-boards/launch.h>
469 +#include <asm/mipsmtregs.h>
470 +
471 +int amon_cpu_avail(int cpu)
472 +{
473 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
474 +
475 + if (cpu < 0 || cpu >= NCPULAUNCH) {
476 + pr_debug("avail: cpu%d is out of range\n", cpu);
477 + return 0;
478 + }
479 +
480 + launch += cpu;
481 + if (!(launch->flags & LAUNCH_FREADY)) {
482 + pr_debug("avail: cpu%d is not ready\n", cpu);
483 + return 0;
484 + }
485 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
486 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
487 + return 0;
488 + }
489 +
490 + return 1;
491 +}
492 +
493 +void amon_cpu_start(int cpu,
494 + unsigned long pc, unsigned long sp,
495 + unsigned long gp, unsigned long a0)
496 +{
497 + volatile struct cpulaunch *launch =
498 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
499 +
500 + if (!amon_cpu_avail(cpu))
501 + return;
502 + if (cpu == smp_processor_id()) {
503 + pr_debug("launch: I am cpu%d!\n", cpu);
504 + return;
505 + }
506 + launch += cpu;
507 +
508 + pr_debug("launch: starting cpu%d\n", cpu);
509 +
510 + launch->pc = pc;
511 + launch->gp = gp;
512 + launch->sp = sp;
513 + launch->a0 = a0;
514 +
515 + smp_wmb(); /* Target must see parameters before go */
516 + launch->flags |= LAUNCH_FGO;
517 + smp_wmb(); /* Target must see go before we poll */
518 +
519 + while ((launch->flags & LAUNCH_FGONE) == 0)
520 + ;
521 + smp_rmb(); /* Target will be updating flags soon */
522 + pr_debug("launch: cpu%d gone!\n", cpu);
523 +}
524 --- /dev/null
525 +++ b/arch/mips/ralink/mt7621.c
526 @@ -0,0 +1,183 @@
527 +/*
528 + * This program is free software; you can redistribute it and/or modify it
529 + * under the terms of the GNU General Public License version 2 as published
530 + * by the Free Software Foundation.
531 + *
532 + * Parts of this file are based on Ralink's 2.6.21 BSP
533 + *
534 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
535 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
536 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
537 + */
538 +
539 +#include <linux/kernel.h>
540 +#include <linux/init.h>
541 +#include <linux/module.h>
542 +#include <asm/gcmpregs.h>
543 +
544 +#include <asm/mipsregs.h>
545 +#include <asm/smp-ops.h>
546 +#include <asm/mach-ralink/ralink_regs.h>
547 +#include <asm/mach-ralink/mt7621.h>
548 +
549 +#include <pinmux.h>
550 +
551 +#include "common.h"
552 +
553 +#define SYSC_REG_SYSCFG 0x10
554 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
555 +#define SYSC_REG_CUR_CLK_STS 0x44
556 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
557 +
558 +#define MT7621_GPIO_MODE_UART1 1
559 +#define MT7621_GPIO_MODE_I2C 2
560 +#define MT7621_GPIO_MODE_UART2 3
561 +#define MT7621_GPIO_MODE_UART3 5
562 +#define MT7621_GPIO_MODE_JTAG 7
563 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
564 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
565 +#define MT7621_GPIO_MODE_WDT_GPIO 1
566 +#define MT7621_GPIO_MODE_PCIE_RST 0
567 +#define MT7621_GPIO_MODE_PCIE_REF 2
568 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
569 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
570 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
571 +#define MT7621_GPIO_MODE_MDIO 12
572 +#define MT7621_GPIO_MODE_RGMII1 14
573 +#define MT7621_GPIO_MODE_RGMII2 15
574 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
575 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
576 +#define MT7621_GPIO_MODE_SPI_GPIO 1
577 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
578 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
579 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
580 +
581 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
582 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
583 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
584 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
585 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
586 +static struct rt2880_pmx_func wdt_grp[] = {
587 + FUNC("wdt rst", 0, 18, 1),
588 + FUNC("wdt refclk", 2, 18, 1),
589 +};
590 +static struct rt2880_pmx_func pcie_rst_grp[] = {
591 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
592 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
593 +};
594 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
595 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
596 +static struct rt2880_pmx_func spi_grp[] = {
597 + FUNC("spi", 0, 34, 7),
598 + FUNC("nand", 2, 34, 8),
599 +};
600 +static struct rt2880_pmx_func sdhci_grp[] = {
601 + FUNC("sdhci", 0, 41, 8),
602 + FUNC("nand", 2, 41, 8),
603 +};
604 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
605 +
606 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
607 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
608 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
609 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
610 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
611 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
612 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
613 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
614 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
615 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
616 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
617 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
618 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
619 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
620 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
621 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
622 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
623 + { 0 }
624 +};
625 +
626 +void __init ralink_clk_init(void)
627 +{
628 + int cpu_fdiv = 0;
629 + int cpu_ffrac = 0;
630 + int fbdiv = 0;
631 + u32 clk_sts, syscfg;
632 + u8 clk_sel = 0, xtal_mode;
633 + u32 cpu_clk;
634 +
635 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
636 + clk_sel = 1;
637 +
638 + switch (clk_sel) {
639 + case 0:
640 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
641 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
642 + cpu_ffrac = (clk_sts & 0x1F);
643 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
644 + break;
645 +
646 + case 1:
647 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
648 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
649 + xtal_mode = (syscfg >> 6) & 0x7;
650 + if(xtal_mode >= 6) { //25Mhz Xtal
651 + cpu_clk = 25 * fbdiv * 1000 * 1000;
652 + } else if(xtal_mode >=3) { //40Mhz Xtal
653 + cpu_clk = 40 * fbdiv * 1000 * 1000;
654 + } else { // 20Mhz Xtal
655 + cpu_clk = 20 * fbdiv * 1000 * 1000;
656 + }
657 + break;
658 + }
659 + cpu_clk = 880000000;
660 + ralink_clk_add("cpu", cpu_clk);
661 + ralink_clk_add("1e000b00.spi", 50000000);
662 + ralink_clk_add("1e000c00.uartlite", 50000000);
663 + ralink_clk_add("1e000d00.uart", 50000000);
664 +}
665 +
666 +void __init ralink_of_remap(void)
667 +{
668 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
669 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
670 +
671 + if (!rt_sysc_membase || !rt_memc_membase)
672 + panic("Failed to remap core resources");
673 +}
674 +
675 +void prom_soc_init(struct ralink_soc_info *soc_info)
676 +{
677 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
678 + unsigned char *name = NULL;
679 + u32 n0;
680 + u32 n1;
681 + u32 rev;
682 +
683 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
684 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
685 +
686 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
687 + name = "MT7621";
688 + soc_info->compatible = "mtk,mt7621-soc";
689 + } else {
690 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
691 + }
692 +
693 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
694 +
695 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
696 + "Mediatek %s ver:%u eco:%u",
697 + name,
698 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
699 + (rev & CHIP_REV_ECO_MASK));
700 +
701 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
702 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
703 + soc_info->mem_base = MT7621_DRAM_BASE;
704 +
705 + rt2880_pinmux_data = mt7621_pinmux_data;
706 +
707 + if (register_cmp_smp_ops())
708 + panic("failed to register_vsmp_smp_ops()");
709 +}
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