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kernel: update linux 3.8 to 3.8.6
[openwrt/staging/yousong.git] / target / linux / ramips / patches-3.8 / 0111-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch
1 From 8831277e0167cdcf3dc3ecc5d5a67d4fd9d0ed77 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 17:49:02 +0100
4 Subject: [PATCH 111/121] MIPS: ralink: adds support for MT7620 SoC family
5
6 Add support code for mt7620 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 ---
12 arch/mips/include/asm/mach-ralink/mt7620.h | 66 +++++++++
13 arch/mips/ralink/Kconfig | 3 +
14 arch/mips/ralink/Makefile | 1 +
15 arch/mips/ralink/Platform | 5 +
16 arch/mips/ralink/mt7620.c | 215 ++++++++++++++++++++++++++++
17 5 files changed, 290 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
19 create mode 100644 arch/mips/ralink/mt7620.c
20
21 --- /dev/null
22 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
23 @@ -0,0 +1,66 @@
24 +/*
25 + * This program is free software; you can redistribute it and/or modify it
26 + * under the terms of the GNU General Public License version 2 as published
27 + * by the Free Software Foundation.
28 + *
29 + * Parts of this file are based on Ralink's 2.6.21 BSP
30 + *
31 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
32 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
33 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
34 + */
35 +
36 +#ifndef _MT7620_REGS_H_
37 +#define _MT7620_REGS_H_
38 +
39 +#define MT7620_SYSC_BASE 0x10000000
40 +
41 +#define SYSC_REG_CHIP_NAME0 0x00
42 +#define SYSC_REG_CHIP_NAME1 0x04
43 +#define SYSC_REG_CHIP_REV 0x0c
44 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
45 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
46 +#define SYSC_REG_CPLL_CONFIG0 0x54
47 +#define SYSC_REG_CPLL_CONFIG1 0x58
48 +
49 +#define MT7620N_CHIP_NAME0 0x33365452
50 +#define MT7620N_CHIP_NAME1 0x20203235
51 +
52 +#define MT7620A_CHIP_NAME0 0x3637544d
53 +#define MT7620A_CHIP_NAME1 0x20203032
54 +
55 +#define CHIP_REV_PKG_MASK 0x1
56 +#define CHIP_REV_PKG_SHIFT 16
57 +#define CHIP_REV_VER_MASK 0xf
58 +#define CHIP_REV_VER_SHIFT 8
59 +#define CHIP_REV_ECO_MASK 0xf
60 +
61 +#define MT7620_CPLL_SW_CONFIG_SHIFT 31
62 +#define MT7620_CPLL_SW_CONFIG_MASK 0x1
63 +#define MT7620_CPLL_CPU_CLK_SHIFT 24
64 +#define MT7620_CPLL_CPU_CLK_MASK 0x1
65 +
66 +#define MT7620_GPIO_MODE_I2C BIT(0)
67 +#define MT7620_GPIO_MODE_UART0_SHIFT 2
68 +#define MT7620_GPIO_MODE_UART0_MASK 0x7
69 +#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
70 +#define MT7620_GPIO_MODE_UARTF 0x0
71 +#define MT7620_GPIO_MODE_PCM_UARTF 0x1
72 +#define MT7620_GPIO_MODE_PCM_I2S 0x2
73 +#define MT7620_GPIO_MODE_I2S_UARTF 0x3
74 +#define MT7620_GPIO_MODE_PCM_GPIO 0x4
75 +#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
76 +#define MT7620_GPIO_MODE_GPIO_I2S 0x6
77 +#define MT7620_GPIO_MODE_GPIO 0x7
78 +#define MT7620_GPIO_MODE_UART1 BIT(5)
79 +#define MT7620_GPIO_MODE_MDIO BIT(8)
80 +#define MT7620_GPIO_MODE_RGMII1 BIT(9)
81 +#define MT7620_GPIO_MODE_RGMII2 BIT(10)
82 +#define MT7620_GPIO_MODE_SPI BIT(11)
83 +#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
84 +#define MT7620_GPIO_MODE_WLED BIT(13)
85 +#define MT7620_GPIO_MODE_JTAG BIT(15)
86 +#define MT7620_GPIO_MODE_EPHY BIT(15)
87 +#define MT7620_GPIO_MODE_WDT BIT(22)
88 +
89 +#endif
90 --- a/arch/mips/ralink/Kconfig
91 +++ b/arch/mips/ralink/Kconfig
92 @@ -20,6 +20,9 @@ choice
93 select USB_ARCH_HAS_OHCI
94 select USB_ARCH_HAS_EHCI
95
96 + config SOC_MT7620
97 + bool "MT7620"
98 +
99 endchoice
100
101 choice
102 --- a/arch/mips/ralink/Makefile
103 +++ b/arch/mips/ralink/Makefile
104 @@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
105 obj-$(CONFIG_SOC_RT288X) += rt288x.o
106 obj-$(CONFIG_SOC_RT305X) += rt305x.o
107 obj-$(CONFIG_SOC_RT3883) += rt3883.o
108 +obj-$(CONFIG_SOC_MT7620) += mt7620.o
109
110 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
111
112 --- a/arch/mips/ralink/Platform
113 +++ b/arch/mips/ralink/Platform
114 @@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff8
115 # Ralink RT3883
116 #
117 load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
118 +
119 +#
120 +# Ralink MT7620
121 +#
122 +load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
123 --- /dev/null
124 +++ b/arch/mips/ralink/mt7620.c
125 @@ -0,0 +1,215 @@
126 +/*
127 + * This program is free software; you can redistribute it and/or modify it
128 + * under the terms of the GNU General Public License version 2 as published
129 + * by the Free Software Foundation.
130 + *
131 + * Parts of this file are based on Ralink's 2.6.21 BSP
132 + *
133 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
134 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
135 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
136 + */
137 +
138 +#include <linux/kernel.h>
139 +#include <linux/init.h>
140 +#include <linux/module.h>
141 +
142 +#include <asm/mipsregs.h>
143 +#include <asm/mach-ralink/ralink_regs.h>
144 +#include <asm/mach-ralink/mt7620.h>
145 +
146 +#include "common.h"
147 +
148 +
149 +struct ralink_pinmux_grp mode_mux[] = {
150 + {
151 + .name = "i2c",
152 + .mask = MT7620_GPIO_MODE_I2C,
153 + .gpio_first = 1,
154 + .gpio_last = 2,
155 + }, {
156 + .name = "spi",
157 + .mask = MT7620_GPIO_MODE_SPI,
158 + .gpio_first = 3,
159 + .gpio_last = 6,
160 + }, {
161 + .name = "uartlite",
162 + .mask = MT7620_GPIO_MODE_UART1,
163 + .gpio_first = 15,
164 + .gpio_last = 16,
165 + }, {
166 + .name = "wdt",
167 + .mask = MT7620_GPIO_MODE_WDT,
168 + .gpio_first = 17,
169 + .gpio_last = 17,
170 + }, {
171 + .name = "mdio",
172 + .mask = MT7620_GPIO_MODE_MDIO,
173 + .gpio_first = 22,
174 + .gpio_last = 23,
175 + }, {
176 + .name = "rgmii1",
177 + .mask = MT7620_GPIO_MODE_RGMII1,
178 + .gpio_first = 24,
179 + .gpio_last = 35,
180 + }, {
181 + .name = "spi refclk",
182 + .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
183 + .gpio_first = 37,
184 + .gpio_last = 39,
185 + }, {
186 + .name = "jtag",
187 + .mask = MT7620_GPIO_MODE_JTAG,
188 + .gpio_first = 40,
189 + .gpio_last = 44,
190 + }, {
191 + /* shared lines with jtag */
192 + .name = "ephy",
193 + .mask = MT7620_GPIO_MODE_EPHY,
194 + .gpio_first = 40,
195 + .gpio_last = 44,
196 + }, {
197 + .name = "nand",
198 + .mask = MT7620_GPIO_MODE_JTAG,
199 + .gpio_first = 45,
200 + .gpio_last = 59,
201 + }, {
202 + .name = "rgmii2",
203 + .mask = MT7620_GPIO_MODE_RGMII2,
204 + .gpio_first = 60,
205 + .gpio_last = 71,
206 + }, {
207 + .name = "wled",
208 + .mask = MT7620_GPIO_MODE_WLED,
209 + .gpio_first = 72,
210 + .gpio_last = 72,
211 + }, {0}
212 +};
213 +
214 +
215 +struct ralink_pinmux_grp uart_mux[] = {
216 + {
217 + .name = "uartf",
218 + .mask = MT7620_GPIO_MODE_UARTF,
219 + .gpio_first = 7,
220 + .gpio_last = 14,
221 + }, {
222 + .name = "pcm uartf",
223 + .mask = MT7620_GPIO_MODE_PCM_UARTF,
224 + .gpio_first = 7,
225 + .gpio_last = 14,
226 + }, {
227 + .name = "pcm i2s",
228 + .mask = MT7620_GPIO_MODE_PCM_I2S,
229 + .gpio_first = 7,
230 + .gpio_last = 14,
231 + }, {
232 + .name = "i2s uartf",
233 + .mask = MT7620_GPIO_MODE_I2S_UARTF,
234 + .gpio_first = 7,
235 + .gpio_last = 14,
236 + }, {
237 + .name = "pcm gpio",
238 + .mask = MT7620_GPIO_MODE_PCM_GPIO,
239 + .gpio_first = 11,
240 + .gpio_last = 14,
241 + }, {
242 + .name = "gpio uartf",
243 + .mask = MT7620_GPIO_MODE_GPIO_UARTF,
244 + .gpio_first = 7,
245 + .gpio_last = 10,
246 + }, {
247 + .name = "gpio i2s",
248 + .mask = MT7620_GPIO_MODE_GPIO_I2S,
249 + .gpio_first = 7,
250 + .gpio_last = 10,
251 + }, {
252 + .name = "gpio",
253 + .mask = MT7620_GPIO_MODE_GPIO,
254 + }, {0}
255 +};
256 +/*
257 +void rt305x_wdt_reset(void)
258 +{
259 + u32 t;
260 +
261 + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
262 + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
263 + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
264 + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
265 +}
266 +*/
267 +struct ralink_pinmux rt_pinmux = {
268 + .mode = mode_mux,
269 + .uart = uart_mux,
270 + .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
271 +// .wdt_reset = rt305x_wdt_reset,
272 +};
273 +
274 +void __init ralink_clk_init(void)
275 +{
276 + unsigned long cpu_rate, sys_rate;
277 + u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
278 + u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
279 +
280 + c0 = (c0 >> MT7620_CPLL_SW_CONFIG_SHIFT) &
281 + MT7620_CPLL_SW_CONFIG_MASK;
282 + c1 = (c1 >> MT7620_CPLL_CPU_CLK_SHIFT) &
283 + MT7620_CPLL_CPU_CLK_MASK;
284 + if (c1 == 0x01) {
285 + cpu_rate = 480000000;
286 + } else {
287 + if (c1 == 0x0) {
288 + cpu_rate = 600000000;
289 + } else {
290 + /* TODO calculate custom clock from pll settings */
291 + BUG();
292 + }
293 + }
294 + /* FIXME SDR - 4, DDR - 3 */
295 + sys_rate = cpu_rate / 4;
296 +
297 + ralink_clk_add("cpu", cpu_rate);
298 + ralink_clk_add("10000100.timer", 40000000);
299 + ralink_clk_add("10000500.uart", 40000000);
300 + ralink_clk_add("10000c00.uartlite", 40000000);
301 +}
302 +
303 +void __init ralink_of_remap(void)
304 +{
305 + rt_sysc_membase = plat_of_remap_node("ralink,mt7620-sysc");
306 + rt_memc_membase = plat_of_remap_node("ralink,mt7620-memc");
307 +
308 + if (!rt_sysc_membase || !rt_memc_membase)
309 + panic("Failed to remap core resources");
310 +}
311 +
312 +void prom_soc_init(struct ralink_soc_info *soc_info)
313 +{
314 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
315 + unsigned char *name = NULL;
316 + u32 n0;
317 + u32 n1;
318 + u32 rev;
319 +
320 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
321 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
322 +
323 + if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
324 + name = "MT7620N";
325 + soc_info->compatible = "ralink,mt7620n-soc";
326 + } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
327 + name = "MT7620A";
328 + soc_info->compatible = "ralink,mt7620a-soc";
329 + } else {
330 + printk("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
331 + }
332 +
333 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
334 +
335 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
336 + "Ralink %s ver:%u eco:%u",
337 + name,
338 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
339 + (rev & CHIP_REV_ECO_MASK));
340 +}
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