projects / openwrt / staging / yousong.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ramips: sync kernel patches with the mips-next tree
[openwrt/staging/yousong.git] / target / linux / ramips / patches-3.8 / 0112-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch
1 From 5eb4dfe5072595e0706de3364f2da45378dbaca6 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:39:02 +0100
4 Subject: [PATCH 112/137] MIPS: ralink: adds support for RT3883 SoC family
5
6 Add support code for rt3883 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/5185/
13 ---
14 arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
15 arch/mips/ralink/Kconfig | 5 +
16 arch/mips/ralink/Makefile | 1 +
17 arch/mips/ralink/Platform | 5 +
18 arch/mips/ralink/rt3883.c | 242 +++++++++++++++++++++++++++
19 5 files changed, 500 insertions(+)
20 create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
21 create mode 100644 arch/mips/ralink/rt3883.c
22
23 --- /dev/null
24 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
25 @@ -0,0 +1,247 @@
26 +/*
27 + * Ralink RT3662/RT3883 SoC register definitions
28 + *
29 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
30 + *
31 + * This program is free software; you can redistribute it and/or modify it
32 + * under the terms of the GNU General Public License version 2 as published
33 + * by the Free Software Foundation.
34 + */
35 +
36 +#ifndef _RT3883_REGS_H_
37 +#define _RT3883_REGS_H_
38 +
39 +#include <linux/bitops.h>
40 +
41 +#define RT3883_SDRAM_BASE 0x00000000
42 +#define RT3883_SYSC_BASE 0x10000000
43 +#define RT3883_TIMER_BASE 0x10000100
44 +#define RT3883_INTC_BASE 0x10000200
45 +#define RT3883_MEMC_BASE 0x10000300
46 +#define RT3883_UART0_BASE 0x10000500
47 +#define RT3883_PIO_BASE 0x10000600
48 +#define RT3883_FSCC_BASE 0x10000700
49 +#define RT3883_NANDC_BASE 0x10000810
50 +#define RT3883_I2C_BASE 0x10000900
51 +#define RT3883_I2S_BASE 0x10000a00
52 +#define RT3883_SPI_BASE 0x10000b00
53 +#define RT3883_UART1_BASE 0x10000c00
54 +#define RT3883_PCM_BASE 0x10002000
55 +#define RT3883_GDMA_BASE 0x10002800
56 +#define RT3883_CODEC1_BASE 0x10003000
57 +#define RT3883_CODEC2_BASE 0x10003800
58 +#define RT3883_FE_BASE 0x10100000
59 +#define RT3883_ROM_BASE 0x10118000
60 +#define RT3883_USBDEV_BASE 0x10112000
61 +#define RT3883_PCI_BASE 0x10140000
62 +#define RT3883_WLAN_BASE 0x10180000
63 +#define RT3883_USBHOST_BASE 0x101c0000
64 +#define RT3883_BOOT_BASE 0x1c000000
65 +#define RT3883_SRAM_BASE 0x1e000000
66 +#define RT3883_PCIMEM_BASE 0x20000000
67 +
68 +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
69 +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
70 +
71 +#define RT3883_SYSC_SIZE 0x100
72 +#define RT3883_TIMER_SIZE 0x100
73 +#define RT3883_INTC_SIZE 0x100
74 +#define RT3883_MEMC_SIZE 0x100
75 +#define RT3883_UART0_SIZE 0x100
76 +#define RT3883_UART1_SIZE 0x100
77 +#define RT3883_PIO_SIZE 0x100
78 +#define RT3883_FSCC_SIZE 0x100
79 +#define RT3883_NANDC_SIZE 0x0f0
80 +#define RT3883_I2C_SIZE 0x100
81 +#define RT3883_I2S_SIZE 0x100
82 +#define RT3883_SPI_SIZE 0x100
83 +#define RT3883_PCM_SIZE 0x800
84 +#define RT3883_GDMA_SIZE 0x800
85 +#define RT3883_CODEC1_SIZE 0x800
86 +#define RT3883_CODEC2_SIZE 0x800
87 +#define RT3883_FE_SIZE 0x10000
88 +#define RT3883_ROM_SIZE 0x4000
89 +#define RT3883_USBDEV_SIZE 0x4000
90 +#define RT3883_PCI_SIZE 0x40000
91 +#define RT3883_WLAN_SIZE 0x40000
92 +#define RT3883_USBHOST_SIZE 0x40000
93 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
94 +#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
95 +
96 +/* SYSC registers */
97 +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
98 +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
99 +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
100 +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
101 +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
102 +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
103 +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
104 +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
105 +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
106 +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
107 +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
108 +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
109 +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
110 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
111 +#define RT3883_SYSC_REG_PMU 0x88
112 +#define RT3883_SYSC_REG_PMU1 0x8c
113 +
114 +#define RT3883_CHIP_NAME0 0x38335452
115 +#define RT3883_CHIP_NAME1 0x20203338
116 +
117 +#define RT3883_REVID_VER_ID_MASK 0x0f
118 +#define RT3883_REVID_VER_ID_SHIFT 8
119 +#define RT3883_REVID_ECO_ID_MASK 0x0f
120 +
121 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
122 +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
123 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
124 +#define RT3883_SYSCFG0_CPUCLK_250 0x0
125 +#define RT3883_SYSCFG0_CPUCLK_384 0x1
126 +#define RT3883_SYSCFG0_CPUCLK_480 0x2
127 +#define RT3883_SYSCFG0_CPUCLK_500 0x3
128 +
129 +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
130 +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
131 +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
132 +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
133 +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
134 +
135 +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
136 +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
137 +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
138 +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
139 +
140 +#define RT3883_GPIO_MODE_I2C BIT(0)
141 +#define RT3883_GPIO_MODE_SPI BIT(1)
142 +#define RT3883_GPIO_MODE_UART0_SHIFT 2
143 +#define RT3883_GPIO_MODE_UART0_MASK 0x7
144 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
145 +#define RT3883_GPIO_MODE_UARTF 0x0
146 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1
147 +#define RT3883_GPIO_MODE_PCM_I2S 0x2
148 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3
149 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4
150 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
151 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6
152 +#define RT3883_GPIO_MODE_GPIO 0x7
153 +#define RT3883_GPIO_MODE_UART1 BIT(5)
154 +#define RT3883_GPIO_MODE_JTAG BIT(6)
155 +#define RT3883_GPIO_MODE_MDIO BIT(7)
156 +#define RT3883_GPIO_MODE_GE1 BIT(9)
157 +#define RT3883_GPIO_MODE_GE2 BIT(10)
158 +#define RT3883_GPIO_MODE_PCI_SHIFT 11
159 +#define RT3883_GPIO_MODE_PCI_MASK 0x7
160 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
161 +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
162 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
163 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
164 +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
165 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
166 +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
167 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
168 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
169 +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
170 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
171 +
172 +#define RT3883_GPIO_I2C_SD 1
173 +#define RT3883_GPIO_I2C_SCLK 2
174 +#define RT3883_GPIO_SPI_CS0 3
175 +#define RT3883_GPIO_SPI_CLK 4
176 +#define RT3883_GPIO_SPI_MOSI 5
177 +#define RT3883_GPIO_SPI_MISO 6
178 +#define RT3883_GPIO_7 7
179 +#define RT3883_GPIO_10 10
180 +#define RT3883_GPIO_14 14
181 +#define RT3883_GPIO_UART1_TXD 15
182 +#define RT3883_GPIO_UART1_RXD 16
183 +#define RT3883_GPIO_JTAG_TDO 17
184 +#define RT3883_GPIO_JTAG_TDI 18
185 +#define RT3883_GPIO_JTAG_TMS 19
186 +#define RT3883_GPIO_JTAG_TCLK 20
187 +#define RT3883_GPIO_JTAG_TRST_N 21
188 +#define RT3883_GPIO_MDIO_MDC 22
189 +#define RT3883_GPIO_MDIO_MDIO 23
190 +#define RT3883_GPIO_LNA_PE_A0 32
191 +#define RT3883_GPIO_LNA_PE_A1 33
192 +#define RT3883_GPIO_LNA_PE_A2 34
193 +#define RT3883_GPIO_LNA_PE_G0 35
194 +#define RT3883_GPIO_LNA_PE_G1 36
195 +#define RT3883_GPIO_LNA_PE_G2 37
196 +#define RT3883_GPIO_PCI_AD0 40
197 +#define RT3883_GPIO_PCI_AD31 71
198 +#define RT3883_GPIO_GE2_TXD0 72
199 +#define RT3883_GPIO_GE2_TXD1 73
200 +#define RT3883_GPIO_GE2_TXD2 74
201 +#define RT3883_GPIO_GE2_TXD3 75
202 +#define RT3883_GPIO_GE2_TXEN 76
203 +#define RT3883_GPIO_GE2_TXCLK 77
204 +#define RT3883_GPIO_GE2_RXD0 78
205 +#define RT3883_GPIO_GE2_RXD1 79
206 +#define RT3883_GPIO_GE2_RXD2 80
207 +#define RT3883_GPIO_GE2_RXD3 81
208 +#define RT3883_GPIO_GE2_RXDV 82
209 +#define RT3883_GPIO_GE2_RXCLK 83
210 +#define RT3883_GPIO_GE1_TXD0 84
211 +#define RT3883_GPIO_GE1_TXD1 85
212 +#define RT3883_GPIO_GE1_TXD2 86
213 +#define RT3883_GPIO_GE1_TXD3 87
214 +#define RT3883_GPIO_GE1_TXEN 88
215 +#define RT3883_GPIO_GE1_TXCLK 89
216 +#define RT3883_GPIO_GE1_RXD0 90
217 +#define RT3883_GPIO_GE1_RXD1 91
218 +#define RT3883_GPIO_GE1_RXD2 92
219 +#define RT3883_GPIO_GE1_RXD3 93
220 +#define RT3883_GPIO_GE1_RXDV 94
221 +#define RT3883_GPIO_GE1_RXCLK 95
222 +
223 +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
224 +#define RT3883_RSTCTRL_FLASH BIT(26)
225 +#define RT3883_RSTCTRL_UDEV BIT(25)
226 +#define RT3883_RSTCTRL_PCI BIT(24)
227 +#define RT3883_RSTCTRL_PCIE BIT(23)
228 +#define RT3883_RSTCTRL_UHST BIT(22)
229 +#define RT3883_RSTCTRL_FE BIT(21)
230 +#define RT3883_RSTCTRL_WLAN BIT(20)
231 +#define RT3883_RSTCTRL_UART1 BIT(29)
232 +#define RT3883_RSTCTRL_SPI BIT(18)
233 +#define RT3883_RSTCTRL_I2S BIT(17)
234 +#define RT3883_RSTCTRL_I2C BIT(16)
235 +#define RT3883_RSTCTRL_NAND BIT(15)
236 +#define RT3883_RSTCTRL_DMA BIT(14)
237 +#define RT3883_RSTCTRL_PIO BIT(13)
238 +#define RT3883_RSTCTRL_UART BIT(12)
239 +#define RT3883_RSTCTRL_PCM BIT(11)
240 +#define RT3883_RSTCTRL_MC BIT(10)
241 +#define RT3883_RSTCTRL_INTC BIT(9)
242 +#define RT3883_RSTCTRL_TIMER BIT(8)
243 +#define RT3883_RSTCTRL_SYS BIT(0)
244 +
245 +#define RT3883_INTC_INT_SYSCTL BIT(0)
246 +#define RT3883_INTC_INT_TIMER0 BIT(1)
247 +#define RT3883_INTC_INT_TIMER1 BIT(2)
248 +#define RT3883_INTC_INT_IA BIT(3)
249 +#define RT3883_INTC_INT_PCM BIT(4)
250 +#define RT3883_INTC_INT_UART0 BIT(5)
251 +#define RT3883_INTC_INT_PIO BIT(6)
252 +#define RT3883_INTC_INT_DMA BIT(7)
253 +#define RT3883_INTC_INT_NAND BIT(8)
254 +#define RT3883_INTC_INT_PERFC BIT(9)
255 +#define RT3883_INTC_INT_I2S BIT(10)
256 +#define RT3883_INTC_INT_UART1 BIT(12)
257 +#define RT3883_INTC_INT_UHST BIT(18)
258 +#define RT3883_INTC_INT_UDEV BIT(19)
259 +
260 +/* FLASH/SRAM/Codec Controller registers */
261 +#define RT3883_FSCC_REG_FLASH_CFG0 0x00
262 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04
263 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40
264 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44
265 +
266 +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
267 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
268 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
269 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
270 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
271 +
272 +#endif /* _RT3883_REGS_H_ */
273 --- a/arch/mips/ralink/Kconfig
274 +++ b/arch/mips/ralink/Kconfig
275 @@ -15,6 +15,11 @@ choice
276 select USB_ARCH_HAS_OHCI
277 select USB_ARCH_HAS_EHCI
278
279 + config SOC_RT3883
280 + bool "RT3883"
281 + select USB_ARCH_HAS_OHCI
282 + select USB_ARCH_HAS_EHCI
283 +
284 endchoice
285
286 choice
287 --- a/arch/mips/ralink/Makefile
288 +++ b/arch/mips/ralink/Makefile
289 @@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
290
291 obj-$(CONFIG_SOC_RT288X) += rt288x.o
292 obj-$(CONFIG_SOC_RT305X) += rt305x.o
293 +obj-$(CONFIG_SOC_RT3883) += rt3883.o
294
295 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
296
297 --- a/arch/mips/ralink/Platform
298 +++ b/arch/mips/ralink/Platform
299 @@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff8
300 # Ralink RT305x
301 #
302 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
303 +
304 +#
305 +# Ralink RT3883
306 +#
307 +load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
308 --- /dev/null
309 +++ b/arch/mips/ralink/rt3883.c
310 @@ -0,0 +1,242 @@
311 +/*
312 + * This program is free software; you can redistribute it and/or modify it
313 + * under the terms of the GNU General Public License version 2 as published
314 + * by the Free Software Foundation.
315 + *
316 + * Parts of this file are based on Ralink's 2.6.21 BSP
317 + *
318 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
319 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
320 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
321 + */
322 +
323 +#include <linux/kernel.h>
324 +#include <linux/init.h>
325 +#include <linux/module.h>
326 +
327 +#include <asm/mipsregs.h>
328 +#include <asm/mach-ralink/ralink_regs.h>
329 +#include <asm/mach-ralink/rt3883.h>
330 +
331 +#include "common.h"
332 +
333 +static struct ralink_pinmux_grp mode_mux[] = {
334 + {
335 + .name = "i2c",
336 + .mask = RT3883_GPIO_MODE_I2C,
337 + .gpio_first = RT3883_GPIO_I2C_SD,
338 + .gpio_last = RT3883_GPIO_I2C_SCLK,
339 + }, {
340 + .name = "spi",
341 + .mask = RT3883_GPIO_MODE_SPI,
342 + .gpio_first = RT3883_GPIO_SPI_CS0,
343 + .gpio_last = RT3883_GPIO_SPI_MISO,
344 + }, {
345 + .name = "uartlite",
346 + .mask = RT3883_GPIO_MODE_UART1,
347 + .gpio_first = RT3883_GPIO_UART1_TXD,
348 + .gpio_last = RT3883_GPIO_UART1_RXD,
349 + }, {
350 + .name = "jtag",
351 + .mask = RT3883_GPIO_MODE_JTAG,
352 + .gpio_first = RT3883_GPIO_JTAG_TDO,
353 + .gpio_last = RT3883_GPIO_JTAG_TCLK,
354 + }, {
355 + .name = "mdio",
356 + .mask = RT3883_GPIO_MODE_MDIO,
357 + .gpio_first = RT3883_GPIO_MDIO_MDC,
358 + .gpio_last = RT3883_GPIO_MDIO_MDIO,
359 + }, {
360 + .name = "ge1",
361 + .mask = RT3883_GPIO_MODE_GE1,
362 + .gpio_first = RT3883_GPIO_GE1_TXD0,
363 + .gpio_last = RT3883_GPIO_GE1_RXCLK,
364 + }, {
365 + .name = "ge2",
366 + .mask = RT3883_GPIO_MODE_GE2,
367 + .gpio_first = RT3883_GPIO_GE2_TXD0,
368 + .gpio_last = RT3883_GPIO_GE2_RXCLK,
369 + }, {
370 + .name = "pci",
371 + .mask = RT3883_GPIO_MODE_PCI,
372 + .gpio_first = RT3883_GPIO_PCI_AD0,
373 + .gpio_last = RT3883_GPIO_PCI_AD31,
374 + }, {
375 + .name = "lna a",
376 + .mask = RT3883_GPIO_MODE_LNA_A,
377 + .gpio_first = RT3883_GPIO_LNA_PE_A0,
378 + .gpio_last = RT3883_GPIO_LNA_PE_A2,
379 + }, {
380 + .name = "lna g",
381 + .mask = RT3883_GPIO_MODE_LNA_G,
382 + .gpio_first = RT3883_GPIO_LNA_PE_G0,
383 + .gpio_last = RT3883_GPIO_LNA_PE_G2,
384 + }, {0}
385 +};
386 +
387 +static struct ralink_pinmux_grp uart_mux[] = {
388 + {
389 + .name = "uartf",
390 + .mask = RT3883_GPIO_MODE_UARTF,
391 + .gpio_first = RT3883_GPIO_7,
392 + .gpio_last = RT3883_GPIO_14,
393 + }, {
394 + .name = "pcm uartf",
395 + .mask = RT3883_GPIO_MODE_PCM_UARTF,
396 + .gpio_first = RT3883_GPIO_7,
397 + .gpio_last = RT3883_GPIO_14,
398 + }, {
399 + .name = "pcm i2s",
400 + .mask = RT3883_GPIO_MODE_PCM_I2S,
401 + .gpio_first = RT3883_GPIO_7,
402 + .gpio_last = RT3883_GPIO_14,
403 + }, {
404 + .name = "i2s uartf",
405 + .mask = RT3883_GPIO_MODE_I2S_UARTF,
406 + .gpio_first = RT3883_GPIO_7,
407 + .gpio_last = RT3883_GPIO_14,
408 + }, {
409 + .name = "pcm gpio",
410 + .mask = RT3883_GPIO_MODE_PCM_GPIO,
411 + .gpio_first = RT3883_GPIO_11,
412 + .gpio_last = RT3883_GPIO_14,
413 + }, {
414 + .name = "gpio uartf",
415 + .mask = RT3883_GPIO_MODE_GPIO_UARTF,
416 + .gpio_first = RT3883_GPIO_7,
417 + .gpio_last = RT3883_GPIO_10,
418 + }, {
419 + .name = "gpio i2s",
420 + .mask = RT3883_GPIO_MODE_GPIO_I2S,
421 + .gpio_first = RT3883_GPIO_7,
422 + .gpio_last = RT3883_GPIO_10,
423 + }, {
424 + .name = "gpio",
425 + .mask = RT3883_GPIO_MODE_GPIO,
426 + }, {0}
427 +};
428 +
429 +static struct ralink_pinmux_grp pci_mux[] = {
430 + {
431 + .name = "pci-dev",
432 + .mask = 0,
433 + .gpio_first = RT3883_GPIO_PCI_AD0,
434 + .gpio_last = RT3883_GPIO_PCI_AD31,
435 + }, {
436 + .name = "pci-host2",
437 + .mask = 1,
438 + .gpio_first = RT3883_GPIO_PCI_AD0,
439 + .gpio_last = RT3883_GPIO_PCI_AD31,
440 + }, {
441 + .name = "pci-host1",
442 + .mask = 2,
443 + .gpio_first = RT3883_GPIO_PCI_AD0,
444 + .gpio_last = RT3883_GPIO_PCI_AD31,
445 + }, {
446 + .name = "pci-fnc",
447 + .mask = 3,
448 + .gpio_first = RT3883_GPIO_PCI_AD0,
449 + .gpio_last = RT3883_GPIO_PCI_AD31,
450 + }, {
451 + .name = "pci-gpio",
452 + .mask = 7,
453 + .gpio_first = RT3883_GPIO_PCI_AD0,
454 + .gpio_last = RT3883_GPIO_PCI_AD31,
455 + }, {0}
456 +};
457 +
458 +static void rt3883_wdt_reset(void)
459 +{
460 + u32 t;
461 +
462 + /* enable WDT reset output on GPIO 2 */
463 + t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
464 + t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
465 + rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
466 +}
467 +
468 +struct ralink_pinmux rt_gpio_pinmux = {
469 + .mode = mode_mux,
470 + .uart = uart_mux,
471 + .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
472 + .uart_mask = RT3883_GPIO_MODE_GPIO,
473 + .wdt_reset = rt3883_wdt_reset,
474 + .pci = pci_mux,
475 + .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
476 + .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
477 +};
478 +
479 +void __init ralink_clk_init(void)
480 +{
481 + unsigned long cpu_rate, sys_rate;
482 + u32 syscfg0;
483 + u32 clksel;
484 + u32 ddr2;
485 +
486 + syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
487 + clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
488 + RT3883_SYSCFG0_CPUCLK_MASK);
489 + ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
490 +
491 + switch (clksel) {
492 + case RT3883_SYSCFG0_CPUCLK_250:
493 + cpu_rate = 250000000;
494 + sys_rate = (ddr2) ? 125000000 : 83000000;
495 + break;
496 + case RT3883_SYSCFG0_CPUCLK_384:
497 + cpu_rate = 384000000;
498 + sys_rate = (ddr2) ? 128000000 : 96000000;
499 + break;
500 + case RT3883_SYSCFG0_CPUCLK_480:
501 + cpu_rate = 480000000;
502 + sys_rate = (ddr2) ? 160000000 : 120000000;
503 + break;
504 + case RT3883_SYSCFG0_CPUCLK_500:
505 + cpu_rate = 500000000;
506 + sys_rate = (ddr2) ? 166000000 : 125000000;
507 + break;
508 + }
509 +
510 + ralink_clk_add("cpu", cpu_rate);
511 + ralink_clk_add("10000100.timer", sys_rate);
512 + ralink_clk_add("10000120.watchdog", sys_rate);
513 + ralink_clk_add("10000500.uart", 40000000);
514 + ralink_clk_add("10000b00.spi", sys_rate);
515 + ralink_clk_add("10000c00.uartlite", 40000000);
516 + ralink_clk_add("10100000.ethernet", sys_rate);
517 +}
518 +
519 +void __init ralink_of_remap(void)
520 +{
521 + rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
522 + rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
523 +
524 + if (!rt_sysc_membase || !rt_memc_membase)
525 + panic("Failed to remap core resources");
526 +}
527 +
528 +void prom_soc_init(struct ralink_soc_info *soc_info)
529 +{
530 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
531 + const char *name;
532 + u32 n0;
533 + u32 n1;
534 + u32 id;
535 +
536 + n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
537 + n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
538 + id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
539 +
540 + if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
541 + soc_info->compatible = "ralink,rt3883-soc";
542 + name = "RT3883";
543 + } else {
544 + panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
545 + }
546 +
547 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
548 + "Ralink %s ver:%u eco:%u",
549 + name,
550 + (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
551 + (id & RT3883_REVID_ECO_ID_MASK));
552 +}
Yousong Zhou staging tree