target/linux/ramips/patches-3.8/0119-PCI-MIPS-adds-rt3883-pci-support.patch

   1 From f01830fcc57273bd9ec5f6733ab3d28adeb71955 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:34:08 +0100
   4 Subject: [PATCH 119/121] PCI: MIPS: adds rt3883 pci support
   5
   6 Add support for the pcie found on the rt3883 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt3883.c |  487 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 489 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt3883.c
  15
  16 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  17 index 77974ba..3cbfd9b 100644
  18 --- a/arch/mips/pci/Makefile
  19 +++ b/arch/mips/pci/Makefile
  20 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
  21  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  22  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  23  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  24 +obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  25  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  26  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  27  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
  28 diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
  29 new file mode 100644
  30 index 0000000..8a4c8ce
  31 --- /dev/null
  32 +++ b/arch/mips/pci/pci-rt3883.c
  33 @@ -0,0 +1,487 @@
  34 +/*
  35 + *  Ralink RT3883 SoC PCI support
  36 + *
  37 + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  38 + *
  39 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  40 + *
  41 + *  This program is free software; you can redistribute it and/or modify it
  42 + *  under the terms of the GNU General Public License version 2 as published
  43 + *  by the Free Software Foundation.
  44 + */
  45 +
  46 +#include <linux/types.h>
  47 +#include <linux/pci.h>
  48 +#include <linux/io.h>
  49 +#include <linux/init.h>
  50 +#include <linux/delay.h>
  51 +#include <linux/interrupt.h>
  52 +
  53 +#include <asm/mach-ralink/rt3883.h>
  54 +#include <asm/mach-ralink/rt3883_regs.h>
  55 +
  56 +#define RT3883_MEMORY_BASE             0x00000000
  57 +#define RT3883_MEMORY_SIZE             0x02000000
  58 +
  59 +#define RT3883_PCI_MEM_BASE            0x20000000
  60 +#define RT3883_PCI_MEM_SIZE            0x10000000
  61 +#define RT3883_PCI_IO_BASE             0x10160000
  62 +#define RT3883_PCI_IO_SIZE             0x00010000
  63 +
  64 +#define RT3883_PCI_REG_PCICFG_ADDR     0x00
  65 +#define RT3883_PCI_REG_PCIRAW_ADDR     0x04
  66 +#define RT3883_PCI_REG_PCIINT_ADDR     0x08
  67 +#define RT3883_PCI_REG_PCIMSK_ADDR     0x0c
  68 +#define   RT3833_PCI_PCIINT_PCIE       BIT(20)
  69 +#define   RT3833_PCI_PCIINT_PCI1       BIT(19)
  70 +#define   RT3833_PCI_PCIINT_PCI0       BIT(18)
  71 +
  72 +#define RT3883_PCI_REG_CONFIG_ADDR     0x20
  73 +#define RT3883_PCI_REG_CONFIG_DATA     0x24
  74 +#define RT3883_PCI_REG_MEMBASE         0x28
  75 +#define RT3883_PCI_REG_IOBASE          0x2c
  76 +#define RT3883_PCI_REG_ARBCTL          0x80
  77 +
  78 +#define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
  79 +#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
  80 +#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
  81 +#define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
  82 +#define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
  83 +#define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
  84 +#define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
  85 +
  86 +static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
  87 +static void __iomem *rt3883_pci_base;
  88 +static DEFINE_SPINLOCK(rt3883_pci_lock);
  89 +
  90 +static inline u32 rt3883_pci_rr(unsigned reg)
  91 +{
  92 +       return readl(rt3883_pci_base + reg);
  93 +}
  94 +
  95 +static inline void rt3883_pci_wr(u32 val, unsigned reg)
  96 +{
  97 +       writel(val, rt3883_pci_base + reg);
  98 +}
  99 +
 100 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 101 +                                        unsigned int func, unsigned int where)
 102 +{
 103 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
 104 +               0x80000000);
 105 +}
 106 +
 107 +static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
 108 +                              unsigned func, unsigned reg)
 109 +{
 110 +       unsigned long flags;
 111 +       u32 address;
 112 +       u32 ret;
 113 +
 114 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 115 +
 116 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 117 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 118 +       ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 119 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 120 +
 121 +       return ret;
 122 +}
 123 +
 124 +static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
 125 +                                unsigned func, unsigned reg, u32 val)
 126 +{
 127 +       unsigned long flags;
 128 +       u32 address;
 129 +
 130 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 131 +
 132 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 133 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 134 +       rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
 135 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 136 +}
 137 +
 138 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 139 +{
 140 +       u32 pending;
 141 +
 142 +       pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
 143 +                 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 144 +
 145 +       if (!pending) {
 146 +               spurious_interrupt();
 147 +               return;
 148 +       }
 149 +
 150 +       if (pending & RT3833_PCI_PCIINT_PCI0)
 151 +               generic_handle_irq(RT3883_PCI_IRQ_PCI0);
 152 +
 153 +       if (pending & RT3833_PCI_PCIINT_PCI1)
 154 +               generic_handle_irq(RT3883_PCI_IRQ_PCI1);
 155 +
 156 +       if (pending & RT3833_PCI_PCIINT_PCIE)
 157 +               generic_handle_irq(RT3883_PCI_IRQ_PCIE);
 158 +}
 159 +
 160 +static void rt3883_pci_irq_unmask(struct irq_data *d)
 161 +{
 162 +       int irq = d->irq;
 163 +       u32 mask;
 164 +       u32 t;
 165 +
 166 +       switch (irq) {
 167 +       case RT3883_PCI_IRQ_PCI0:
 168 +               mask = RT3833_PCI_PCIINT_PCI0;
 169 +               break;
 170 +       case RT3883_PCI_IRQ_PCI1:
 171 +               mask = RT3833_PCI_PCIINT_PCI1;
 172 +               break;
 173 +       case RT3883_PCI_IRQ_PCIE:
 174 +               mask = RT3833_PCI_PCIINT_PCIE;
 175 +               break;
 176 +       default:
 177 +               BUG();
 178 +       }
 179 +
 180 +       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 181 +       rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
 182 +       /* flush write */
 183 +       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 184 +}
 185 +
 186 +static void rt3883_pci_irq_mask(struct irq_data *d)
 187 +{
 188 +       int irq = d->irq;
 189 +       u32 mask;
 190 +       u32 t;
 191 +
 192 +       switch (irq) {
 193 +       case RT3883_PCI_IRQ_PCI0:
 194 +               mask = RT3833_PCI_PCIINT_PCI0;
 195 +               break;
 196 +       case RT3883_PCI_IRQ_PCI1:
 197 +               mask = RT3833_PCI_PCIINT_PCI1;
 198 +               break;
 199 +       case RT3883_PCI_IRQ_PCIE:
 200 +               mask = RT3833_PCI_PCIINT_PCIE;
 201 +               break;
 202 +       default:
 203 +               BUG();
 204 +       }
 205 +
 206 +       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 207 +       rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
 208 +       /* flush write */
 209 +       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 210 +}
 211 +
 212 +static struct irq_chip rt3883_pci_irq_chip = {
 213 +       .name           = "RT3883 PCI",
 214 +       .irq_mask       = rt3883_pci_irq_mask,
 215 +       .irq_unmask     = rt3883_pci_irq_unmask,
 216 +       .irq_mask_ack   = rt3883_pci_irq_mask,
 217 +};
 218 +
 219 +static void __init rt3883_pci_irq_init(void)
 220 +{
 221 +       int i;
 222 +
 223 +       /* disable all interrupts */
 224 +       rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
 225 +
 226 +       for (i = RT3883_PCI_IRQ_BASE;
 227 +            i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
 228 +               irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
 229 +                                        handle_level_irq);
 230 +       }
 231 +
 232 +       irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
 233 +}
 234 +
 235 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 236 +                                 int where, int size, u32 *val)
 237 +{
 238 +       unsigned long flags;
 239 +       u32 address;
 240 +       u32 data;
 241 +
 242 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 243 +                                        PCI_FUNC(devfn), where);
 244 +
 245 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 246 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 247 +       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 248 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 249 +
 250 +       switch (size) {
 251 +       case 1:
 252 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 253 +               break;
 254 +       case 2:
 255 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 256 +               break;
 257 +       case 4:
 258 +               *val = data;
 259 +               break;
 260 +       }
 261 +
 262 +       return PCIBIOS_SUCCESSFUL;
 263 +}
 264 +
 265 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 266 +                                  int where, int size, u32 val)
 267 +{
 268 +       unsigned long flags;
 269 +       u32 address;
 270 +       u32 data;
 271 +
 272 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 273 +                                        PCI_FUNC(devfn), where);
 274 +
 275 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 276 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 277 +       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 278 +
 279 +       switch (size) {
 280 +       case 1:
 281 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 282 +                      (val << ((where & 3) << 3));
 283 +               break;
 284 +       case 2:
 285 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 286 +                      (val << ((where & 3) << 3));
 287 +               break;
 288 +       case 4:
 289 +               data = val;
 290 +               break;
 291 +       }
 292 +
 293 +       rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
 294 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 295 +
 296 +       return PCIBIOS_SUCCESSFUL;
 297 +}
 298 +
 299 +static struct pci_ops rt3883_pci_ops = {
 300 +       .read   = rt3883_pci_config_read,
 301 +       .write  = rt3883_pci_config_write,
 302 +};
 303 +
 304 +static struct resource rt3883_pci_mem_resource = {
 305 +       .name   = "PCI MEM space",
 306 +       .start  = RT3883_PCI_MEM_BASE,
 307 +       .end    = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
 308 +       .flags  = IORESOURCE_MEM,
 309 +};
 310 +
 311 +static struct resource rt3883_pci_io_resource = {
 312 +       .name   = "PCI IO space",
 313 +       .start  = RT3883_PCI_IO_BASE,
 314 +       .end    = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
 315 +       .flags  = IORESOURCE_IO,
 316 +};
 317 +
 318 +static struct pci_controller rt3883_pci_controller = {
 319 +       .pci_ops        = &rt3883_pci_ops,
 320 +       .mem_resource   = &rt3883_pci_mem_resource,
 321 +       .io_resource    = &rt3883_pci_io_resource,
 322 +};
 323 +
 324 +static void rt3883_pci_preinit(unsigned mode)
 325 +{
 326 +       u32 syscfg1;
 327 +       u32 rstctrl;
 328 +       u32 clkcfg1;
 329 +
 330 +       if (mode & RT3883_PCI_MODE_PCIE) {
 331 +               u32 val;
 332 +
 333 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 334 +               val &= ~(0x30);
 335 +               val |= (2 << 4);
 336 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
 337 +
 338 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 339 +               val &= ~BIT(31);
 340 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 341 +
 342 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 343 +               val &= 0x80ffffff;
 344 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 345 +
 346 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 347 +               val |= 0xa << 24;
 348 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 349 +
 350 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 351 +               val |= BIT(31);
 352 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 353 +
 354 +               msleep(50);
 355 +       }
 356 +
 357 +       syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 358 +       syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
 359 +                    RT3883_SYSCFG1_PCI_HOST_MODE);
 360 +
 361 +       rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
 362 +       rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
 363 +
 364 +       clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
 365 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
 366 +                    RT3883_CLKCFG1_PCIE_CLK_EN);
 367 +
 368 +       if (mode & RT3883_PCI_MODE_PCI) {
 369 +               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
 370 +               clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 371 +               rstctrl &= ~RT3883_RSTCTRL_PCI;
 372 +       }
 373 +       if (mode & RT3883_PCI_MODE_PCIE) {
 374 +               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
 375 +                          RT3883_SYSCFG1_PCIE_RC_MODE;
 376 +               clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 377 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 378 +       }
 379 +
 380 +       rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 381 +       rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 382 +       rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 383 +
 384 +       msleep(500);
 385 +}
 386 +
 387 +static int rt3883_pcie_ready(void)
 388 +{
 389 +       u32 status;
 390 +
 391 +       msleep(500);
 392 +
 393 +       status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
 394 +       if (status & BIT(0))
 395 +               return 0;
 396 +
 397 +       /* TODO: reset PCIe and turn off PCIe clock */
 398 +
 399 +       return -ENODEV;
 400 +}
 401 +
 402 +void __init rt3883_pci_init(unsigned mode)
 403 +{
 404 +       u32 val;
 405 +       int err;
 406 +
 407 +       rt3883_pci_preinit(mode);
 408 +
 409 +       rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
 410 +       if (rt3883_pci_base == NULL) {
 411 +               pr_err("failed to ioremap PCI registers\n");
 412 +               return;
 413 +       }
 414 +
 415 +       rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
 416 +       if (mode & RT3883_PCI_MODE_PCI)
 417 +               rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
 418 +
 419 +       msleep(500);
 420 +
 421 +       if (mode & RT3883_PCI_MODE_PCIE) {
 422 +               err = rt3883_pcie_ready();
 423 +               if (err)
 424 +                       return;
 425 +       }
 426 +
 427 +       if (mode & RT3883_PCI_MODE_PCI)
 428 +               rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
 429 +
 430 +       rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
 431 +       rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
 432 +
 433 +       /* PCI */
 434 +       rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 435 +       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
 436 +       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
 437 +       rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
 438 +       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
 439 +
 440 +       /* PCIe */
 441 +       rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 442 +       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
 443 +       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
 444 +       rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
 445 +       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
 446 +
 447 +       rt3883_pci_irq_init();
 448 +
 449 +       /* PCIe */
 450 +       val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
 451 +       val |= 0x7;
 452 +       rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
 453 +
 454 +       /* PCI */
 455 +       val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
 456 +       val |= 0x7;
 457 +       rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
 458 +
 459 +       ioport_resource.start = rt3883_pci_io_resource.start;
 460 +       ioport_resource.end = rt3883_pci_io_resource.end;
 461 +
 462 +       register_pci_controller(&rt3883_pci_controller);
 463 +}
 464 +
 465 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 466 +{
 467 +       int irq = -1;
 468 +
 469 +       switch (dev->bus->number) {
 470 +       case 0:
 471 +               switch (PCI_SLOT(dev->devfn)) {
 472 +               case 0x00:
 473 +                       rt3883_pci_wr(0x03ff0001,
 474 +                                            RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 475 +                       rt3883_pci_wr(0x03ff0001,
 476 +                                            RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 477 +
 478 +                       rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
 479 +                                            RT3883_MEMORY_BASE);
 480 +                       rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
 481 +
 482 +                       irq = RT3883_CPU_IRQ_PCI;
 483 +                       break;
 484 +               case 0x01:
 485 +                       rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
 486 +                                            0x00000101);
 487 +                       break;
 488 +               case 0x11:
 489 +                       irq = RT3883_PCI_IRQ_PCI0;
 490 +                       break;
 491 +               case 0x12:
 492 +                       irq = RT3883_PCI_IRQ_PCI1;
 493 +                       break;
 494 +               }
 495 +               break;
 496 +
 497 +       case 1:
 498 +               irq = RT3883_PCI_IRQ_PCIE;
 499 +               break;
 500 +
 501 +       default:
 502 +               dev_err(&dev->dev, "no IRQ specified\n");
 503 +               return irq;
 504 +       }
 505 +
 506 +       return irq;
 507 +}
 508 +
 509 +void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
 510 +{
 511 +       rt3883_pci_plat_dev_init = f;
 512 +}
 513 +
 514 +int pcibios_plat_dev_init(struct pci_dev *dev)
 515 +{
 516 +       if (rt3883_pci_plat_dev_init)
 517 +               return rt3883_pci_plat_dev_init(dev);
 518 +
 519 +       return 0;
 520 +}
 521 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 522 index a3eec2a..2b7b70a 100644
 523 --- a/arch/mips/ralink/Kconfig
 524 +++ b/arch/mips/ralink/Kconfig
 525 @@ -20,6 +20,7 @@ choice
 526                 bool "RT3883"
 527                 select USB_ARCH_HAS_OHCI
 528                 select USB_ARCH_HAS_EHCI
 529 +               select HW_HAS_PCI
 530
 531         config SOC_MT7620
 532                 bool "MT7620"
 533 --
 534 1.7.10.4
 535