target/linux/sunxi/patches-3.13/113-clk-sunxi-register-factors-clocks.patch

   1 From 9212bc4a3752e9a4db2f73afd99278eb28e5dcff Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:32 -0300
   4 Subject: [PATCH] clk: sunxi: register factors clocks behind composite
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit reworks factors clock registration to be done behind a
  10 composite clock. This allows us to additionally add a gate, mux or
  11 divisors, as it will be needed by some future PLLs.
  12
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 ---
  16  drivers/clk/sunxi/clk-factors.c | 63 +------------------------------------
  17  drivers/clk/sunxi/clk-factors.h | 16 +++++-----
  18  drivers/clk/sunxi/clk-sunxi.c   | 70 ++++++++++++++++++++++++++++++++++++++---
  19  3 files changed, 76 insertions(+), 73 deletions(-)
  20
  21 diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
  22 index f05207a..9e23264 100644
  23 --- a/drivers/clk/sunxi/clk-factors.c
  24 +++ b/drivers/clk/sunxi/clk-factors.c
  25 @@ -30,14 +30,6 @@
  26   * parent - fixed parent.  No clk_set_parent support
  27   */
  28
  29 -struct clk_factors {
  30 -       struct clk_hw hw;
  31 -       void __iomem *reg;
  32 -       struct clk_factors_config *config;
  33 -       void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
  34 -       spinlock_t *lock;
  35 -};
  36 -
  37  #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
  38
  39  #define SETMASK(len, pos)              (((1U << (len)) - 1) << (pos))
  40 @@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
  41         return 0;
  42  }
  43
  44 -static const struct clk_ops clk_factors_ops = {
  45 +const struct clk_ops clk_factors_ops = {
  46         .recalc_rate = clk_factors_recalc_rate,
  47         .round_rate = clk_factors_round_rate,
  48         .set_rate = clk_factors_set_rate,
  49  };
  50 -
  51 -/**
  52 - * clk_register_factors - register a factors clock with
  53 - * the clock framework
  54 - * @dev: device registering this clock
  55 - * @name: name of this clock
  56 - * @parent_name: name of clock's parent
  57 - * @flags: framework-specific flags
  58 - * @reg: register address to adjust factors
  59 - * @config: shift and width of factors n, k, m and p
  60 - * @get_factors: function to calculate the factors for a given frequency
  61 - * @lock: shared register lock for this clock
  62 - */
  63 -struct clk *clk_register_factors(struct device *dev, const char *name,
  64 -                                const char *parent_name,
  65 -                                unsigned long flags, void __iomem *reg,
  66 -                                struct clk_factors_config *config,
  67 -                                void (*get_factors)(u32 *rate, u32 parent,
  68 -                                                    u8 *n, u8 *k, u8 *m, u8 *p),
  69 -                                spinlock_t *lock)
  70 -{
  71 -       struct clk_factors *factors;
  72 -       struct clk *clk;
  73 -       struct clk_init_data init;
  74 -
  75 -       /* allocate the factors */
  76 -       factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
  77 -       if (!factors) {
  78 -               pr_err("%s: could not allocate factors clk\n", __func__);
  79 -               return ERR_PTR(-ENOMEM);
  80 -       }
  81 -
  82 -       init.name = name;
  83 -       init.ops = &clk_factors_ops;
  84 -       init.flags = flags;
  85 -       init.parent_names = (parent_name ? &parent_name : NULL);
  86 -       init.num_parents = (parent_name ? 1 : 0);
  87 -
  88 -       /* struct clk_factors assignments */
  89 -       factors->reg = reg;
  90 -       factors->config = config;
  91 -       factors->lock = lock;
  92 -       factors->hw.init = &init;
  93 -       factors->get_factors = get_factors;
  94 -
  95 -       /* register the clock */
  96 -       clk = clk_register(dev, &factors->hw);
  97 -
  98 -       if (IS_ERR(clk))
  99 -               kfree(factors);
 100 -
 101 -       return clk;
 102 -}
 103 diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
 104 index f49851c..02e1a43 100644
 105 --- a/drivers/clk/sunxi/clk-factors.h
 106 +++ b/drivers/clk/sunxi/clk-factors.h
 107 @@ -17,11 +17,13 @@ struct clk_factors_config {
 108         u8 pwidth;
 109  };
 110
 111 -struct clk *clk_register_factors(struct device *dev, const char *name,
 112 -                                const char *parent_name,
 113 -                                unsigned long flags, void __iomem *reg,
 114 -                                struct clk_factors_config *config,
 115 -                                void (*get_factors) (u32 *rate, u32 parent_rate,
 116 -                                                     u8 *n, u8 *k, u8 *m, u8 *p),
 117 -                                spinlock_t *lock);
 118 +struct clk_factors {
 119 +       struct clk_hw hw;
 120 +       void __iomem *reg;
 121 +       struct clk_factors_config *config;
 122 +       void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
 123 +       spinlock_t *lock;
 124 +};
 125 +
 126 +extern const struct clk_ops clk_factors_ops;
 127  #endif
 128 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
 129 index 492ef0e..7dc39a6 100644
 130 --- a/drivers/clk/sunxi/clk-sunxi.c
 131 +++ b/drivers/clk/sunxi/clk-sunxi.c
 132 @@ -23,6 +23,9 @@
 133
 134  static DEFINE_SPINLOCK(clk_lock);
 135
 136 +/* Maximum number of parents our clocks have */
 137 +#define SUNXI_MAX_PARENTS      5
 138 +
 139  /**
 140   * sun4i_osc_clk_setup() - Setup function for gatable oscillator
 141   */
 142 @@ -261,7 +264,11 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 143   * sunxi_factors_clk_setup() - Setup function for factor clocks
 144   */
 145
 146 +#define SUNXI_FACTORS_MUX_MASK 0x3
 147 +
 148  struct factors_data {
 149 +       int enable;
 150 +       int mux;
 151         struct clk_factors_config *table;
 152         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 153  };
 154 @@ -312,16 +319,71 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
 155                                            struct factors_data *data)
 156  {
 157         struct clk *clk;
 158 +       struct clk_factors *factors;
 159 +       struct clk_gate *gate = NULL;
 160 +       struct clk_mux *mux = NULL;
 161 +       struct clk_hw *gate_hw = NULL;
 162 +       struct clk_hw *mux_hw = NULL;
 163         const char *clk_name = node->name;
 164 -       const char *parent;
 165 +       const char *parents[SUNXI_MAX_PARENTS];
 166         void *reg;
 167 +       int i = 0;
 168
 169         reg = of_iomap(node, 0);
 170
 171 -       parent = of_clk_get_parent_name(node, 0);
 172 +       /* if we have a mux, we will have >1 parents */
 173 +       while (i < SUNXI_MAX_PARENTS &&
 174 +              (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 175 +               i++;
 176 +
 177 +       factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
 178 +       if (!factors)
 179 +               return;
 180 +
 181 +       /* Add a gate if this factor clock can be gated */
 182 +       if (data->enable) {
 183 +               gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 184 +               if (!gate) {
 185 +                       kfree(factors);
 186 +                       return;
 187 +               }
 188 +
 189 +               /* set up gate properties */
 190 +               gate->reg = reg;
 191 +               gate->bit_idx = data->enable;
 192 +               gate->lock = &clk_lock;
 193 +               gate_hw = &gate->hw;
 194 +       }
 195 +
 196 +       /* Add a mux if this factor clock can be muxed */
 197 +       if (data->mux) {
 198 +               mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 199 +               if (!mux) {
 200 +                       kfree(factors);
 201 +                       kfree(gate);
 202 +                       return;
 203 +               }
 204 +
 205 +               /* set up gate properties */
 206 +               mux->reg = reg;
 207 +               mux->shift = data->mux;
 208 +               mux->mask = SUNXI_FACTORS_MUX_MASK;
 209 +               mux->lock = &clk_lock;
 210 +               mux_hw = &mux->hw;
 211 +       }
 212 +
 213 +       /* set up factors properties */
 214 +       factors->reg = reg;
 215 +       factors->config = data->table;
 216 +       factors->get_factors = data->getter;
 217 +       factors->lock = &clk_lock;
 218
 219 -       clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
 220 -                                  data->table, data->getter, &clk_lock);
 221 +       clk = clk_register_composite(NULL, clk_name,
 222 +                       parents, i,
 223 +                       mux_hw, &clk_mux_ops,
 224 +                       &factors->hw, &clk_factors_ops,
 225 +                       gate_hw, &clk_gate_ops,
 226 +                       i ? 0 : CLK_IS_ROOT);
 227
 228         if (!IS_ERR(clk)) {
 229                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 230 --
 231 1.8.5.1
 232