target/linux/sunxi/patches-3.13/128-dt-sunxi-add-mbusclk.patch

   1 From 538d4a6ca5f41039d906f28be82e0f4d26ec8ac9 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:44 -0300
   4 Subject: [PATCH] ARM: sunxi: dt: add nodes for the mbus clock
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 mbus is the memory bus clock, and it is present on both sun5i and sun7i
  10 machines. Its register layout is compatible with the mod0 one.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
  16  arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
  17  arch/arm/boot/dts/sun7i-a20.dtsi  | 8 ++++++++
  18  3 files changed, 24 insertions(+)
  19
  20 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  21 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  22 @@ -257,6 +257,14 @@
  23                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  24                         clock-output-names = "ir0";
  25                 };
  26 +
  27 +               mbus_clk: clk@01c2015c {
  28 +                       #clock-cells = <0>;
  29 +                       compatible = "allwinner,sun4i-mod0-clk";
  30 +                       reg = <0x01c2015c 0x4>;
  31 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  32 +                       clock-output-names = "mbus";
  33 +               };
  34         };
  35
  36         soc@01c00000 {
  37 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
  38 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
  39 @@ -258,6 +258,14 @@
  40                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  41                         clock-output-names = "ir0";
  42                 };
  43 +
  44 +               mbus_clk: clk@01c2015c {
  45 +                       #clock-cells = <0>;
  46 +                       compatible = "allwinner,sun4i-mod0-clk";
  47 +                       reg = <0x01c2015c 0x4>;
  48 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  49 +                       clock-output-names = "mbus";
  50 +               };
  51         };
  52
  53         soc@01c00000 {
  54 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  55 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  56 @@ -290,6 +290,14 @@
  57                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  58                         clock-output-names = "spi3";
  59                 };
  60 +
  61 +               mbus_clk: clk@01c2015c {
  62 +                       #clock-cells = <0>;
  63 +                       compatible = "allwinner,sun4i-mod0-clk";
  64 +                       reg = <0x01c2015c 0x4>;
  65 +                       clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
  66 +                       clock-output-names = "mbus";
  67 +               };
  68         };
  69
  70         soc@01c00000 {