target/linux/sunxi/patches-3.14/112-dt-sun5i-rename-clocknodes.patch

   1 From 266f79cef78cdf3545065a4786506eee0ae012b3 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:42 +0800
   4 Subject: [PATCH] ARM: dts: sun5i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun5i-a10s.dtsi | 30 ++++++++++++++++++++----------
  14  arch/arm/boot/dts/sun5i-a13.dtsi  | 30 ++++++++++++++++++++----------
  15  2 files changed, 40 insertions(+), 20 deletions(-)
  16
  17 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  18 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  19 @@ -47,34 +47,38 @@
  20                         clock-frequency = <0>;
  21                 };
  22
  23 -               osc24M: osc24M@01c20050 {
  24 +               osc24M: clk@01c20050 {
  25                         #clock-cells = <0>;
  26                         compatible = "allwinner,sun4i-osc-clk";
  27                         reg = <0x01c20050 0x4>;
  28                         clock-frequency = <24000000>;
  29 +                       clock-output-names = "osc24M";
  30                 };
  31
  32 -               osc32k: osc32k {
  33 +               osc32k: clk@0 {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <32768>;
  37 +                       clock-output-names = "osc32k";
  38                 };
  39
  40 -               pll1: pll1@01c20000 {
  41 +               pll1: clk@01c20000 {
  42                         #clock-cells = <0>;
  43                         compatible = "allwinner,sun4i-pll1-clk";
  44                         reg = <0x01c20000 0x4>;
  45                         clocks = <&osc24M>;
  46 +                       clock-output-names = "pll1";
  47                 };
  48
  49 -               pll4: pll4@01c20018 {
  50 +               pll4: clk@01c20018 {
  51                         #clock-cells = <0>;
  52                         compatible = "allwinner,sun4i-pll1-clk";
  53                         reg = <0x01c20018 0x4>;
  54                         clocks = <&osc24M>;
  55 +                       clock-output-names = "pll4";
  56                 };
  57
  58 -               pll5: pll5@01c20020 {
  59 +               pll5: clk@01c20020 {
  60                         #clock-cells = <1>;
  61                         compatible = "allwinner,sun4i-pll5-clk";
  62                         reg = <0x01c20020 0x4>;
  63 @@ -82,7 +86,7 @@
  64                         clock-output-names = "pll5_ddr", "pll5_other";
  65                 };
  66
  67 -               pll6: pll6@01c20028 {
  68 +               pll6: clk@01c20028 {
  69                         #clock-cells = <1>;
  70                         compatible = "allwinner,sun4i-pll6-clk";
  71                         reg = <0x01c20028 0x4>;
  72 @@ -96,6 +100,7 @@
  73                         compatible = "allwinner,sun4i-cpu-clk";
  74                         reg = <0x01c20054 0x4>;
  75                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  76 +                       clock-output-names = "cpu";
  77                 };
  78
  79                 axi: axi@01c20054 {
  80 @@ -103,9 +108,10 @@
  81                         compatible = "allwinner,sun4i-axi-clk";
  82                         reg = <0x01c20054 0x4>;
  83                         clocks = <&cpu>;
  84 +                       clock-output-names = "axi";
  85                 };
  86
  87 -               axi_gates: axi_gates@01c2005c {
  88 +               axi_gates: clk@01c2005c {
  89                         #clock-cells = <1>;
  90                         compatible = "allwinner,sun4i-axi-gates-clk";
  91                         reg = <0x01c2005c 0x4>;
  92 @@ -118,9 +124,10 @@
  93                         compatible = "allwinner,sun4i-ahb-clk";
  94                         reg = <0x01c20054 0x4>;
  95                         clocks = <&axi>;
  96 +                       clock-output-names = "ahb";
  97                 };
  98
  99 -               ahb_gates: ahb_gates@01c20060 {
 100 +               ahb_gates: clk@01c20060 {
 101                         #clock-cells = <1>;
 102                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 103                         reg = <0x01c20060 0x8>;
 104 @@ -139,9 +146,10 @@
 105                         compatible = "allwinner,sun4i-apb0-clk";
 106                         reg = <0x01c20054 0x4>;
 107                         clocks = <&ahb>;
 108 +                       clock-output-names = "apb0";
 109                 };
 110
 111 -               apb0_gates: apb0_gates@01c20068 {
 112 +               apb0_gates: clk@01c20068 {
 113                         #clock-cells = <1>;
 114                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 115                         reg = <0x01c20068 0x4>;
 116 @@ -155,6 +163,7 @@
 117                         compatible = "allwinner,sun4i-apb1-mux-clk";
 118                         reg = <0x01c20058 0x4>;
 119                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 120 +                       clock-output-names = "apb1_mux";
 121                 };
 122
 123                 apb1: apb1@01c20058 {
 124 @@ -162,9 +171,10 @@
 125                         compatible = "allwinner,sun4i-apb1-clk";
 126                         reg = <0x01c20058 0x4>;
 127                         clocks = <&apb1_mux>;
 128 +                       clock-output-names = "apb1";
 129                 };
 130
 131 -               apb1_gates: apb1_gates@01c2006c {
 132 +               apb1_gates: clk@01c2006c {
 133                         #clock-cells = <1>;
 134                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 135                         reg = <0x01c2006c 0x4>;
 136 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 137 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 138 @@ -52,34 +52,38 @@
 139                         clock-frequency = <0>;
 140                 };
 141
 142 -               osc24M: osc24M@01c20050 {
 143 +               osc24M: clk@01c20050 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-osc-clk";
 146                         reg = <0x01c20050 0x4>;
 147                         clock-frequency = <24000000>;
 148 +                       clock-output-names = "osc24M";
 149                 };
 150
 151 -               osc32k: osc32k {
 152 +               osc32k: clk@0 {
 153                         #clock-cells = <0>;
 154                         compatible = "fixed-clock";
 155                         clock-frequency = <32768>;
 156 +                       clock-output-names = "osc32k";
 157                 };
 158
 159 -               pll1: pll1@01c20000 {
 160 +               pll1: clk@01c20000 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-pll1-clk";
 163                         reg = <0x01c20000 0x4>;
 164                         clocks = <&osc24M>;
 165 +                       clock-output-names = "pll1";
 166                 };
 167
 168 -               pll4: pll4@01c20018 {
 169 +               pll4: clk@01c20018 {
 170                         #clock-cells = <0>;
 171                         compatible = "allwinner,sun4i-pll1-clk";
 172                         reg = <0x01c20018 0x4>;
 173                         clocks = <&osc24M>;
 174 +                       clock-output-names = "pll4";
 175                 };
 176
 177 -               pll5: pll5@01c20020 {
 178 +               pll5: clk@01c20020 {
 179                         #clock-cells = <1>;
 180                         compatible = "allwinner,sun4i-pll5-clk";
 181                         reg = <0x01c20020 0x4>;
 182 @@ -87,7 +91,7 @@
 183                         clock-output-names = "pll5_ddr", "pll5_other";
 184                 };
 185
 186 -               pll6: pll6@01c20028 {
 187 +               pll6: clk@01c20028 {
 188                         #clock-cells = <1>;
 189                         compatible = "allwinner,sun4i-pll6-clk";
 190                         reg = <0x01c20028 0x4>;
 191 @@ -101,6 +105,7 @@
 192                         compatible = "allwinner,sun4i-cpu-clk";
 193                         reg = <0x01c20054 0x4>;
 194                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 195 +                       clock-output-names = "cpu";
 196                 };
 197
 198                 axi: axi@01c20054 {
 199 @@ -108,9 +113,10 @@
 200                         compatible = "allwinner,sun4i-axi-clk";
 201                         reg = <0x01c20054 0x4>;
 202                         clocks = <&cpu>;
 203 +                       clock-output-names = "axi";
 204                 };
 205
 206 -               axi_gates: axi_gates@01c2005c {
 207 +               axi_gates: clk@01c2005c {
 208                         #clock-cells = <1>;
 209                         compatible = "allwinner,sun4i-axi-gates-clk";
 210                         reg = <0x01c2005c 0x4>;
 211 @@ -123,9 +129,10 @@
 212                         compatible = "allwinner,sun4i-ahb-clk";
 213                         reg = <0x01c20054 0x4>;
 214                         clocks = <&axi>;
 215 +                       clock-output-names = "ahb";
 216                 };
 217
 218 -               ahb_gates: ahb_gates@01c20060 {
 219 +               ahb_gates: clk@01c20060 {
 220                         #clock-cells = <1>;
 221                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 222                         reg = <0x01c20060 0x8>;
 223 @@ -143,9 +150,10 @@
 224                         compatible = "allwinner,sun4i-apb0-clk";
 225                         reg = <0x01c20054 0x4>;
 226                         clocks = <&ahb>;
 227 +                       clock-output-names = "apb0";
 228                 };
 229
 230 -               apb0_gates: apb0_gates@01c20068 {
 231 +               apb0_gates: clk@01c20068 {
 232                         #clock-cells = <1>;
 233                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 234                         reg = <0x01c20068 0x4>;
 235 @@ -158,6 +166,7 @@
 236                         compatible = "allwinner,sun4i-apb1-mux-clk";
 237                         reg = <0x01c20058 0x4>;
 238                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 239 +                       clock-output-names = "apb1_mux";
 240                 };
 241
 242                 apb1: apb1@01c20058 {
 243 @@ -165,9 +174,10 @@
 244                         compatible = "allwinner,sun4i-apb1-clk";
 245                         reg = <0x01c20058 0x4>;
 246                         clocks = <&apb1_mux>;
 247 +                       clock-output-names = "apb1";
 248                 };
 249
 250 -               apb1_gates: apb1_gates@01c2006c {
 251 +               apb1_gates: clk@01c2006c {
 252                         #clock-cells = <1>;
 253                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 254                         reg = <0x01c2006c 0x4>;