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realtek: Add support for clause45 PHYs
[openwrt/staging/zorun.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7 extern struct rtl83xx_soc_info soc_info;
8
9 void rtl839x_print_matrix(void)
10 {
11 volatile u64 *ptr9;
12 int i;
13
14 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
15 for (i = 0; i < 52; i += 4)
16 pr_debug("> %16llx %16llx %16llx %16llx\n",
17 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
18 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
19 }
20
21 static inline int rtl839x_port_iso_ctrl(int p)
22 {
23 return RTL839X_PORT_ISO_CTRL(p);
24 }
25
26 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
27 {
28 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
29 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
30 }
31
32 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
33 {
34 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
35 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
36 }
37
38 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
39 {
40 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
41 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
42 }
43
44 static inline int rtl839x_tbl_access_data_0(int i)
45 {
46 return RTL839X_TBL_ACCESS_DATA_0(i);
47 }
48
49 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
50 {
51 u32 cmd;
52 u64 v;
53 u32 u, w;
54
55 cmd = 1 << 16 /* Execute cmd */
56 | 0 << 15 /* Read */
57 | 0 << 12 /* Table type 0b000 */
58 | (vlan & 0xfff);
59 rtl839x_exec_tbl0_cmd(cmd);
60
61 v = sw_r32(RTL839X_TBL_ACCESS_DATA_0(0));
62 v <<= 32;
63 u = sw_r32(RTL839X_TBL_ACCESS_DATA_0(1));
64 v |= u;
65 info->tagged_ports = v >> 11;
66
67 w = sw_r32(RTL839X_TBL_ACCESS_DATA_0(2));
68
69 info->profile_id = w >> 30 | ((u & 1) << 2);
70 info->hash_mc_fid = !!(u & 2);
71 info->hash_uc_fid = !!(u & 4);
72 info->fid = (u >> 3) & 0xff;
73
74 cmd = 1 << 15 /* Execute cmd */
75 | 0 << 14 /* Read */
76 | 0 << 12 /* Table type 0b00 */
77 | (vlan & 0xfff);
78 rtl839x_exec_tbl1_cmd(cmd);
79 v = sw_r32(RTL839X_TBL_ACCESS_DATA_1(0));
80 v <<= 32;
81 v |= sw_r32(RTL839X_TBL_ACCESS_DATA_1(1));
82 info->untagged_ports = v >> 11;
83 }
84
85 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
86 {
87 u32 cmd = BIT(16) /* Execute cmd */
88 | BIT(15) /* Write */
89 | 0 << 12 /* Table type 0b00 */
90 | (vlan & 0xfff);
91 u32 w;
92 u64 v = info->tagged_ports << 11;
93
94 v |= info->profile_id >> 2;
95 v |= info->hash_mc_fid ? 2 : 0;
96 v |= info->hash_uc_fid ? 4 : 0;
97 v |= ((u32)info->fid) << 3;
98 rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
99
100 w = info->profile_id;
101 sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
102 rtl839x_exec_tbl0_cmd(cmd);
103 }
104
105 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
106 {
107 u32 cmd = BIT(16) /* Execute cmd */
108 | BIT(15) /* Write */
109 | 0 << 12 /* Table type 0b00 */
110 | (vlan & 0xfff);
111 rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
112 rtl839x_exec_tbl1_cmd(cmd);
113 }
114
115 static inline int rtl839x_mac_force_mode_ctrl(int p)
116 {
117 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
118 }
119
120 static inline int rtl839x_mac_port_ctrl(int p)
121 {
122 return RTL839X_MAC_PORT_CTRL(p);
123 }
124
125 static inline int rtl839x_l2_port_new_salrn(int p)
126 {
127 return RTL839X_L2_PORT_NEW_SALRN(p);
128 }
129
130 static inline int rtl839x_l2_port_new_sa_fwd(int p)
131 {
132 return RTL839X_L2_PORT_NEW_SA_FWD(p);
133 }
134
135 static inline int rtl839x_mac_link_spd_sts(int p)
136 {
137 return RTL839X_MAC_LINK_SPD_STS(p);
138 }
139
140 static inline int rtl839x_trk_mbr_ctr(int group)
141 {
142 return RTL839X_TRK_MBR_CTR + (group << 3);
143 }
144
145 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
146 {
147 /* Table contains different entry types, we need to identify the right one:
148 * Check for MC entries, first
149 */
150 e->is_ip_mc = !!(r[2] & BIT(31));
151 e->is_ipv6_mc = !!(r[2] & BIT(30));
152 e->type = L2_INVALID;
153 if (!e->is_ip_mc) {
154 e->mac[0] = (r[0] >> 12);
155 e->mac[1] = (r[0] >> 4);
156 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
157 e->mac[3] = (r[1] >> 20);
158 e->mac[4] = (r[1] >> 12);
159 e->mac[5] = (r[1] >> 4);
160
161 /* Is it a unicast entry? check multicast bit */
162 if (!(e->mac[0] & 1)) {
163 e->is_static = !!((r[2] >> 18) & 1);
164 e->vid = (r[2] >> 4) & 0xfff;
165 e->rvid = (r[0] >> 20) & 0xfff;
166 e->port = (r[2] >> 24) & 0x3f;
167 e->block_da = !!(r[2] & (1 << 19));
168 e->block_sa = !!(r[2] & (1 << 20));
169 e->suspended = !!(r[2] & (1 << 17));
170 e->next_hop = !!(r[2] & (1 << 16));
171 if (e->next_hop)
172 pr_info("Found next hop entry, need to read data\n");
173 e->age = (r[2] >> 21) & 3;
174 e->valid = true;
175 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
176 e->valid = false;
177 else
178 e->type = L2_UNICAST;
179 } else {
180 e->valid = true;
181 e->type = L2_MULTICAST;
182 e->mc_portmask_index = (r[2]>>6) & 0xfff;
183 }
184 }
185 if (e->is_ip_mc) {
186 e->valid = true;
187 e->type = IP4_MULTICAST;
188 }
189 if (e->is_ipv6_mc) {
190 e->valid = true;
191 e->type = IP6_MULTICAST;
192 }
193 }
194
195 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
196 {
197 u64 entry;
198 u32 r[3];
199
200 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
201 u32 idx = (0 << 14) | (hash << 2) | position;
202
203 u32 cmd = 1 << 17 /* Execute cmd */
204 | 0 << 16 /* Read */
205 | 0 << 14 /* Table type 0b00 */
206 | (idx & 0x3fff);
207
208 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
209 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
210 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
211 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
212 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
213
214 rtl839x_fill_l2_entry(r, e);
215
216 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
217 return entry;
218 }
219
220 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
221 {
222 u64 entry;
223 u32 r[3];
224
225 u32 cmd = 1 << 17 /* Execute cmd */
226 | 0 << 16 /* Read */
227 | 1 << 14 /* Table type 0b01 */
228 | (idx & 0x3f);
229 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
230 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
231 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
232 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
233 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
234
235
236 rtl839x_fill_l2_entry(r, e);
237 if (e->valid)
238 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
239 else
240 return 0;
241
242 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
243 return entry;
244 }
245
246 static inline int rtl839x_vlan_profile(int profile)
247 {
248 return RTL839X_VLAN_PROFILE(profile);
249 }
250
251 static inline int rtl839x_vlan_port_egr_filter(int port)
252 {
253 return RTL839X_VLAN_PORT_EGR_FLTR(port);
254 }
255
256 static inline int rtl839x_vlan_port_igr_filter(int port)
257 {
258 return RTL839X_VLAN_PORT_IGR_FLTR(port);
259 }
260
261 u64 rtl839x_traffic_get(int source)
262 {
263 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
264 }
265
266 void rtl839x_traffic_set(int source, u64 dest_matrix)
267 {
268 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
269 }
270
271 void rtl839x_traffic_enable(int source, int dest)
272 {
273 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
274 }
275
276 void rtl839x_traffic_disable(int source, int dest)
277 {
278 rtl839x_mask_port_reg_be(BIT(dest), 0, rtl839x_port_iso_ctrl(source));
279 }
280
281 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
282 {
283 struct dsa_switch *ds = dev_id;
284 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
285 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
286 u64 link;
287 int i;
288
289 /* Clear status */
290 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
291 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
292
293 for (i = 0; i < 52; i++) {
294 if (ports & (1ULL << i)) {
295 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
296 if (link & (1ULL << i))
297 dsa_port_phylink_mac_change(ds, i, true);
298 else
299 dsa_port_phylink_mac_change(ds, i, false);
300 }
301 }
302 return IRQ_HANDLED;
303 }
304
305 // TODO: unused
306 int rtl8390_sds_power(int mac, int val)
307 {
308 u32 offset = (mac == 48) ? 0x0 : 0x100;
309 u32 mode = val ? 0 : 1;
310
311 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
312
313 if ((mac != 48) && (mac != 49)) {
314 pr_err("%s: not an SFP port: %d\n", __func__, mac);
315 return -1;
316 }
317
318 // Set bit 1003. 1000 starts at 7c
319 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
320
321 return 0;
322 }
323
324
325 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
326 {
327 u32 v;
328
329 if (port > 63 || page > 4095 || reg > 31)
330 return -ENOTSUPP;
331
332 mutex_lock(&smi_lock);
333
334 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
335 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
336 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
337
338 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
339
340 v |= 1;
341 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
342
343 do {
344 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
345
346 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
347
348 mutex_unlock(&smi_lock);
349 return 0;
350 }
351
352 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
353 {
354 u32 v;
355 int err = 0;
356
357 val &= 0xffff;
358 if (port > 63 || page > 4095 || reg > 31)
359 return -ENOTSUPP;
360
361 mutex_lock(&smi_lock);
362
363 // Set PHY to access
364 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
365
366 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
367
368 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
369 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
370
371 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
372
373 v |= BIT(3) | 1; /* Write operation and execute */
374 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
375
376 do {
377 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
378
379 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
380 err = -EIO;
381
382 mutex_unlock(&smi_lock);
383 return err;
384 }
385
386 /*
387 * Read an mmd register of the PHY
388 */
389 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
390 {
391 int err = 0;
392 u32 v;
393
394 mutex_lock(&smi_lock);
395
396 // Set PHY to access
397 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
398
399 // Set MMD device number and register to write to
400 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
401
402 v = BIT(2) | BIT(0); // MMD-access | EXEC
403 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
404
405 do {
406 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
407 } while (v & BIT(0));
408 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
409 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
410 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
411
412 mutex_unlock(&smi_lock);
413
414 return err;
415 }
416
417 /*
418 * Write to an mmd register of the PHY
419 */
420 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
421 {
422 int err = 0;
423 u32 v;
424
425 mutex_lock(&smi_lock);
426
427 // Set PHY to access
428 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
429
430 // Set data to write
431 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
432
433 // Set MMD device number and register to write to
434 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
435
436 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
437 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
438
439 do {
440 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
441 } while (v & BIT(0));
442
443 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
444 mutex_unlock(&smi_lock);
445 return err;
446 }
447
448 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
449 {
450 u32 info;
451
452 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
453 info = sw_r32(RTL839X_CHIP_INFO);
454 pr_debug("Chip-Info: %x\n", info);
455 priv->version = RTL8390_VERSION_A;
456 }
457
458 u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
459 {
460 u32 h1, h2, h;
461
462 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
463 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
464 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
465 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
466 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
467 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
468 ^ (seed & 0x3f));
469 h = (h1 << 6) | h2;
470 } else {
471 h = (seed >> 60)
472 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
473 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
474 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
475 }
476
477 return h;
478 }
479
480 void rtl839x_vlan_profile_dump(int index)
481 {
482 u32 profile, profile1;
483
484 if (index < 0 || index > 7)
485 return;
486
487 profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
488 profile = sw_r32(RTL839X_VLAN_PROFILE(index));
489
490 pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
491 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
492 index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
493 (profile1) & 0xfff);
494 }
495
496 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
497 {
498 int i;
499 u32 cmd = 1 << 16 /* Execute cmd */
500 | 0 << 15 /* Read */
501 | 5 << 12 /* Table type 0b101 */
502 | (msti & 0xfff);
503 priv->r->exec_tbl0_cmd(cmd);
504
505 for (i = 0; i < 4; i++)
506 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
507 }
508
509 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
510 {
511 int i;
512 u32 cmd = 1 << 16 /* Execute cmd */
513 | 1 << 15 /* Write */
514 | 5 << 12 /* Table type 0b101 */
515 | (msti & 0xfff);
516 for (i = 0; i < 4; i++)
517 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
518 priv->r->exec_tbl0_cmd(cmd);
519 }
520
521 /*
522 * Enables or disables the EEE/EEEP capability of a port
523 */
524 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
525 {
526 u32 v;
527
528 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
529 if (port >= 48)
530 return;
531
532 enable = true;
533 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
534 v = enable ? 0xf : 0x0;
535
536 // Set EEE for 100, 500, 1000MBit and 10GBit
537 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
538
539 // Set TX/RX EEE state
540 v = enable ? 0x3 : 0x0;
541 sw_w32(v, RTL839X_EEE_CTRL(port));
542
543 priv->ports[port].eee_enabled = enable;
544 }
545
546 /*
547 * Get EEE own capabilities and negotiation result
548 */
549 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
550 {
551 u64 link, a;
552
553 if (port >= 48)
554 return 0;
555
556 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
557 if (!(link & BIT_ULL(port)))
558 return 0;
559
560 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
561 e->advertised |= ADVERTISED_100baseT_Full;
562
563 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
564 e->advertised |= ADVERTISED_1000baseT_Full;
565
566 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
567 pr_info("Link partner: %016llx\n", a);
568 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
569 e->lp_advertised = ADVERTISED_100baseT_Full;
570 e->lp_advertised |= ADVERTISED_1000baseT_Full;
571 return 1;
572 }
573
574 return 0;
575 }
576
577 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
578 {
579 int i;
580
581 pr_info("Setting up EEE, state: %d\n", enable);
582
583 // Set wake timer for TX and pause timer both to 0x21
584 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
585 // Set pause wake timer for GIGA-EEE to 0x11
586 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
587 // Set pause wake timer for 10GBit ports to 0x11
588 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
589
590 // Setup EEE on all ports
591 for (i = 0; i < priv->cpu_port; i++) {
592 if (priv->ports[i].phy)
593 rtl839x_port_eee_set(priv, i, enable);
594 }
595 priv->eee_enabled = enable;
596 }
597
598 const struct rtl838x_reg rtl839x_reg = {
599 .mask_port_reg_be = rtl839x_mask_port_reg_be,
600 .set_port_reg_be = rtl839x_set_port_reg_be,
601 .get_port_reg_be = rtl839x_get_port_reg_be,
602 .mask_port_reg_le = rtl839x_mask_port_reg_le,
603 .set_port_reg_le = rtl839x_set_port_reg_le,
604 .get_port_reg_le = rtl839x_get_port_reg_le,
605 .stat_port_rst = RTL839X_STAT_PORT_RST,
606 .stat_rst = RTL839X_STAT_RST,
607 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
608 .traffic_enable = rtl839x_traffic_enable,
609 .traffic_disable = rtl839x_traffic_disable,
610 .traffic_get = rtl839x_traffic_get,
611 .traffic_set = rtl839x_traffic_set,
612 .port_iso_ctrl = rtl839x_port_iso_ctrl,
613 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
614 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
615 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
616 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
617 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
618 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
619 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
620 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
621 .isr_glb_src = RTL839X_ISR_GLB_SRC,
622 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
623 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
624 .imr_glb = RTL839X_IMR_GLB,
625 .vlan_tables_read = rtl839x_vlan_tables_read,
626 .vlan_set_tagged = rtl839x_vlan_set_tagged,
627 .vlan_set_untagged = rtl839x_vlan_set_untagged,
628 .vlan_profile_dump = rtl839x_vlan_profile_dump,
629 .stp_get = rtl839x_stp_get,
630 .stp_set = rtl839x_stp_set,
631 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
632 .mac_port_ctrl = rtl839x_mac_port_ctrl,
633 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
634 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
635 .mir_ctrl = RTL839X_MIR_CTRL,
636 .mir_dpm = RTL839X_MIR_DPM_CTRL,
637 .mir_spm = RTL839X_MIR_SPM_CTRL,
638 .mac_link_sts = RTL839X_MAC_LINK_STS,
639 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
640 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
641 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
642 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
643 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
644 .read_cam = rtl839x_read_cam,
645 .vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR(0),
646 .vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR(0),
647 .vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
648 .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
649 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
650 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
651 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
652 .init_eee = rtl839x_init_eee,
653 .port_eee_set = rtl839x_port_eee_set,
654 .eee_port_ability = rtl839x_eee_port_ability,
655 };
Staging tree of Baptiste Jonglez