--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_PHYS_TO_DMA=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_MODULE_PLTS=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
+CONFIG_ARM_QCOM_CPUIDLE=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+# CONFIG_DWMAC_GENERIC is not set
+CONFIG_DWMAC_IPQ806X=y
+# CONFIG_DWMAC_QCOM_ETHQOS is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PCI=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=100
+CONFIG_HZ_100=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPQ_GCC_4019 is not set
+CONFIG_IPQ_GCC_806X=y
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_KPSS_XCC=y
+CONFIG_KRAITCC=y
+CONFIG_KRAIT_CLOCKS=y
+CONFIG_KRAIT_L2_ACCESSORS=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ8064=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_QCOM_RPM=y
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_QCOM_DML=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSM_GCC_8660=y
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_IOMMU is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_QCOM_SMEM_PARTS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K=y
+CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+CONFIG_PHY_QCOM_IPQ806X_SATA=y
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_UFS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+# CONFIG_PINCTRL_IPQ4019 is not set
+CONFIG_PINCTRL_IPQ8064=y
+# CONFIG_PINCTRL_IPQ8074 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_MSM8998 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_QCS404 is not set
+# CONFIG_PINCTRL_SC7180 is not set
+# CONFIG_PINCTRL_SDM660 is not set
+# CONFIG_PINCTRL_SDM845 is not set
+# CONFIG_PINCTRL_SM8150 is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_QCOM_A53PLL is not set
+CONFIG_QCOM_ADM=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_CLK_RPM=y
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GENI_SE is not set
+CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_HFPLL=y
+# CONFIG_QCOM_IOMMU is not set
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_PDC is not set
+CONFIG_QCOM_PM=y
+CONFIG_QCOM_QFPROM=y
+# CONFIG_QCOM_RMTFS_MEM is not set
+CONFIG_QCOM_RPMCC=y
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SCM_32=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMSM is not set
+# CONFIG_QCOM_SOCINFO is not set
+CONFIG_QCOM_TCSR=y
+CONFIG_QCOM_TSENS=y
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+# CONFIG_QRTR is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REFCOUNT_FULL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_QCOM_RPM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SM_GCC_8150 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001
+From: Thomas Pedersen <twp@codeaurora.org>
+Date: Mon, 16 May 2016 17:58:50 -0700
+Subject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers
+
+Original patch from Andy Gross.
+
+This patch removes the crci information from the dma
+channel property. At least one client device requires
+using more than one CRCI value for a channel. This does
+not match the current binding and the crci information
+needs to be removed.
+
+Instead, the client device will provide this information
+via other means.
+
+Signed-off-by: Andy Gross <agross@codeaurora.org>
+Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
+---
+ Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++----------
+ 1 file changed, 6 insertions(+), 10 deletions(-)
+
+--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
++++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
+@@ -4,8 +4,7 @@ Required properties:
+ - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
+ - reg: Address range for DMA registers
+ - interrupts: Should contain one interrupt shared by all channels
+-- #dma-cells: must be <2>. First cell denotes the channel number. Second cell
+- denotes CRCI (client rate control interface) flow control assignment.
++- #dma-cells: must be <1>. First cell denotes the channel number.
+ - clocks: Should contain the core clock and interface clock.
+ - clock-names: Must contain "core" for the core clock and "iface" for the
+ interface clock.
+@@ -22,7 +21,7 @@ Example:
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <0 170 0>;
+- #dma-cells = <2>;
++ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+@@ -35,15 +34,12 @@ Example:
+ qcom,ee = <0>;
+ };
+
+-DMA clients must use the format descripted in the dma.txt file, using a three
++DMA clients must use the format descripted in the dma.txt file, using a two
+ cell specifier for each channel.
+
+-Each dmas request consists of 3 cells:
++Each dmas request consists of two cells:
+ 1. phandle pointing to the DMA controller
+ 2. channel number
+- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
+- The CRCI is used for flow control. It identifies the peripheral device that
+- is the source/destination for the transferred data.
+
+ Example:
+
+@@ -55,7 +51,7 @@ Example:
+
+ cs-gpios = <&qcom_pinmux 20 0>;
+
+- dmas = <&adm_dma 6 9>,
+- <&adm_dma 5 10>;
++ dmas = <&adm_dma 6>,
++ <&adm_dma 5>;
+ dma-names = "rx", "tx";
+ };
--- /dev/null
+From 563fa24db4e529c5a3311928d73a8a90531ee527 Mon Sep 17 00:00:00 2001
+From: Thomas Pedersen <twp@codeaurora.org>
+Date: Mon, 16 May 2016 17:58:51 -0700
+Subject: [PATCH 02/69] dmaengine: Add ADM driver
+
+Original patch by Andy Gross.
+
+Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
+controller found in the MSM8x60 and IPQ/APQ8064 platforms.
+
+The ADM supports both memory to memory transactions and memory
+to/from peripheral device transactions. The controller also provides flow
+control capabilities for transactions to/from peripheral devices.
+
+The initial release of this driver supports slave transfers to/from peripherals
+and also incorporates CRCI (client rate control interface) flow control.
+
+Signed-off-by: Andy Gross <agross@codeaurora.org>
+Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
+---
+ drivers/dma/qcom/Kconfig | 10 +
+ drivers/dma/qcom/Makefile | 1 +
+ drivers/dma/qcom/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 911 insertions(+)
+ create mode 100644 drivers/dma/qcom/qcom_adm.c
+
+--- a/drivers/dma/qcom/Kconfig
++++ b/drivers/dma/qcom/Kconfig
+@@ -28,3 +28,13 @@ config QCOM_HIDMA
+ (user to kernel, kernel to kernel, etc.). It only supports
+ memcpy interface. The core is not intended for general
+ purpose slave DMA.
++
++config QCOM_ADM
++ tristate "Qualcomm ADM support"
++ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
++ ---help---
++ Enable support for the Qualcomm ADM DMA controller. This controller
++ provides DMA capabilities for both general purpose and on-chip
++ peripheral devices.
+--- a/drivers/dma/qcom/Makefile
++++ b/drivers/dma/qcom/Makefile
+@@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mg
+ hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o
+ obj-$(CONFIG_QCOM_HIDMA) += hdma.o
+ hdma-objs := hidma_ll.o hidma.o hidma_dbg.o
++obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
+--- /dev/null
++++ b/drivers/dma/qcom/qcom_adm.c
+@@ -0,0 +1,914 @@
++/*
++ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/scatterlist.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of_dma.h>
++#include <linux/reset.h>
++#include <linux/clk.h>
++#include <linux/dmaengine.h>
++
++#include "../dmaengine.h"
++#include "../virt-dma.h"
++
++/* ADM registers - calculated from channel number and security domain */
++#define ADM_CHAN_MULTI 0x4
++#define ADM_CI_MULTI 0x4
++#define ADM_CRCI_MULTI 0x4
++#define ADM_EE_MULTI 0x800
++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan)
++#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * ee)
++#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan)
++#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci))
++#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee))
++#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
++#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
++#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
++#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan))
++#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
++#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee))
++#define ADM_CI_CONF(ci) (0x390 + ci * ADM_CI_MULTI)
++#define ADM_GP_CTL 0x3d8
++#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \
++ ADM_EE_OFFS(ee))
++
++/* channel status */
++#define ADM_CH_STATUS_VALID BIT(1)
++
++/* channel result */
++#define ADM_CH_RSLT_VALID BIT(31)
++#define ADM_CH_RSLT_ERR BIT(3)
++#define ADM_CH_RSLT_FLUSH BIT(2)
++#define ADM_CH_RSLT_TPD BIT(1)
++
++/* channel conf */
++#define ADM_CH_CONF_SHADOW_EN BIT(12)
++#define ADM_CH_CONF_MPU_DISABLE BIT(11)
++#define ADM_CH_CONF_PERM_MPU_CONF BIT(9)
++#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7)
++#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee & 0x3) << 4) | ((ee & 0x4) << 11))
++
++/* channel result conf */
++#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1)
++#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0)
++
++/* CRCI CTL */
++#define ADM_CRCI_CTL_MUX_SEL BIT(18)
++#define ADM_CRCI_CTL_RST BIT(17)
++
++/* CI configuration */
++#define ADM_CI_RANGE_END(x) (x << 24)
++#define ADM_CI_RANGE_START(x) (x << 16)
++#define ADM_CI_BURST_4_WORDS BIT(2)
++#define ADM_CI_BURST_8_WORDS BIT(3)
++
++/* GP CTL */
++#define ADM_GP_CTL_LP_EN BIT(12)
++#define ADM_GP_CTL_LP_CNT(x) (x << 8)
++
++/* Command pointer list entry */
++#define ADM_CPLE_LP BIT(31)
++#define ADM_CPLE_CMD_PTR_LIST BIT(29)
++
++/* Command list entry */
++#define ADM_CMD_LC BIT(31)
++#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7)
++#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3)
++
++#define ADM_CMD_TYPE_SINGLE 0x0
++#define ADM_CMD_TYPE_BOX 0x3
++
++#define ADM_CRCI_MUX_SEL BIT(4)
++#define ADM_DESC_ALIGN 8
++#define ADM_MAX_XFER (SZ_64K-1)
++#define ADM_MAX_ROWS (SZ_64K-1)
++#define ADM_MAX_CHANNELS 16
++
++struct adm_desc_hw_box {
++ u32 cmd;
++ u32 src_addr;
++ u32 dst_addr;
++ u32 row_len;
++ u32 num_rows;
++ u32 row_offset;
++};
++
++struct adm_desc_hw_single {
++ u32 cmd;
++ u32 src_addr;
++ u32 dst_addr;
++ u32 len;
++};
++
++struct adm_async_desc {
++ struct virt_dma_desc vd;
++ struct adm_device *adev;
++
++ size_t length;
++ enum dma_transfer_direction dir;
++ dma_addr_t dma_addr;
++ size_t dma_len;
++
++ void *cpl;
++ dma_addr_t cp_addr;
++ u32 crci;
++ u32 mux;
++ u32 blk_size;
++};
++
++struct adm_chan {
++ struct virt_dma_chan vc;
++ struct adm_device *adev;
++
++ /* parsed from DT */
++ u32 id; /* channel id */
++
++ struct adm_async_desc *curr_txd;
++ struct dma_slave_config slave;
++ struct list_head node;
++
++ int error;
++ int initialized;
++};
++
++static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
++{
++ return container_of(common, struct adm_chan, vc.chan);
++}
++
++struct adm_device {
++ void __iomem *regs;
++ struct device *dev;
++ struct dma_device common;
++ struct device_dma_parameters dma_parms;
++ struct adm_chan *channels;
++
++ u32 ee;
++
++ struct clk *core_clk;
++ struct clk *iface_clk;
++
++ struct reset_control *clk_reset;
++ struct reset_control *c0_reset;
++ struct reset_control *c1_reset;
++ struct reset_control *c2_reset;
++ int irq;
++};
++
++/**
++ * adm_free_chan - Frees dma resources associated with the specific channel
++ *
++ * Free all allocated descriptors associated with this channel
++ *
++ */
++static void adm_free_chan(struct dma_chan *chan)
++{
++ /* free all queued descriptors */
++ vchan_free_chan_resources(to_virt_chan(chan));
++}
++
++/**
++ * adm_get_blksize - Get block size from burst value
++ *
++ */
++static int adm_get_blksize(unsigned int burst)
++{
++ int ret;
++
++ switch (burst) {
++ case 16:
++ case 32:
++ case 64:
++ case 128:
++ ret = ffs(burst>>4) - 1;
++ break;
++ case 192:
++ ret = 4;
++ break;
++ case 256:
++ ret = 5;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/**
++ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
++ *
++ * @achan: ADM channel
++ * @desc: Descriptor memory pointer
++ * @sg: Scatterlist entry
++ * @crci: CRCI value
++ * @burst: Burst size of transaction
++ * @direction: DMA transfer direction
++ */
++static void *adm_process_fc_descriptors(struct adm_chan *achan,
++ void *desc, struct scatterlist *sg, u32 crci, u32 burst,
++ enum dma_transfer_direction direction)
++{
++ struct adm_desc_hw_box *box_desc = NULL;
++ struct adm_desc_hw_single *single_desc;
++ u32 remainder = sg_dma_len(sg);
++ u32 rows, row_offset, crci_cmd;
++ u32 mem_addr = sg_dma_address(sg);
++ u32 *incr_addr = &mem_addr;
++ u32 *src, *dst;
++
++ if (direction == DMA_DEV_TO_MEM) {
++ crci_cmd = ADM_CMD_SRC_CRCI(crci);
++ row_offset = burst;
++ src = &achan->slave.src_addr;
++ dst = &mem_addr;
++ } else {
++ crci_cmd = ADM_CMD_DST_CRCI(crci);
++ row_offset = burst << 16;
++ src = &mem_addr;
++ dst = &achan->slave.dst_addr;
++ }
++
++ while (remainder >= burst) {
++ box_desc = desc;
++ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
++ box_desc->row_offset = row_offset;
++ box_desc->src_addr = *src;
++ box_desc->dst_addr = *dst;
++
++ rows = remainder / burst;
++ rows = min_t(u32, rows, ADM_MAX_ROWS);
++ box_desc->num_rows = rows << 16 | rows;
++ box_desc->row_len = burst << 16 | burst;
++
++ *incr_addr += burst * rows;
++ remainder -= burst * rows;
++ desc += sizeof(*box_desc);
++ }
++
++ /* if leftover bytes, do one single descriptor */
++ if (remainder) {
++ single_desc = desc;
++ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
++ single_desc->len = remainder;
++ single_desc->src_addr = *src;
++ single_desc->dst_addr = *dst;
++ desc += sizeof(*single_desc);
++
++ if (sg_is_last(sg))
++ single_desc->cmd |= ADM_CMD_LC;
++ } else {
++ if (box_desc && sg_is_last(sg))
++ box_desc->cmd |= ADM_CMD_LC;
++ }
++
++ return desc;
++}
++
++/**
++ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
++ *
++ * @achan: ADM channel
++ * @desc: Descriptor memory pointer
++ * @sg: Scatterlist entry
++ * @direction: DMA transfer direction
++ */
++static void *adm_process_non_fc_descriptors(struct adm_chan *achan,
++ void *desc, struct scatterlist *sg,
++ enum dma_transfer_direction direction)
++{
++ struct adm_desc_hw_single *single_desc;
++ u32 remainder = sg_dma_len(sg);
++ u32 mem_addr = sg_dma_address(sg);
++ u32 *incr_addr = &mem_addr;
++ u32 *src, *dst;
++
++ if (direction == DMA_DEV_TO_MEM) {
++ src = &achan->slave.src_addr;
++ dst = &mem_addr;
++ } else {
++ src = &mem_addr;
++ dst = &achan->slave.dst_addr;
++ }
++
++ do {
++ single_desc = desc;
++ single_desc->cmd = ADM_CMD_TYPE_SINGLE;
++ single_desc->src_addr = *src;
++ single_desc->dst_addr = *dst;
++ single_desc->len = (remainder > ADM_MAX_XFER) ?
++ ADM_MAX_XFER : remainder;
++
++ remainder -= single_desc->len;
++ *incr_addr += single_desc->len;
++ desc += sizeof(*single_desc);
++ } while (remainder);
++
++ /* set last command if this is the end of the whole transaction */
++ if (sg_is_last(sg))
++ single_desc->cmd |= ADM_CMD_LC;
++
++ return desc;
++}
++
++/**
++ * adm_prep_slave_sg - Prep slave sg transaction
++ *
++ * @chan: dma channel
++ * @sgl: scatter gather list
++ * @sg_len: length of sg
++ * @direction: DMA transfer direction
++ * @flags: DMA flags
++ * @context: transfer context (unused)
++ */
++static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
++ struct scatterlist *sgl, unsigned int sg_len,
++ enum dma_transfer_direction direction, unsigned long flags,
++ void *context)
++{
++ struct adm_chan *achan = to_adm_chan(chan);
++ struct adm_device *adev = achan->adev;
++ struct adm_async_desc *async_desc;
++ struct scatterlist *sg;
++ dma_addr_t cple_addr;
++ u32 i, burst;
++ u32 single_count = 0, box_count = 0, crci = 0;
++ void *desc;
++ u32 *cple;
++ int blk_size = 0;
++
++ if (!is_slave_direction(direction)) {
++ dev_err(adev->dev, "invalid dma direction\n");
++ return NULL;
++ }
++
++ /*
++ * get burst value from slave configuration
++ */
++ burst = (direction == DMA_MEM_TO_DEV) ?
++ achan->slave.dst_maxburst :
++ achan->slave.src_maxburst;
++
++ /* if using flow control, validate burst and crci values */
++ if (achan->slave.device_fc) {
++
++ blk_size = adm_get_blksize(burst);
++ if (blk_size < 0) {
++ dev_err(adev->dev, "invalid burst value: %d\n",
++ burst);
++ return ERR_PTR(-EINVAL);
++ }
++
++ crci = achan->slave.slave_id & 0xf;
++ if (!crci || achan->slave.slave_id > 0x1f) {
++ dev_err(adev->dev, "invalid crci value\n");
++ return ERR_PTR(-EINVAL);
++ }
++ }
++
++ /* iterate through sgs and compute allocation size of structures */
++ for_each_sg(sgl, sg, sg_len, i) {
++ if (achan->slave.device_fc) {
++ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
++ ADM_MAX_ROWS);
++ if (sg_dma_len(sg) % burst)
++ single_count++;
++ } else {
++ single_count += DIV_ROUND_UP(sg_dma_len(sg),
++ ADM_MAX_XFER);
++ }
++ }
++
++ async_desc = kzalloc(sizeof(*async_desc), GFP_ATOMIC);
++ if (!async_desc)
++ return ERR_PTR(-ENOMEM);
++
++ if (crci)
++ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
++ ADM_CRCI_CTL_MUX_SEL : 0;
++ async_desc->crci = crci;
++ async_desc->blk_size = blk_size;
++ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
++ box_count * sizeof(struct adm_desc_hw_box) +
++ sizeof(*cple) + 2 * ADM_DESC_ALIGN;
++
++ async_desc->cpl = kzalloc(async_desc->dma_len, GFP_ATOMIC);
++ if (!async_desc->cpl)
++ goto free;
++
++ async_desc->adev = adev;
++
++ /* both command list entry and descriptors must be 8 byte aligned */
++ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
++ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
++
++ for_each_sg(sgl, sg, sg_len, i) {
++ async_desc->length += sg_dma_len(sg);
++
++ if (achan->slave.device_fc)
++ desc = adm_process_fc_descriptors(achan, desc, sg, crci,
++ burst, direction);
++ else
++ desc = adm_process_non_fc_descriptors(achan, desc, sg,
++ direction);
++ }
++
++ async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl,
++ async_desc->dma_len,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(adev->dev, async_desc->dma_addr))
++ goto free;
++
++ cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl);
++
++ /* init cmd list */
++ dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple),
++ DMA_TO_DEVICE);
++ *cple = ADM_CPLE_LP;
++ *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3;
++ dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple),
++ DMA_TO_DEVICE);
++
++ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
++
++free:
++ kfree(async_desc);
++ return ERR_PTR(-ENOMEM);
++}
++
++/**
++ * adm_terminate_all - terminate all transactions on a channel
++ * @achan: adm dma channel
++ *
++ * Dequeues and frees all transactions, aborts current transaction
++ * No callbacks are done
++ *
++ */
++static int adm_terminate_all(struct dma_chan *chan)
++{
++ struct adm_chan *achan = to_adm_chan(chan);
++ struct adm_device *adev = achan->adev;
++ unsigned long flags;
++ LIST_HEAD(head);
++
++ spin_lock_irqsave(&achan->vc.lock, flags);
++ vchan_get_all_descriptors(&achan->vc, &head);
++
++ /* send flush command to terminate current transaction */
++ writel_relaxed(0x0,
++ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
++
++ spin_unlock_irqrestore(&achan->vc.lock, flags);
++
++ vchan_dma_desc_free_list(&achan->vc, &head);
++
++ return 0;
++}
++
++static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
++{
++ struct adm_chan *achan = to_adm_chan(chan);
++ unsigned long flag;
++
++ spin_lock_irqsave(&achan->vc.lock, flag);
++ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
++ spin_unlock_irqrestore(&achan->vc.lock, flag);
++
++ return 0;
++}
++
++/**
++ * adm_start_dma - start next transaction
++ * @achan - ADM dma channel
++ */
++static void adm_start_dma(struct adm_chan *achan)
++{
++ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
++ struct adm_device *adev = achan->adev;
++ struct adm_async_desc *async_desc;
++
++ lockdep_assert_held(&achan->vc.lock);
++
++ if (!vd)
++ return;
++
++ list_del(&vd->node);
++
++ /* write next command list out to the CMD FIFO */
++ async_desc = container_of(vd, struct adm_async_desc, vd);
++ achan->curr_txd = async_desc;
++
++ /* reset channel error */
++ achan->error = 0;
++
++ if (!achan->initialized) {
++ /* enable interrupts */
++ writel(ADM_CH_CONF_SHADOW_EN |
++ ADM_CH_CONF_PERM_MPU_CONF |
++ ADM_CH_CONF_MPU_DISABLE |
++ ADM_CH_CONF_SEC_DOMAIN(adev->ee),
++ adev->regs + ADM_CH_CONF(achan->id));
++
++ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
++ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
++
++ achan->initialized = 1;
++ }
++
++ /* set the crci block size if this transaction requires CRCI */
++ if (async_desc->crci) {
++ writel(async_desc->mux | async_desc->blk_size,
++ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
++ }
++
++ /* make sure IRQ enable doesn't get reordered */
++ wmb();
++
++ /* write next command list out to the CMD FIFO */
++ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
++ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
++}
++
++/**
++ * adm_dma_irq - irq handler for ADM controller
++ * @irq: IRQ of interrupt
++ * @data: callback data
++ *
++ * IRQ handler for the bam controller
++ */
++static irqreturn_t adm_dma_irq(int irq, void *data)
++{
++ struct adm_device *adev = data;
++ u32 srcs, i;
++ struct adm_async_desc *async_desc;
++ unsigned long flags;
++
++ srcs = readl_relaxed(adev->regs +
++ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
++
++ for (i = 0; i < ADM_MAX_CHANNELS; i++) {
++ struct adm_chan *achan = &adev->channels[i];
++ u32 status, result;
++
++ if (srcs & BIT(i)) {
++ status = readl_relaxed(adev->regs +
++ ADM_CH_STATUS_SD(i, adev->ee));
++
++ /* if no result present, skip */
++ if (!(status & ADM_CH_STATUS_VALID))
++ continue;
++
++ result = readl_relaxed(adev->regs +
++ ADM_CH_RSLT(i, adev->ee));
++
++ /* no valid results, skip */
++ if (!(result & ADM_CH_RSLT_VALID))
++ continue;
++
++ /* flag error if transaction was flushed or failed */
++ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
++ achan->error = 1;
++
++ spin_lock_irqsave(&achan->vc.lock, flags);
++ async_desc = achan->curr_txd;
++
++ achan->curr_txd = NULL;
++
++ if (async_desc) {
++ vchan_cookie_complete(&async_desc->vd);
++
++ /* kick off next DMA */
++ adm_start_dma(achan);
++ }
++
++ spin_unlock_irqrestore(&achan->vc.lock, flags);
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++/**
++ * adm_tx_status - returns status of transaction
++ * @chan: dma channel
++ * @cookie: transaction cookie
++ * @txstate: DMA transaction state
++ *
++ * Return status of dma transaction
++ */
++static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
++ struct dma_tx_state *txstate)
++{
++ struct adm_chan *achan = to_adm_chan(chan);
++ struct virt_dma_desc *vd;
++ enum dma_status ret;
++ unsigned long flags;
++ size_t residue = 0;
++
++ ret = dma_cookie_status(chan, cookie, txstate);
++ if (ret == DMA_COMPLETE || !txstate)
++ return ret;
++
++ spin_lock_irqsave(&achan->vc.lock, flags);
++
++ vd = vchan_find_desc(&achan->vc, cookie);
++ if (vd)
++ residue = container_of(vd, struct adm_async_desc, vd)->length;
++
++ spin_unlock_irqrestore(&achan->vc.lock, flags);
++
++ /*
++ * residue is either the full length if it is in the issued list, or 0
++ * if it is in progress. We have no reliable way of determining
++ * anything inbetween
++ */
++ dma_set_residue(txstate, residue);
++
++ if (achan->error)
++ return DMA_ERROR;
++
++ return ret;
++}
++
++/**
++ * adm_issue_pending - starts pending transactions
++ * @chan: dma channel
++ *
++ * Issues all pending transactions and starts DMA
++ */
++static void adm_issue_pending(struct dma_chan *chan)
++{
++ struct adm_chan *achan = to_adm_chan(chan);
++ unsigned long flags;
++
++ spin_lock_irqsave(&achan->vc.lock, flags);
++
++ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
++ adm_start_dma(achan);
++ spin_unlock_irqrestore(&achan->vc.lock, flags);
++}
++
++/**
++ * adm_dma_free_desc - free descriptor memory
++ * @vd: virtual descriptor
++ *
++ */
++static void adm_dma_free_desc(struct virt_dma_desc *vd)
++{
++ struct adm_async_desc *async_desc = container_of(vd,
++ struct adm_async_desc, vd);
++
++ dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr,
++ async_desc->dma_len, DMA_TO_DEVICE);
++ kfree(async_desc->cpl);
++ kfree(async_desc);
++}
++
++static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
++ u32 index)
++{
++ achan->id = index;
++ achan->adev = adev;
++
++ vchan_init(&achan->vc, &adev->common);
++ achan->vc.desc_free = adm_dma_free_desc;
++}
++
++static int adm_dma_probe(struct platform_device *pdev)
++{
++ struct adm_device *adev;
++ struct resource *iores;
++ int ret;
++ u32 i;
++
++ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
++ if (!adev)
++ return -ENOMEM;
++
++ adev->dev = &pdev->dev;
++
++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ adev->regs = devm_ioremap_resource(&pdev->dev, iores);
++ if (IS_ERR(adev->regs))
++ return PTR_ERR(adev->regs);
++
++ adev->irq = platform_get_irq(pdev, 0);
++ if (adev->irq < 0)
++ return adev->irq;
++
++ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
++ if (ret) {
++ dev_err(adev->dev, "Execution environment unspecified\n");
++ return ret;
++ }
++
++ adev->core_clk = devm_clk_get(adev->dev, "core");
++ if (IS_ERR(adev->core_clk))
++ return PTR_ERR(adev->core_clk);
++
++ ret = clk_prepare_enable(adev->core_clk);
++ if (ret) {
++ dev_err(adev->dev, "failed to prepare/enable core clock\n");
++ return ret;
++ }
++
++ adev->iface_clk = devm_clk_get(adev->dev, "iface");
++ if (IS_ERR(adev->iface_clk)) {
++ ret = PTR_ERR(adev->iface_clk);
++ goto err_disable_core_clk;
++ }
++
++ ret = clk_prepare_enable(adev->iface_clk);
++ if (ret) {
++ dev_err(adev->dev, "failed to prepare/enable iface clock\n");
++ goto err_disable_core_clk;
++ }
++
++ adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk");
++ if (IS_ERR(adev->clk_reset)) {
++ dev_err(adev->dev, "failed to get ADM0 reset\n");
++ ret = PTR_ERR(adev->clk_reset);
++ goto err_disable_clks;
++ }
++
++ adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0");
++ if (IS_ERR(adev->c0_reset)) {
++ dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
++ ret = PTR_ERR(adev->c0_reset);
++ goto err_disable_clks;
++ }
++
++ adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1");
++ if (IS_ERR(adev->c1_reset)) {
++ dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
++ ret = PTR_ERR(adev->c1_reset);
++ goto err_disable_clks;
++ }
++
++ adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2");
++ if (IS_ERR(adev->c2_reset)) {
++ dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
++ ret = PTR_ERR(adev->c2_reset);
++ goto err_disable_clks;
++ }
++
++ reset_control_assert(adev->clk_reset);
++ reset_control_assert(adev->c0_reset);
++ reset_control_assert(adev->c1_reset);
++ reset_control_assert(adev->c2_reset);
++
++ reset_control_deassert(adev->clk_reset);
++ reset_control_deassert(adev->c0_reset);
++ reset_control_deassert(adev->c1_reset);
++ reset_control_deassert(adev->c2_reset);
++
++ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
++ sizeof(*adev->channels), GFP_KERNEL);
++
++ if (!adev->channels) {
++ ret = -ENOMEM;
++ goto err_disable_clks;
++ }
++
++ /* allocate and initialize channels */
++ INIT_LIST_HEAD(&adev->common.channels);
++
++ for (i = 0; i < ADM_MAX_CHANNELS; i++)
++ adm_channel_init(adev, &adev->channels[i], i);
++
++ /* reset CRCIs */
++ for (i = 0; i < 16; i++)
++ writel(ADM_CRCI_CTL_RST, adev->regs +
++ ADM_CRCI_CTL(i, adev->ee));
++
++ /* configure client interfaces */
++ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
++ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
++ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
++ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
++ adev->regs + ADM_GP_CTL);
++
++ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
++ 0, "adm_dma", adev);
++ if (ret)
++ goto err_disable_clks;
++
++ platform_set_drvdata(pdev, adev);
++
++ adev->common.dev = adev->dev;
++ adev->common.dev->dma_parms = &adev->dma_parms;
++
++ /* set capabilities */
++ dma_cap_zero(adev->common.cap_mask);
++ dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
++ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
++
++ /* initialize dmaengine apis */
++ adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
++ adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
++ adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ adev->common.device_free_chan_resources = adm_free_chan;
++ adev->common.device_prep_slave_sg = adm_prep_slave_sg;
++ adev->common.device_issue_pending = adm_issue_pending;
++ adev->common.device_tx_status = adm_tx_status;
++ adev->common.device_terminate_all = adm_terminate_all;
++ adev->common.device_config = adm_slave_config;
++
++ ret = dma_async_device_register(&adev->common);
++ if (ret) {
++ dev_err(adev->dev, "failed to register dma async device\n");
++ goto err_disable_clks;
++ }
++
++ ret = of_dma_controller_register(pdev->dev.of_node,
++ of_dma_xlate_by_chan_id,
++ &adev->common);
++ if (ret)
++ goto err_unregister_dma;
++
++ return 0;
++
++err_unregister_dma:
++ dma_async_device_unregister(&adev->common);
++err_disable_clks:
++ clk_disable_unprepare(adev->iface_clk);
++err_disable_core_clk:
++ clk_disable_unprepare(adev->core_clk);
++
++ return ret;
++}
++
++static int adm_dma_remove(struct platform_device *pdev)
++{
++ struct adm_device *adev = platform_get_drvdata(pdev);
++ struct adm_chan *achan;
++ u32 i;
++
++ of_dma_controller_free(pdev->dev.of_node);
++ dma_async_device_unregister(&adev->common);
++
++ for (i = 0; i < ADM_MAX_CHANNELS; i++) {
++ achan = &adev->channels[i];
++
++ /* mask IRQs for this channel/EE pair */
++ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
++
++ adm_terminate_all(&adev->channels[i].vc.chan);
++ }
++
++ devm_free_irq(adev->dev, adev->irq, adev);
++
++ clk_disable_unprepare(adev->core_clk);
++ clk_disable_unprepare(adev->iface_clk);
++
++ return 0;
++}
++
++static const struct of_device_id adm_of_match[] = {
++ { .compatible = "qcom,adm", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, adm_of_match);
++
++static struct platform_driver adm_dma_driver = {
++ .probe = adm_dma_probe,
++ .remove = adm_dma_remove,
++ .driver = {
++ .name = "adm-dma-engine",
++ .of_match_table = adm_of_match,
++ },
++};
++
++module_platform_driver(adm_dma_driver);
++
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 08:16:10 +0100
+Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4
+
+This patch was not annotated and comes from the v4.4 tree.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -365,7 +365,7 @@ static struct clk_rcg gsbi1_uart_src = {
+ .parent_names = gcc_pxo_pll8,
+ .num_parents = 2,
+ .ops = &clk_rcg_ops,
+- .flags = CLK_SET_PARENT_GATE,
++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
+ },
+ },
+ };
+@@ -383,7 +383,7 @@ static struct clk_branch gsbi1_uart_clk
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+- .flags = CLK_SET_RATE_PARENT,
++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+ },
+ };
+@@ -961,6 +961,7 @@ static struct clk_branch gsbi1_h_clk = {
+ .hw.init = &(struct clk_init_data){
+ .name = "gsbi1_h_clk",
+ .ops = &clk_branch_ops,
++ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+ };
--- /dev/null
+From d8eeb4de90e968ba32d956728c866f20752cf2c3 Mon Sep 17 00:00:00 2001
+From: Mathieu Olivari <mathieu@codeaurora.org>
+Date: Thu, 9 Mar 2017 08:18:08 +0100
+Subject: [PATCH 31/69] mtd: add SMEM parser for QCOM platforms
+
+On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is
+used to store partition layout. This new parser can now be used to read
+SMEM and use it to register an MTD layout according to its content.
+
+Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
+---
+ drivers/mtd/parsers/Kconfig | 7 ++
+ drivers/mtd/parsers/Makefile | 1 +
+ drivers/mtd/parsers/qcom_smem_part.c | 228 +++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 236 insertions(+)
+ create mode 100644 drivers/mtd/parsers/qcom_smem_part.c
+
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -119,6 +119,13 @@ config MTD_PARSER_TRX
+ This driver will parse TRX header and report at least two partitions:
+ kernel and rootfs.
+
++config MTD_QCOM_SMEM_PARTS
++ tristate "QCOM SMEM partitioning support"
++ depends on QCOM_SMEM
++ help
++ This provides partitions parser for QCOM devices using SMEM
++ such as IPQ806x.
++
+ config MTD_SHARPSL_PARTS
+ tristate "Sharp SL Series NAND flash partition parser"
+ depends on MTD_NAND_SHARPSL || MTD_NAND_TMIO || COMPILE_TEST
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
+ obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o
++obj-$(CONFIG_MTD_QCOM_SMEM_PARTS) += qcom_smem_part.o
+ obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
+ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
+ obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o
+--- /dev/null
++++ b/drivers/mtd/parsers/qcom_smem_part.c
+@@ -0,0 +1,235 @@
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/spi/spi.h>
++#include <linux/module.h>
++
++#include <linux/soc/qcom/smem.h>
++
++/* Processor/host identifier for the application processor */
++#define SMEM_HOST_APPS 0
++
++/* SMEM items index */
++#define SMEM_AARM_PARTITION_TABLE 9
++#define SMEM_BOOT_FLASH_TYPE 421
++#define SMEM_BOOT_FLASH_BLOCK_SIZE 424
++
++/* SMEM Flash types */
++#define SMEM_FLASH_NAND 2
++#define SMEM_FLASH_SPI 6
++
++#define SMEM_PART_NAME_SZ 16
++#define SMEM_PARTS_MAX 32
++
++struct smem_partition {
++ char name[SMEM_PART_NAME_SZ];
++ __le32 start;
++ __le32 size;
++ __le32 attr;
++};
++
++struct smem_partition_table {
++ u8 magic[8];
++ __le32 version;
++ __le32 len;
++ struct smem_partition parts[SMEM_PARTS_MAX];
++};
++
++/* SMEM Magic values in partition table */
++static const u8 SMEM_PTABLE_MAGIC[] = {
++ 0xaa, 0x73, 0xee, 0x55,
++ 0xdb, 0xbd, 0x5e, 0xe3,
++};
++
++static int qcom_smem_get_flash_blksz(u64 **smem_blksz)
++{
++ size_t size;
++
++ *smem_blksz = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_BLOCK_SIZE,
++ &size);
++
++ if (IS_ERR(*smem_blksz)) {
++ pr_err("Unable to read flash blksz from SMEM\n");
++ return -ENOENT;
++ }
++
++ if (size != sizeof(**smem_blksz)) {
++ pr_err("Invalid flash blksz size in SMEM\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int qcom_smem_get_flash_type(u64 **smem_flash_type)
++{
++ size_t size;
++
++ *smem_flash_type = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_TYPE,
++ &size);
++
++ if (IS_ERR(*smem_flash_type)) {
++ pr_err("Unable to read flash type from SMEM\n");
++ return -ENOENT;
++ }
++
++ if (size != sizeof(**smem_flash_type)) {
++ pr_err("Invalid flash type size in SMEM\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int qcom_smem_get_flash_partitions(struct smem_partition_table **pparts)
++{
++ size_t size;
++
++ *pparts = qcom_smem_get(SMEM_HOST_APPS, SMEM_AARM_PARTITION_TABLE,
++ &size);
++
++ if (IS_ERR(*pparts)) {
++ pr_err("Unable to read partition table from SMEM\n");
++ return -ENOENT;
++ }
++
++ return 0;
++}
++
++static int of_dev_node_match(struct device *dev, const void *data)
++{
++ return dev->of_node == data;
++}
++
++static bool is_spi_device(struct device_node *np)
++{
++ struct device *dev;
++
++ dev = bus_find_device(&spi_bus_type, NULL, np, of_dev_node_match);
++ if (!dev)
++ return false;
++
++ put_device(dev);
++ return true;
++}
++
++static int parse_qcom_smem_partitions(struct mtd_info *master,
++ const struct mtd_partition **pparts,
++ struct mtd_part_parser_data *data)
++{
++ struct smem_partition_table *smem_parts;
++ u64 *smem_flash_type, *smem_blksz;
++ struct mtd_partition *mtd_parts;
++ struct device_node *of_node = master->dev.of_node;
++ int i, ret;
++
++ /*
++ * SMEM will only store the partition table of the boot device.
++ * If this is not the boot device, do not return any partition.
++ */
++ ret = qcom_smem_get_flash_type(&smem_flash_type);
++ if (ret < 0)
++ return ret;
++
++ if ((*smem_flash_type == SMEM_FLASH_NAND && !mtd_type_is_nand(master))
++ || (*smem_flash_type == SMEM_FLASH_SPI && !is_spi_device(of_node)))
++ return 0;
++
++ /*
++ * Just for sanity purpose, make sure the block size in SMEM matches the
++ * block size of the MTD device
++ */
++ ret = qcom_smem_get_flash_blksz(&smem_blksz);
++ if (ret < 0)
++ return ret;
++
++ if (*smem_blksz != master->erasesize) {
++ pr_err("SMEM block size differs from MTD block size\n");
++ return -EINVAL;
++ }
++
++ /* Get partition pointer from SMEM */
++ ret = qcom_smem_get_flash_partitions(&smem_parts);
++ if (ret < 0)
++ return ret;
++
++ if (memcmp(SMEM_PTABLE_MAGIC, smem_parts->magic,
++ sizeof(SMEM_PTABLE_MAGIC))) {
++ pr_err("SMEM partition magic invalid\n");
++ return -EINVAL;
++ }
++
++ /* Allocate and populate the mtd structures */
++ mtd_parts = kcalloc(le32_to_cpu(smem_parts->len), sizeof(*mtd_parts),
++ GFP_KERNEL);
++ if (!mtd_parts)
++ return -ENOMEM;
++
++ for (i = 0; i < smem_parts->len; i++) {
++ struct smem_partition *s_part = &smem_parts->parts[i];
++ struct mtd_partition *m_part = &mtd_parts[i];
++
++ m_part->name = s_part->name;
++ m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz);
++ m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz);
++
++ /*
++ * The last SMEM partition may have its size marked as
++ * something like 0xffffffff, which means "until the end of the
++ * flash device". In this case, truncate it.
++ */
++ if (m_part->offset + m_part->size > master->size)
++ m_part->size = master->size - m_part->offset;
++ }
++
++ *pparts = mtd_parts;
++
++ return smem_parts->len;
++}
++
++static const struct of_device_id qcom_smem_of_match_table[] = {
++ { .compatible = "qcom,smem" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, qcom_smem_of_match_table);
++
++static struct mtd_part_parser qcom_smem_parser = {
++ .owner = THIS_MODULE,
++ .parse_fn = parse_qcom_smem_partitions,
++ .name = "qcom-smem",
++ .of_match_table = qcom_smem_of_match_table,
++};
++
++static int __init qcom_smem_parser_init(void)
++{
++ register_mtd_parser(&qcom_smem_parser);
++ return 0;
++}
++
++static void __exit qcom_smem_parser_exit(void)
++{
++ deregister_mtd_parser(&qcom_smem_parser);
++}
++
++module_init(qcom_smem_parser_init);
++module_exit(qcom_smem_parser_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
++MODULE_DESCRIPTION("Parsing code for SMEM based partition tables");
--- /dev/null
+From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001
+From: Mathieu Olivari <mathieu@codeaurora.org>
+Date: Tue, 21 Apr 2015 19:09:07 -0700
+Subject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is
+ enabled
+
+If multiple PCIe devices are present in the system, the kernel will
+panic at boot time when trying to scan the PCI buses. This happens on
+IPQ806x based platforms, which has 3 PCIe ports.
+
+Enabling this option allows the kernel to assign the pci-domains
+according to the device-tree content. This allows multiple PCIe
+controllers to coexist in the system.
+
+Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+---
+ arch/arm/mach-qcom/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-qcom/Kconfig
++++ b/arch/arm/mach-qcom/Kconfig
+@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM
+ select ARM_AMBA
+ select PINCTRL
+ select QCOM_SCM if SMP
++ select PCI_DOMAINS if PCI
+ help
+ Support for Qualcomm's devicetree based systems.
+
--- /dev/null
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+To: krzk@kernel.org, vireshk@kernel.org, robh+dt@kernel.org
+Cc: sboyd@kernel.org, roger.lu@mediatek.com,
+ linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
+ b.zolnierkie@samsung.com, m.szyprowski@samsung.com,
+ Stephen Boyd <sboyd@codeaurora.org>,
+ Sylwester Nawrocki <s.nawrocki@samsung.com>
+Subject: [PATCH v5 1/4] PM / OPP: Support adjusting OPP voltages at runtime
+Date: Wed, 16 Oct 2019 16:57:53 +0200
+Message-ID: <20191016145756.16004-2-s.nawrocki@samsung.com> (raw)
+In-Reply-To: <20191016145756.16004-1-s.nawrocki@samsung.com>
+
+From: Stephen Boyd <sboyd@codeaurora.org>
+
+On some SoCs the Adaptive Voltage Scaling (AVS) technique is
+employed to optimize the operating voltage of a device. At a
+given frequency, the hardware monitors dynamic factors and either
+makes a suggestion for how much to adjust a voltage for the
+current frequency, or it automatically adjusts the voltage
+without software intervention. Add an API to the OPP library for
+the former case, so that AVS type devices can update the voltages
+for an OPP when the hardware determines the voltage should
+change. The assumption is that drivers like CPUfreq or devfreq
+will register for the OPP notifiers and adjust the voltage
+according to suggestions that AVS makes.
+
+This patch is derived from [1] submitted by Stephen.
+[1] https://lore.kernel.org/patchwork/patch/599279/
+
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Roger Lu <roger.lu@mediatek.com>
+[s.nawrocki@samsung.com: added handling of OPP min/max voltage]
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+---
+ drivers/opp/core.c | 69 ++++++++++++++++++++++++++++++++++++++++++
+ include/linux/pm_opp.h | 13 ++++++++
+ 2 files changed, 82 insertions(+)
+
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -2102,6 +2102,75 @@ put_table:
+ }
+
+ /**
++ * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP
++ * @dev: device for which we do this operation
++ * @freq: OPP frequency to adjust voltage of
++ * @u_volt: new OPP target voltage
++ * @u_volt_min: new OPP min voltage
++ * @u_volt_max: new OPP max voltage
++ *
++ * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the
++ * copy operation, returns 0 if no modifcation was done OR modification was
++ * successful.
++ */
++int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
++ unsigned long u_volt, unsigned long u_volt_min,
++ unsigned long u_volt_max)
++
++{
++ struct opp_table *opp_table;
++ struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV);
++ int r = 0;
++
++ /* Find the opp_table */
++ opp_table = _find_opp_table(dev);
++ if (IS_ERR(opp_table)) {
++ r = PTR_ERR(opp_table);
++ dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r);
++ return r;
++ }
++
++ mutex_lock(&opp_table->lock);
++
++ /* Do we have the frequency? */
++ list_for_each_entry(tmp_opp, &opp_table->opp_list, node) {
++ if (tmp_opp->rate == freq) {
++ opp = tmp_opp;
++ break;
++ }
++ }
++
++ if (IS_ERR(opp)) {
++ r = PTR_ERR(opp);
++ goto adjust_unlock;
++ }
++
++ /* Is update really needed? */
++ if (opp->supplies->u_volt == u_volt)
++ goto adjust_unlock;
++
++ opp->supplies->u_volt = u_volt;
++ opp->supplies->u_volt_min = u_volt_min;
++ opp->supplies->u_volt_max = u_volt_max;
++
++ dev_pm_opp_get(opp);
++ mutex_unlock(&opp_table->lock);
++
++ /* Notify the voltage change of the OPP */
++ blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE,
++ opp);
++
++ dev_pm_opp_put(opp);
++ goto adjust_put_table;
++
++adjust_unlock:
++ mutex_unlock(&opp_table->lock);
++adjust_put_table:
++ dev_pm_opp_put_opp_table(opp_table);
++ return r;
++}
++
++/**
+ * dev_pm_opp_enable() - Enable a specific OPP
+ * @dev: device for which we do this operation
+ * @freq: OPP frequency to enable
+--- a/include/linux/pm_opp.h
++++ b/include/linux/pm_opp.h
+@@ -22,6 +22,7 @@ struct opp_table;
+
+ enum dev_pm_opp_event {
+ OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE,
++ OPP_EVENT_ADJUST_VOLTAGE,
+ };
+
+ /**
+@@ -113,6 +114,10 @@ int dev_pm_opp_add(struct device *dev, u
+ void dev_pm_opp_remove(struct device *dev, unsigned long freq);
+ void dev_pm_opp_remove_all_dynamic(struct device *dev);
+
++int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
++ unsigned long u_volt, unsigned long u_volt_min,
++ unsigned long u_volt_max);
++
+ int dev_pm_opp_enable(struct device *dev, unsigned long freq);
+
+ int dev_pm_opp_disable(struct device *dev, unsigned long freq);
+@@ -242,6 +247,14 @@ static inline void dev_pm_opp_remove_all
+ {
+ }
+
++static inline int
++dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
++ unsigned long u_volt, unsigned long u_volt_min,
++ unsigned long u_volt_max)
++{
++ return 0;
++}
++
+ static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq)
+ {
+ return 0;
--- /dev/null
+From d06ca5e7a3cf726f5be5ffd96e93ccd798b8c09a Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Thu, 12 May 2016 14:41:33 +0300
+Subject: [PATCH 51/69] PM / OPP: Add a helper to get an opp regulator for
+ device
+
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+---
+ drivers/opp/core.c | 21 +++++++++++++++++++++
+ include/linux/pm_opp.h | 1 +
+ 2 files changed, 22 insertions(+)
+
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -127,6 +127,27 @@ unsigned long dev_pm_opp_get_freq(struct
+ }
+ EXPORT_SYMBOL_GPL(dev_pm_opp_get_freq);
+
++struct regulator *dev_pm_opp_get_regulator(struct device *dev)
++{
++ struct opp_table *opp_table;
++ struct regulator *reg;
++
++ rcu_read_lock();
++
++ opp_table = _find_opp_table(dev);
++ if (IS_ERR(opp_table)) {
++ rcu_read_unlock();
++ return ERR_CAST(opp_table);
++ }
++
++ reg = opp_table->regulators[0];
++
++ rcu_read_unlock();
++
++ return reg;
++}
++EXPORT_SYMBOL_GPL(dev_pm_opp_get_regulator);
++
+ /**
+ * dev_pm_opp_get_level() - Gets the level corresponding to an available opp
+ * @opp: opp for which level value has to be returned for
+--- a/include/linux/pm_opp.h
++++ b/include/linux/pm_opp.h
+@@ -83,6 +83,7 @@ void dev_pm_opp_put_opp_table(struct opp
+ unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp);
+
+ unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp);
++struct regulator *dev_pm_opp_get_regulator(struct device *dev);
+
+ unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp);
+
--- /dev/null
+From 4533c285c2aedce6d4434d7b877066de3b1ecb33 Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Thu, 25 Aug 2016 18:43:35 +0300
+Subject: [PATCH 52/69] PM / OPP: Update the voltage tolerance when adjusting
+ the OPP
+
+When the voltage is adjusted, the voltage tolerance is not updated.
+This can lead to situations where the voltage min value is greater
+than the voltage max value. The final result is triggering a BUG()
+in the regulator core.
+Fix this by updating the voltage tolerance values too.
+
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+---
+ drivers/opp/core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -2142,6 +2142,7 @@ int dev_pm_opp_adjust_voltage(struct dev
+ struct opp_table *opp_table;
+ struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV);
+ int r = 0;
++ unsigned long tol;
+
+ /* Find the opp_table */
+ opp_table = _find_opp_table(dev);
+@@ -2171,8 +2172,17 @@ int dev_pm_opp_adjust_voltage(struct dev
+ goto adjust_unlock;
+
+ opp->supplies->u_volt = u_volt;
+- opp->supplies->u_volt_min = u_volt_min;
+- opp->supplies->u_volt_max = u_volt_max;
++
++ tol = u_volt * opp_table->voltage_tolerance_v1 / 100;
++ if ( u_volt_min == u_volt )
++ opp->supplies->u_volt_min = u_volt - tol;
++ else
++ opp->supplies->u_volt_min = u_volt_min;
++
++ if ( u_volt_max == u_volt )
++ opp->supplies->u_volt_max = u_volt + tol;
++ else
++ opp->supplies->u_volt_max = u_volt_max;
+
+ dev_pm_opp_get(opp);
+ mutex_unlock(&opp_table->lock);
--- /dev/null
+From 10577f74c35bd395951d1b2382c8d821089b5745 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Fri, 18 Sep 2015 17:52:08 -0700
+Subject: [PATCH 54/69] cpufreq-dt: Handle OPP voltage adjust events
+
+On some SoCs the Adaptive Voltage Scaling (AVS) technique is
+employed to optimize the operating voltage of a device. At a
+given frequency, the hardware monitors dynamic factors and either
+makes a suggestion for how much to adjust a voltage for the
+current frequency, or it automatically adjusts the voltage
+without software intervention.
+
+In the former case, an AVS driver will call
+dev_pm_opp_modify_voltage() and update the voltage for the
+particular OPP the CPUs are using. Add an OPP notifier to
+cpufreq-dt so that we can adjust the voltage of the CPU when AVS
+updates the OPP.
+
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+---
+ drivers/cpufreq/cpufreq-dt.c | 68 ++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 65 insertions(+), 3 deletions(-)
+
+--- a/drivers/cpufreq/cpufreq-dt.c
++++ b/drivers/cpufreq/cpufreq-dt.c
+@@ -27,6 +27,9 @@ struct private_data {
+ struct opp_table *opp_table;
+ struct device *cpu_dev;
+ const char *reg_name;
++ struct notifier_block opp_nb;
++ struct mutex lock;
++ unsigned long opp_freq;
+ bool have_static_opps;
+ };
+
+@@ -42,12 +45,15 @@ static int set_target(struct cpufreq_pol
+ unsigned long freq = policy->freq_table[index].frequency;
+ int ret;
+
++ mutex_lock(&priv->lock);
+ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
+
+ if (!ret) {
++ priv->opp_freq = freq * 1000;
+ arch_set_freq_scale(policy->related_cpus, freq,
+ policy->cpuinfo.max_freq);
+ }
++ mutex_unlock(&priv->lock);
+
+ return ret;
+ }
+@@ -90,6 +96,39 @@ node_put:
+ return name;
+ }
+
++static int opp_notifier(struct notifier_block *nb, unsigned long event,
++ void *data)
++{
++ struct dev_pm_opp *opp = data;
++ struct private_data *priv = container_of(nb, struct private_data,
++ opp_nb);
++ struct device *cpu_dev = priv->cpu_dev;
++ struct regulator *cpu_reg;
++ unsigned long volt, freq;
++ int ret = 0;
++
++ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
++ cpu_reg = dev_pm_opp_get_regulator(cpu_dev);
++ if (IS_ERR(cpu_reg)) {
++ ret = PTR_ERR(cpu_reg);
++ goto out;
++ }
++ volt = dev_pm_opp_get_voltage(opp);
++ freq = dev_pm_opp_get_freq(opp);
++
++ mutex_lock(&priv->lock);
++ if (freq == priv->opp_freq) {
++ ret = regulator_set_voltage_triplet(cpu_reg, volt, volt, volt);
++ }
++ mutex_unlock(&priv->lock);
++ if (ret)
++ dev_err(cpu_dev, "failed to scale voltage: %d\n", ret);
++ }
++
++out:
++ return notifier_from_errno(ret);
++}
++
+ static int resources_available(void)
+ {
+ struct device *cpu_dev;
+@@ -246,10 +285,14 @@ static int cpufreq_init(struct cpufreq_p
+ __func__, ret);
+ }
+
++ mutex_init(&priv->lock);
++ priv->opp_nb.notifier_call = opp_notifier;
++ dev_pm_opp_register_notifier(cpu_dev, &priv->opp_nb);
++
+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+- goto out_free_opp;
++ goto out_unregister_nb;
+ }
+
+ priv->cpu_dev = cpu_dev;
+@@ -281,6 +324,8 @@ static int cpufreq_init(struct cpufreq_p
+
+ out_free_cpufreq_table:
+ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
++out_unregister_nb:
++ dev_pm_opp_unregister_notifier(cpu_dev, &priv->opp_nb);
+ out_free_opp:
+ if (priv->have_static_opps)
+ dev_pm_opp_of_cpumask_remove_table(policy->cpus);
--- /dev/null
+--- a/drivers/cpufreq/cpufreq-dt.c
++++ b/drivers/cpufreq/cpufreq-dt.c
+@@ -39,20 +39,85 @@ static struct freq_attr *cpufreq_dt_attr
+ NULL,
+ };
+
++struct shared_data {
++ unsigned long *curr_freq_table;
++ unsigned long curr_l2_freq;
++ unsigned long curr_l2_volt;
++};
++
++static struct shared_data *cpus_shared_data;
++
+ static int set_target(struct cpufreq_policy *policy, unsigned int index)
+ {
+ struct private_data *priv = policy->driver_data;
+ unsigned long freq = policy->freq_table[index].frequency;
++ struct clk *l2_clk = policy->l2_clk;
++ struct regulator *l2_regulator = policy->l2_regulator;
++ unsigned long l2_freq, target_l2_freq;
++ unsigned long l2_vol, target_l2_volt;
++ unsigned long target_freq;
+ int ret;
+
+ mutex_lock(&priv->lock);
+ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
+
+ if (!ret) {
++ if (policy->l2_rate_set) {
++ int cpu, l2_index, tol = 0;
++ target_freq = freq * 1000;
++
++ cpus_shared_data->curr_freq_table[policy->cpu] = target_freq;
++ for_each_present_cpu(cpu)
++ if (cpu != policy->cpu)
++ target_freq = max(target_freq, cpus_shared_data->curr_freq_table[cpu]);
++
++ for (l2_index = 2; l2_index > 0; l2_index--)
++ if (target_freq >= policy->l2_cpufreq[l2_index])
++ break;
++
++ l2_freq = cpus_shared_data->curr_l2_freq;
++ target_l2_freq = policy->l2_rate[l2_index];
++
++ if (l2_freq != target_l2_freq) {
++
++ /*
++ * Set to idle bin if switching from normal to high bin
++ * or vice versa
++ */
++ if ( (l2_index == 2 && l2_freq == policy->l2_rate[1]) ||
++ (l2_index == 1 && l2_freq == policy->l2_rate[2]) ) {
++ ret = clk_set_rate(l2_clk, policy->l2_rate[0]);
++ if (ret)
++ goto exit;
++ }
++
++ /* scale l2 with the core */
++ ret = clk_set_rate(l2_clk, target_l2_freq);
++ if (ret)
++ goto exit;
++ cpus_shared_data->curr_l2_freq = target_l2_freq;
++
++ if (policy->l2_volt_set) {
++
++ l2_vol = cpus_shared_data->curr_l2_volt;
++ target_l2_volt = policy->l2_volt[l2_index];
++
++ if (l2_vol != target_l2_volt) {
++ tol = target_l2_volt * policy->l2_volt_tol / 100;
++ ret = regulator_set_voltage_tol(l2_regulator,target_l2_volt,tol);
++ if (ret)
++ goto exit;
++ cpus_shared_data->curr_l2_volt = target_l2_volt;
++ }
++ }
++ }
++ }
+ priv->opp_freq = freq * 1000;
+ arch_set_freq_scale(policy->related_cpus, freq,
+ policy->cpuinfo.max_freq);
+ }
++
++exit:
+ mutex_unlock(&priv->lock);
+
+ return ret;
+@@ -195,6 +260,9 @@ static int cpufreq_init(struct cpufreq_p
+ bool fallback = false;
+ const char *name;
+ int ret;
++ struct device_node *np, *l2_np;
++ struct clk *l2_clk = NULL;
++ struct regulator *l2_regulator = NULL;
+
+ cpu_dev = get_cpu_device(policy->cpu);
+ if (!cpu_dev) {
+@@ -302,6 +370,57 @@ static int cpufreq_init(struct cpufreq_p
+
+ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;
+
++ policy->l2_rate_set = false;
++ policy->l2_volt_set = false;
++
++ l2_clk = clk_get(cpu_dev, "l2");
++ if (!IS_ERR(l2_clk))
++ policy->l2_clk = l2_clk;
++
++ l2_np = of_find_node_by_name(NULL, "qcom,l2");
++ if (l2_np) {
++ struct device_node *vdd;
++ np = of_node_get(priv->cpu_dev->of_node);
++
++ if (np)
++ of_property_read_u32(np, "voltage-tolerance", &policy->l2_volt_tol);
++
++ of_property_read_u32_array(l2_np, "qcom,l2-rates", policy->l2_rate, 3);
++ if (policy->l2_rate[0] && policy->l2_rate[1] && policy->l2_rate[2]) {
++ policy->l2_rate_set = true;
++ of_property_read_u32_array(l2_np, "qcom,l2-cpufreq", policy->l2_cpufreq, 3);
++ of_property_read_u32_array(l2_np, "qcom,l2-volt", policy->l2_volt, 3);
++ } else
++ pr_warn("L2: failed to parse L2 rates\n");
++
++ if (!policy->l2_cpufreq[0] && !policy->l2_cpufreq[1] &&
++ !policy->l2_cpufreq[2] && policy->l2_rate_set) {
++ int i;
++
++ pr_warn("L2: failed to parse target cpu freq, using defaults\n");
++ for (i = 0; i < 3; i++)
++ policy->l2_cpufreq[i] = policy->l2_rate[i];
++ }
++
++ if (policy->l2_volt[0] && policy->l2_volt[1] && policy->l2_volt[2] &&
++ policy->l2_volt_tol && policy->l2_rate_set) {
++ vdd = of_parse_phandle(l2_np, "qcom,l2-supply", 0);
++
++ if (vdd) {
++ l2_regulator = devm_regulator_get(cpu_dev, vdd->name);
++ if (!IS_ERR(l2_regulator)) {
++ policy->l2_regulator = l2_regulator;
++ policy->l2_volt_set = true;
++ } else {
++ pr_warn("failed to get l2 supply\n");
++ l2_regulator = NULL;
++ }
++
++ of_node_put(vdd);
++ }
++ }
++ }
++
+ /* Support turbo/boost mode */
+ if (policy_has_boost_freq(policy)) {
+ /* This gets disabled by core on driver unregister */
+@@ -401,6 +520,14 @@ static int dt_cpufreq_probe(struct platf
+ if (ret)
+ return ret;
+
++ cpus_shared_data = kzalloc(sizeof(struct shared_data), GFP_KERNEL);
++ if (!cpus_shared_data)
++ return -ENOMEM;
++
++ cpus_shared_data->curr_freq_table = kzalloc(sizeof(int) * CONFIG_NR_CPUS, GFP_KERNEL);
++ if (!cpus_shared_data->curr_freq_table)
++ return -ENOMEM;
++
+ if (data) {
+ if (data->have_governor_per_policy)
+ dt_cpufreq_driver.flags |= CPUFREQ_HAVE_GOVERNOR_PER_POLICY;
+@@ -419,6 +546,8 @@ static int dt_cpufreq_probe(struct platf
+
+ static int dt_cpufreq_remove(struct platform_device *pdev)
+ {
++ kfree(cpus_shared_data->curr_freq_table);
++ kfree(cpus_shared_data);
+ cpufreq_unregister_driver(&dt_cpufreq_driver);
+ return 0;
+ }
+--- a/include/linux/cpufreq.h
++++ b/include/linux/cpufreq.h
+@@ -58,7 +58,15 @@ struct cpufreq_policy {
+ should set cpufreq */
+ unsigned int cpu; /* cpu managing this policy, must be online */
+
+- struct clk *clk;
++ struct clk *clk;
++ struct clk *l2_clk; /* L2 clock */
++ struct regulator *l2_regulator; /* L2 supply */
++ unsigned int l2_rate[3]; /* L2 bus clock rate */
++ bool l2_rate_set;
++ unsigned int l2_cpufreq[3]; /* L2 target CPU frequency */
++ unsigned int l2_volt[3]; /* L2 voltage array */
++ bool l2_volt_set;
++ unsigned int l2_volt_tol; /* L2 voltage tolerance */
+ struct cpufreq_cpuinfo cpuinfo;/* see above */
+
+ unsigned int min; /* in kHz */
--- /dev/null
+From 001a8dcb56ced58c518aaa10a4f0ba5e878705b6 Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Tue, 17 May 2016 16:15:43 +0300
+Subject: [PATCH 56/69] cpufreq-dt: Add missing rcu locks
+
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+---
+ drivers/cpufreq/cpufreq-dt.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/cpufreq/cpufreq-dt.c
++++ b/drivers/cpufreq/cpufreq-dt.c
+@@ -178,8 +178,10 @@ static int opp_notifier(struct notifier_
+ ret = PTR_ERR(cpu_reg);
+ goto out;
+ }
++ rcu_read_lock();
+ volt = dev_pm_opp_get_voltage(opp);
+ freq = dev_pm_opp_get_freq(opp);
++ rcu_read_unlock();
+
+ mutex_lock(&priv->lock);
+ if (freq == priv->opp_freq) {
--- /dev/null
+--- a/drivers/clk/qcom/Makefile
++++ b/drivers/clk/qcom/Makefile
+@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k
+ clk-qcom-y += clk-hfpll.o
+ clk-qcom-y += reset.o
+ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
++clk-qcom-y += fab_scaling.o
+
+ # Keep alphabetically sorted by config
+ obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
+--- /dev/null
++++ b/drivers/clk/qcom/fab_scaling.c
+@@ -0,0 +1,172 @@
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include <linux/fab_scaling.h>
++
++struct qcom_fab_scaling_data {
++ u32 fab_freq_high;
++ u32 fab_freq_nominal;
++ u32 cpu_freq_threshold;
++ struct clk *apps_fab_clk;
++ struct clk *ddr_fab_clk;
++};
++
++static struct qcom_fab_scaling_data *drv_data;
++
++int scale_fabrics(unsigned long max_cpu_freq)
++{
++ struct clk *apps_fab_clk = drv_data->apps_fab_clk,
++ *ddr_fab_clk = drv_data->ddr_fab_clk;
++ unsigned long target_freq, cur_freq;
++ int ret;
++
++ /* Skip fab scaling if the driver is not ready */
++ if (!apps_fab_clk || !ddr_fab_clk)
++ return 0;
++
++ if (max_cpu_freq > drv_data->cpu_freq_threshold)
++ target_freq = drv_data->fab_freq_high;
++ else
++ target_freq = drv_data->fab_freq_nominal;
++
++ cur_freq = clk_get_rate(ddr_fab_clk);
++
++ if (target_freq != cur_freq) {
++ ret = clk_set_rate(apps_fab_clk, target_freq);
++ if (ret)
++ return ret;
++ ret = clk_set_rate(ddr_fab_clk, target_freq);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(scale_fabrics);
++
++static int ipq806x_fab_scaling_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct clk *apps_fab_clk, *ddr_fab_clk;
++ int ret;
++
++ if (!np)
++ return -ENODEV;
++
++ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);
++ if (!drv_data)
++ return -ENOMEM;
++
++ if (of_property_read_u32(np, "fab_freq_high", &drv_data->fab_freq_high)) {
++ pr_err("FABRICS turbo freq not found. Using defaults...\n");
++ drv_data->fab_freq_high = 533000000;
++ }
++
++ if (of_property_read_u32(np, "fab_freq_nominal", &drv_data->fab_freq_nominal)) {
++ pr_err("FABRICS nominal freq not found. Using defaults...\n");
++ drv_data->fab_freq_nominal = 400000000;
++ }
++
++ if (of_property_read_u32(np, "cpu_freq_threshold", &drv_data->cpu_freq_threshold)) {
++ pr_err("FABRICS cpu freq threshold not found. Using defaults...\n");
++ drv_data->cpu_freq_threshold = 1000000000;
++ }
++
++ apps_fab_clk = devm_clk_get(&pdev->dev, "apps-fab-clk");
++ ret = PTR_ERR_OR_ZERO(apps_fab_clk);
++ if (ret) {
++ /*
++ * If apps fab clk node is present, but clock is not yet
++ * registered, we should try defering probe.
++ */
++ if (ret != -EPROBE_DEFER) {
++ pr_err("Failed to get APPS FABRIC clock: %d\n", ret);
++ ret = -ENODEV;
++ }
++ goto err;
++ }
++
++ clk_prepare_enable(apps_fab_clk);
++ clk_set_rate(apps_fab_clk, drv_data->fab_freq_high);
++ drv_data->apps_fab_clk = apps_fab_clk;
++
++ ddr_fab_clk = devm_clk_get(&pdev->dev, "ddr-fab-clk");
++ ret = PTR_ERR_OR_ZERO(ddr_fab_clk);
++ if (ret) {
++ /*
++ * If ddr fab clk node is present, but clock is not yet
++ * registered, we should try defering probe.
++ */
++ if (ret != -EPROBE_DEFER) {
++ pr_err("Failed to get DDR FABRIC clock: %d\n", ret);
++ ddr_fab_clk = NULL;
++ ret = -ENODEV;
++ }
++ goto err;
++ }
++
++ clk_prepare_enable(ddr_fab_clk);
++ clk_set_rate(ddr_fab_clk, drv_data->fab_freq_high);
++ drv_data->ddr_fab_clk = ddr_fab_clk;
++
++ return 0;
++err:
++ kfree(drv_data);
++ return ret;
++}
++
++static int ipq806x_fab_scaling_remove(struct platform_device *pdev)
++{
++ kfree(drv_data);
++ return 0;
++}
++
++static const struct of_device_id fab_scaling_ipq806x_match_table[] = {
++ { .compatible = "qcom,fab-scaling" },
++ { }
++};
++
++static struct platform_driver fab_scaling_ipq806x_driver = {
++ .probe = ipq806x_fab_scaling_probe,
++ .remove = ipq806x_fab_scaling_remove,
++ .driver = {
++ .name = "fab-scaling",
++ .of_match_table = fab_scaling_ipq806x_match_table,
++ },
++};
++
++static int __init fab_scaling_ipq806x_init(void)
++{
++ return platform_driver_register(&fab_scaling_ipq806x_driver);
++}
++late_initcall(fab_scaling_ipq806x_init);
++
++static void __exit fab_scaling_ipq806x_exit(void)
++{
++ platform_driver_unregister(&fab_scaling_ipq806x_driver);
++}
++module_exit(fab_scaling_ipq806x_exit);
+--- /dev/null
++++ b/include/linux/fab_scaling.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __FAB_SCALING_H
++#define __FAB_SCALING_H
++
++/**
++ * scale_fabrics - Scale DDR and APPS FABRICS
++ *
++ * This function monitors all the registered clocks and does APPS
++ * and DDR FABRIC scaling based on the idle frequencies with which
++ * it was registered.
++ *
++ */
++int scale_fabrics(unsigned long max_cpu_freq);
++
++#endif
+--- a/drivers/cpufreq/cpufreq-dt.c
++++ b/drivers/cpufreq/cpufreq-dt.c
+@@ -20,6 +20,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ #include <linux/thermal.h>
++#include <linux/fab_scaling.h>
+
+ #include "cpufreq-dt.h"
+
+@@ -111,6 +112,13 @@ static int set_target(struct cpufreq_pol
+ }
+ }
+ }
++
++ /*
++ * Scale fabrics with max freq across all cores
++ */
++ ret = scale_fabrics(target_freq);
++ if (ret)
++ goto exit;
+ }
+ priv->opp_freq = freq * 1000;
+ arch_set_freq_scale(policy->related_cpus, freq,
--- /dev/null
+From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
+From: Lina Iyer <lina.iyer@linaro.org>
+Date: Wed, 25 Mar 2015 14:25:29 -0600
+Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
+
+Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
+
+Cc: Stephen Boyd <sboyd@codeaurora.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Kevin Hilman <khilman@linaro.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
+---
+ drivers/cpuidle/Kconfig.arm | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/cpuidle/Kconfig.arm
++++ b/drivers/cpuidle/Kconfig.arm
+@@ -86,3 +86,10 @@ config ARM_MVEBU_V7_CPUIDLE
+ depends on ARCH_MVEBU && !ARM64
+ help
+ Select this to enable cpuidle on Armada 370, 38x and XP processors.
++
++config ARM_QCOM_CPUIDLE
++ bool "CPU Idle Driver for QCOM processors"
++ depends on ARCH_QCOM
++ select ARM_CPUIDLE
++ help
++ Select this to enable cpuidle on QCOM processors.
--- /dev/null
+From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001
+From: Mathieu Olivari <mathieu@codeaurora.org>
+Date: Wed, 29 Apr 2015 15:21:46 -0700
+Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom
+
+ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended
+on most ARM architectures. This automatically calculate ZRELADDR by
+masking PHYS_OFFSET with 0xf8000000.
+
+However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware
+network accelerators, and the bootloader removes this section from the
+layout passed from the ATAGS (when used).
+
+For newer bootloader, when DT is used, this is not a problem, we just
+reserve this memory in the device tree. But if the bootloader doesn't
+have DT support, then ATAGS have to be used. In this case, the ARM
+decompressor will position the kernel in this low mem, which will not be
+in the RAM section mapped by the bootloader, which means the kernel will
+freeze in the middle of the boot process trying to map the memory.
+
+As a work around, this patch allows disabling AUTO_ZRELADDR when
+ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders
+which don't support device-tree, which is the case on certain early
+IPQ806x based designs.
+
+Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+---
+ arch/arm/Kconfig | 2 +-
+ arch/arm/Makefile | 2 ++
+ arch/arm/mach-qcom/Makefile.boot | 1 +
+ 3 files changed, 4 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/mach-qcom/Makefile.boot
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -318,7 +318,7 @@ config ARCH_MULTIPLATFORM
+ depends on MMU
+ select ARM_HAS_SG_CHAIN
+ select ARM_PATCH_PHYS_VIRT
+- select AUTO_ZRELADDR
++ select AUTO_ZRELADDR if !ARCH_QCOM
+ select TIMER_OF
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -258,9 +258,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac
+ else
+ MACHINE :=
+ endif
++ifeq ($(CONFIG_ARCH_QCOM),)
+ ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+ MACHINE :=
+ endif
++endif
+
+ machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
+ platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
+--- /dev/null
++++ b/arch/arm/mach-qcom/Makefile.boot
+@@ -0,0 +1 @@
++zreladdr-y+= 0x42208000
--- /dev/null
+From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 09:31:44 +0100
+Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/mtd/parsers/qcom_smem_part.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mtd/parsers/qcom_smem_part.c
++++ b/drivers/mtd/parsers/qcom_smem_part.c
+@@ -189,6 +189,10 @@ static int parse_qcom_smem_partitions(st
+ m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz);
+ m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz);
+
++ /* "rootfs" conflicts with OpenWrt auto mounting */
++ if (mtd_type_is_nand(master) && !strcmp(m_part->name, "rootfs"))
++ m_part->name = "ubi";
++
+ /*
+ * The last SMEM partition may have its size marked as
+ * something like 0xffffffff, which means "until the end of the
--- /dev/null
+From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001
+From: Rajith Cherian <rajith@codeaurora.org>
+Date: Tue, 14 Feb 2017 18:30:43 +0530
+Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064
+
+Add TSENS driver template to support IPQ8064.
+This is a base file copied from tsens-8960.c
+
+Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7
+Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
+
+ipq8064: tsens: TSENS driver support for IPQ8064
+
+Support for IPQ8064 tsens driver. The driver works
+with the thermal framework. The driver overrides the
+following fucntionalities:
+
+1. Get current temperature.
+2. Get/Set trip temperatures.
+3. Enabled/Disable trip points.
+4. ISR for threshold generated interrupt.
+5. Notify userspace when trip points are hit.
+
+Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918
+Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
+---
+
+--- a/drivers/thermal/qcom/Makefile
++++ b/drivers/thermal/qcom/Makefile
+@@ -2,5 +2,5 @@
+ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
+
+ qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
+- tsens-8960.o tsens-v2.o tsens-v1.o
++ tsens-8960.o tsens-v2.o tsens-v1.o tsens-ipq8064.o
+ obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
+--- /dev/null
++++ b/drivers/thermal/qcom/tsens-ipq8064.c
+@@ -0,0 +1,551 @@
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/bitops.h>
++#include <linux/regmap.h>
++#include <linux/thermal.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include "tsens.h"
++
++#define CAL_MDEGC 30000
++
++#define CONFIG_ADDR 0x3640
++/* CONFIG_ADDR bitmasks */
++#define CONFIG 0x9b
++#define CONFIG_MASK 0xf
++#define CONFIG_SHIFT 0
++
++#define STATUS_CNTL_8064 0x3660
++#define CNTL_ADDR 0x3620
++/* CNTL_ADDR bitmasks */
++#define EN BIT(0)
++#define SW_RST BIT(1)
++#define SENSOR0_EN BIT(3)
++#define SLP_CLK_ENA BIT(26)
++#define MEASURE_PERIOD 1
++#define SENSOR0_SHIFT 3
++
++/* INT_STATUS_ADDR bitmasks */
++#define MIN_STATUS_MASK BIT(0)
++#define LOWER_STATUS_CLR BIT(1)
++#define UPPER_STATUS_CLR BIT(2)
++#define MAX_STATUS_MASK BIT(3)
++
++#define THRESHOLD_ADDR 0x3624
++/* THRESHOLD_ADDR bitmasks */
++#define THRESHOLD_MAX_CODE 0x20000
++#define THRESHOLD_MIN_CODE 0
++#define THRESHOLD_MAX_LIMIT_SHIFT 24
++#define THRESHOLD_MIN_LIMIT_SHIFT 16
++#define THRESHOLD_UPPER_LIMIT_SHIFT 8
++#define THRESHOLD_LOWER_LIMIT_SHIFT 0
++#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \
++ THRESHOLD_MAX_LIMIT_SHIFT)
++#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \
++ THRESHOLD_MIN_LIMIT_SHIFT)
++#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
++ THRESHOLD_UPPER_LIMIT_SHIFT)
++#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
++ THRESHOLD_LOWER_LIMIT_SHIFT)
++
++/* Initial temperature threshold values */
++#define LOWER_LIMIT_TH 0x9d /* 95C */
++#define UPPER_LIMIT_TH 0xa6 /* 105C */
++#define MIN_LIMIT_TH 0x0
++#define MAX_LIMIT_TH 0xff
++
++#define S0_STATUS_ADDR 0x3628
++#define STATUS_ADDR_OFFSET 2
++#define SENSOR_STATUS_SIZE 4
++#define INT_STATUS_ADDR 0x363c
++#define TRDY_MASK BIT(7)
++#define TIMEOUT_US 100
++
++#define TSENS_EN BIT(0)
++#define TSENS_SW_RST BIT(1)
++#define TSENS_ADC_CLK_SEL BIT(2)
++#define SENSOR0_EN BIT(3)
++#define SENSOR1_EN BIT(4)
++#define SENSOR2_EN BIT(5)
++#define SENSOR3_EN BIT(6)
++#define SENSOR4_EN BIT(7)
++#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \
++ SENSOR2_EN | SENSOR3_EN | SENSOR4_EN)
++#define TSENS_8064_SENSOR5_EN BIT(8)
++#define TSENS_8064_SENSOR6_EN BIT(9)
++#define TSENS_8064_SENSOR7_EN BIT(10)
++#define TSENS_8064_SENSOR8_EN BIT(11)
++#define TSENS_8064_SENSOR9_EN BIT(12)
++#define TSENS_8064_SENSOR10_EN BIT(13)
++#define TSENS_8064_SENSORS_EN (SENSORS_EN | \
++ TSENS_8064_SENSOR5_EN | \
++ TSENS_8064_SENSOR6_EN | \
++ TSENS_8064_SENSOR7_EN | \
++ TSENS_8064_SENSOR8_EN | \
++ TSENS_8064_SENSOR9_EN | \
++ TSENS_8064_SENSOR10_EN)
++
++#define TSENS_8064_SEQ_SENSORS 5
++#define TSENS_8064_S4_S5_OFFSET 40
++#define TSENS_FACTOR 1
++
++/* Trips: from very hot to very cold */
++enum tsens_trip_type {
++ TSENS_TRIP_STAGE3 = 0,
++ TSENS_TRIP_STAGE2,
++ TSENS_TRIP_STAGE1,
++ TSENS_TRIP_STAGE0,
++ TSENS_TRIP_NUM,
++};
++
++u32 tsens_8064_slope[] = {
++ 1176, 1176, 1154, 1176,
++ 1111, 1132, 1132, 1199,
++ 1132, 1199, 1132
++ };
++
++/* Temperature on y axis and ADC-code on x-axis */
++static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s)
++{
++ int degcbeforefactor, degc;
++
++ degcbeforefactor = (adc_code * s->slope) + s->offset;
++
++ if (degcbeforefactor == 0)
++ degc = degcbeforefactor;
++ else if (degcbeforefactor > 0)
++ degc = (degcbeforefactor + TSENS_FACTOR/2)
++ / TSENS_FACTOR;
++ else
++ degc = (degcbeforefactor - TSENS_FACTOR/2)
++ / TSENS_FACTOR;
++
++ return degc;
++}
++
++static int degC_to_code(int degC, const struct tsens_sensor *s)
++{
++ int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2))
++ / s->slope;
++
++ if (code > THRESHOLD_MAX_CODE)
++ code = THRESHOLD_MAX_CODE;
++ else if (code < THRESHOLD_MIN_CODE)
++ code = THRESHOLD_MIN_CODE;
++ return code;
++}
++
++static int suspend_ipq8064(struct tsens_priv *priv)
++{
++ int ret;
++ unsigned int mask;
++ struct regmap *map = priv->tm_map;
++
++ ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
++ if (ret)
++ return ret;
++
++ ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
++ if (ret)
++ return ret;
++
++ mask = SLP_CLK_ENA | EN;
++
++ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int resume_ipq8064(struct tsens_priv *priv)
++{
++ int ret;
++ struct regmap *map = priv->tm_map;
++
++ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
++ if (ret)
++ return ret;
++
++ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
++ if (ret)
++ return ret;
++
++ ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
++ if (ret)
++ return ret;
++
++ ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static void notify_uspace_tsens_fn(struct work_struct *work)
++{
++ struct tsens_sensor *s = container_of(work, struct tsens_sensor,
++ notify_work);
++
++ sysfs_notify(&s->tzd->device.kobj, NULL, "type");
++}
++
++static void tsens_scheduler_fn(struct work_struct *work)
++{
++ struct tsens_priv *priv = container_of(work, struct tsens_priv,
++ tsens_work);
++ unsigned int threshold, threshold_low, code, reg, sensor, mask;
++ unsigned int sensor_addr;
++ bool upper_th_x, lower_th_x;
++ int adc_code, ret;
++
++ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®);
++ if (ret)
++ return;
++ reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR;
++ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, reg);
++ if (ret)
++ return;
++
++ mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR);
++ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold);
++ if (ret)
++ return;
++ threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK)
++ >> THRESHOLD_LOWER_LIMIT_SHIFT;
++ threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK)
++ >> THRESHOLD_UPPER_LIMIT_SHIFT;
++
++ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®);
++ if (ret)
++ return;
++
++ ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor);
++ if (ret)
++ return;
++ sensor &= (uint32_t) TSENS_8064_SENSORS_EN;
++ sensor >>= SENSOR0_SHIFT;
++
++ /* Constraint: There is only 1 interrupt control register for all
++ * 11 temperature sensor. So monitoring more than 1 sensor based
++ * on interrupts will yield inconsistent result. To overcome this
++ * issue we will monitor only sensor 0 which is the master sensor.
++ */
++
++ /* Skip if the sensor is disabled */
++ if (sensor & 1) {
++ ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code);
++ if (ret)
++ return;
++ upper_th_x = code >= threshold;
++ lower_th_x = code <= threshold_low;
++ if (upper_th_x)
++ mask |= UPPER_STATUS_CLR;
++ if (lower_th_x)
++ mask |= LOWER_STATUS_CLR;
++ if (upper_th_x || lower_th_x) {
++ /* Notify user space */
++ schedule_work(&priv->sensor[0].notify_work);
++ regmap_read(priv->tm_map, sensor_addr, &adc_code);
++ pr_debug("Trigger (%d degrees) for sensor %d\n",
++ code_to_degC(adc_code, &priv->sensor[0]), 0);
++ }
++ }
++ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
++
++ /* force memory to sync */
++ mb();
++}
++
++static irqreturn_t tsens_isr(int irq, void *data)
++{
++ struct tsens_priv *priv = data;
++
++ schedule_work(&priv->tsens_work);
++ return IRQ_HANDLED;
++}
++
++static void hw_init(struct tsens_priv *priv)
++{
++ int ret;
++ unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0;
++ unsigned int reg_status_cntl = 0;
++
++ regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl);
++ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST);
++
++ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18)
++ | (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT);
++ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
++ regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_status_cntl);
++ reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR
++ | MIN_STATUS_MASK | MAX_STATUS_MASK;
++ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg_status_cntl);
++ reg_cntl |= TSENS_EN;
++ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
++
++ regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg);
++ reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT);
++ regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg);
++
++ reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT)
++ | (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT)
++ | (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT)
++ | (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT);
++
++ regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr);
++
++ ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr,
++ IRQF_TRIGGER_RISING, "tsens_interrupt", priv);
++ if (ret < 0) {
++ pr_err("%s: request_irq FAIL: %d\n", __func__, ret);
++ return;
++ }
++
++ INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
++}
++
++static int init_ipq8064(struct tsens_priv *priv)
++{
++ int ret, i;
++ u32 reg_cntl, offset = 0;
++
++ init_common(priv);
++ if (!priv->tm_map)
++ return -ENODEV;
++
++ /*
++ * The status registers for each sensor are discontiguous
++ * because some SoCs have 5 sensors while others have more
++ * but the control registers stay in the same place, i.e
++ * directly after the first 5 status registers.
++ */
++ for (i = 0; i < priv->num_sensors; i++) {
++ if (i >= TSENS_8064_SEQ_SENSORS)
++ offset = TSENS_8064_S4_S5_OFFSET;
++
++ priv->sensor[i].status = S0_STATUS_ADDR + offset
++ + (i << STATUS_ADDR_OFFSET);
++ priv->sensor[i].slope = tsens_8064_slope[i];
++ INIT_WORK(&priv->sensor[i].notify_work,
++ notify_uspace_tsens_fn);
++ }
++
++ reg_cntl = SW_RST;
++ ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
++ if (ret)
++ return ret;
++
++ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
++ reg_cntl &= ~SW_RST;
++ ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
++ CONFIG_MASK, CONFIG);
++
++ reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
++ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
++ if (ret)
++ return ret;
++
++ reg_cntl |= EN;
++ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int calibrate_ipq8064(struct tsens_priv *priv)
++{
++ int i;
++ char *data, *data_backup;
++
++ ssize_t num_read = priv->num_sensors;
++ struct tsens_sensor *s = priv->sensor;
++
++ data = qfprom_read(priv->dev, "calib");
++ if (IS_ERR(data)) {
++ pr_err("Calibration not found.\n");
++ return PTR_ERR(data);
++ }
++
++ data_backup = qfprom_read(priv->dev, "calib_backup");
++ if (IS_ERR(data_backup)) {
++ pr_err("Backup calibration not found.\n");
++ return PTR_ERR(data_backup);
++ }
++
++ for (i = 0; i < num_read; i++) {
++ s[i].calib_data = readb_relaxed(data + i);
++ s[i].calib_data_backup = readb_relaxed(data_backup + i);
++
++ if (s[i].calib_data_backup)
++ s[i].calib_data = s[i].calib_data_backup;
++ if (!s[i].calib_data) {
++ pr_err("QFPROM TSENS calibration data not present\n");
++ return -ENODEV;
++ }
++ s[i].slope = tsens_8064_slope[i];
++ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
++ }
++
++ hw_init(priv);
++
++ return 0;
++}
++
++static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
++{
++ int ret;
++ u32 code, trdy;
++ const struct tsens_sensor *s = &priv->sensor[id];
++ unsigned long timeout;
++
++ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
++ do {
++ ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
++ if (ret)
++ return ret;
++ if (!(trdy & TRDY_MASK))
++ continue;
++ ret = regmap_read(priv->tm_map, s->status, &code);
++ if (ret)
++ return ret;
++ *temp = code_to_degC(code, s);
++ return 0;
++ } while (time_before(jiffies, timeout));
++
++ return -ETIMEDOUT;
++}
++
++static int set_trip_temp_ipq8064(void *data, int trip, int temp)
++{
++ unsigned int reg_th, reg_cntl;
++ int ret, code, code_chk, hi_code, lo_code;
++ const struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
++
++ code_chk = code = degC_to_code(temp, s);
++
++ if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE)
++ return -EINVAL;
++
++ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_cntl);
++ if (ret)
++ return ret;
++
++ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th);
++ if (ret)
++ return ret;
++
++ hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK)
++ >> THRESHOLD_UPPER_LIMIT_SHIFT;
++ lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK)
++ >> THRESHOLD_LOWER_LIMIT_SHIFT;
++
++ switch (trip) {
++ case TSENS_TRIP_STAGE3:
++ code <<= THRESHOLD_MAX_LIMIT_SHIFT;
++ reg_th &= ~THRESHOLD_MAX_LIMIT_MASK;
++ break;
++ case TSENS_TRIP_STAGE2:
++ if (code_chk <= lo_code)
++ return -EINVAL;
++ code <<= THRESHOLD_UPPER_LIMIT_SHIFT;
++ reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK;
++ break;
++ case TSENS_TRIP_STAGE1:
++ if (code_chk >= hi_code)
++ return -EINVAL;
++ code <<= THRESHOLD_LOWER_LIMIT_SHIFT;
++ reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK;
++ break;
++ case TSENS_TRIP_STAGE0:
++ code <<= THRESHOLD_MIN_LIMIT_SHIFT;
++ reg_th &= ~THRESHOLD_MIN_LIMIT_MASK;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int set_trip_activate_ipq8064(void *data, int trip,
++ enum thermal_trip_activation_mode mode)
++{
++ unsigned int reg_cntl, mask, val;
++ const struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
++ int ret;
++
++ if (!priv || trip < 0)
++ return -EINVAL;
++
++ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_cntl);
++ if (ret)
++ return ret;
++
++ switch (trip) {
++ case TSENS_TRIP_STAGE3:
++ mask = MAX_STATUS_MASK;
++ break;
++ case TSENS_TRIP_STAGE2:
++ mask = UPPER_STATUS_CLR;
++ break;
++ case TSENS_TRIP_STAGE1:
++ mask = LOWER_STATUS_CLR;
++ break;
++ case TSENS_TRIP_STAGE0:
++ mask = MIN_STATUS_MASK;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (mode == THERMAL_TRIP_ACTIVATION_DISABLED)
++ val = reg_cntl | mask;
++ else
++ val = reg_cntl & ~mask;
++
++ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, val);
++ if (ret)
++ return ret;
++
++ /* force memory to sync */
++ mb();
++ return 0;
++}
++
++const struct tsens_ops ops_ipq8064 = {
++ .init = init_ipq8064,
++ .calibrate = calibrate_ipq8064,
++ .get_temp = get_temp_ipq8064,
++ .suspend = suspend_ipq8064,
++ .resume = resume_ipq8064,
++ .set_trip_temp = set_trip_temp_ipq8064,
++ .set_trip_activate = set_trip_activate_ipq8064,
++};
++
++const struct tsens_plat_data data_ipq8064 = {
++ .num_sensors = 11,
++ .ops = &ops_ipq8064,
++};
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -69,8 +69,11 @@ static const struct of_device_id tsens_t
+ }, {
+ .compatible = "qcom,tsens-v2",
+ .data = &data_tsens_v2,
++ }, {
++ .compatible = "qcom,ipq8064-tsens",
++ .data = &data_ipq8064,
+ },
+- {}
++ {}
+ };
+ MODULE_DEVICE_TABLE(of, tsens_table);
+
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -324,7 +324,7 @@ extern const struct tsens_plat_data data
+ extern const struct tsens_plat_data data_8916, data_8974;
+
+ /* TSENS v1 targets */
+-extern const struct tsens_plat_data data_tsens_v1;
++extern const struct tsens_plat_data data_tsens_v1, data_ipq8064;
+
+ /* TSENS v2 targets */
+ extern const struct tsens_plat_data data_8996, data_tsens_v2;
--- /dev/null
+From 4e87400732c77765afae2ea89ed43837457aa604 Mon Sep 17 00:00:00 2001
+From: Rajith Cherian <rajith@codeaurora.org>
+Date: Wed, 1 Feb 2017 19:00:26 +0530
+Subject: [PATCH] ipq8064: tsens: Support for configurable interrupts
+
+Provide support for adding configurable high and
+configurable low trip temperatures. An interrupts is
+also triggerred when these trip points are hit. The
+interrupts can be activated or deactivated from sysfs.
+This functionality is made available only if
+CONFIG_THERMAL_WRITABLE_TRIPS is defined.
+
+Change-Id: Ib73f3f9459de4fffce7bb985a0312a88291f4934
+Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
+---
+ .../devicetree/bindings/thermal/qcom-tsens.txt | 4 ++
+ drivers/thermal/of-thermal.c | 63 ++++++++++++++++++----
+ drivers/thermal/qcom/tsens.c | 43 ++++++++++++---
+ drivers/thermal/qcom/tsens.h | 11 ++++
+ drivers/thermal/thermal_core.c | 44 ++++++++++++++-
+ include/linux/thermal.h | 14 +++++
+ 6 files changed, 162 insertions(+), 17 deletions(-)
+
+--- a/drivers/thermal/of-thermal.c
++++ b/drivers/thermal/of-thermal.c
+@@ -91,7 +91,7 @@ static int of_thermal_get_temp(struct th
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (!data->ops->get_temp)
++ if (!data->ops->get_temp || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EINVAL;
+
+ return data->ops->get_temp(data->sensor_data, temp);
+@@ -102,7 +102,8 @@ static int of_thermal_set_trips(struct t
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (!data->ops || !data->ops->set_trips)
++ if (!data->ops || !data->ops->set_trips
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EINVAL;
+
+ return data->ops->set_trips(data->sensor_data, low, high);
+@@ -188,6 +189,9 @@ static int of_thermal_set_emul_temp(stru
+ {
+ struct __thermal_zone *data = tz->devdata;
+
++ if (data->mode == THERMAL_DEVICE_DISABLED)
++ return -EINVAL;
++
+ return data->ops->set_emul_temp(data->sensor_data, temp);
+ }
+
+@@ -196,7 +200,7 @@ static int of_thermal_get_trend(struct t
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (!data->ops->get_trend)
++ if (!data->ops->get_trend || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EINVAL;
+
+ return data->ops->get_trend(data->sensor_data, trip, trend);
+@@ -297,7 +301,9 @@ static int of_thermal_set_mode(struct th
+ mutex_unlock(&tz->lock);
+
+ data->mode = mode;
+- thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
++
++ if (mode == THERMAL_DEVICE_ENABLED)
++ thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
+
+ return 0;
+ }
+@@ -307,7 +313,8 @@ static int of_thermal_get_trip_type(stru
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (trip >= data->ntrips || trip < 0)
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ *type = data->trips[trip].type;
+@@ -315,12 +322,39 @@ static int of_thermal_get_trip_type(stru
+ return 0;
+ }
+
++static int of_thermal_activate_trip_type(struct thermal_zone_device *tz,
++ int trip, enum thermal_trip_activation_mode mode)
++{
++ struct __thermal_zone *data = tz->devdata;
++
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
++ return -EDOM;
++
++ /*
++ * The configurable_hi and configurable_lo trip points can be
++ * activated and deactivated.
++ */
++
++ if (data->ops->set_trip_activate) {
++ int ret;
++
++ ret = data->ops->set_trip_activate(data->sensor_data,
++ trip, mode);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
+ static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip,
+ int *temp)
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (trip >= data->ntrips || trip < 0)
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ *temp = data->trips[trip].temperature;
+@@ -333,7 +367,8 @@ static int of_thermal_set_trip_temp(stru
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (trip >= data->ntrips || trip < 0)
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ if (data->ops->set_trip_temp) {
+@@ -355,7 +390,8 @@ static int of_thermal_get_trip_hyst(stru
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (trip >= data->ntrips || trip < 0)
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ *hyst = data->trips[trip].hysteresis;
+@@ -368,7 +404,8 @@ static int of_thermal_set_trip_hyst(stru
+ {
+ struct __thermal_zone *data = tz->devdata;
+
+- if (trip >= data->ntrips || trip < 0)
++ if (trip >= data->ntrips || trip < 0
++ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ /* thermal framework should take care of data->mask & (1 << trip) */
+@@ -443,6 +480,9 @@ thermal_zone_of_add_sensor(struct device
+ if (ops->set_emul_temp)
+ tzd->ops->set_emul_temp = of_thermal_set_emul_temp;
+
++ if (ops->set_trip_activate)
++ tzd->ops->set_trip_activate = of_thermal_activate_trip_type;
++
+ mutex_unlock(&tzd->lock);
+
+ return tzd;
+@@ -762,7 +802,10 @@ static const char * const trip_types[] =
+ [THERMAL_TRIP_ACTIVE] = "active",
+ [THERMAL_TRIP_PASSIVE] = "passive",
+ [THERMAL_TRIP_HOT] = "hot",
+- [THERMAL_TRIP_CRITICAL] = "critical",
++ [THERMAL_TRIP_CRITICAL] = "critical_high",
++ [THERMAL_TRIP_CONFIGURABLE_HI] = "configurable_hi",
++ [THERMAL_TRIP_CONFIGURABLE_LOW] = "configurable_lo",
++ [THERMAL_TRIP_CRITICAL_LOW] = "critical_low",
+ };
+
+ /**
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -22,7 +22,7 @@ static int tsens_get_temp(void *data, in
+
+ static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend)
+ {
+- const struct tsens_sensor *s = data;
++ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops->get_trend)
+@@ -31,9 +31,10 @@ static int tsens_get_trend(void *data, i
+ return -ENOTSUPP;
+ }
+
+-static int __maybe_unused tsens_suspend(struct device *dev)
++static int __maybe_unused tsens_suspend(void *data)
+ {
+- struct tsens_priv *priv = dev_get_drvdata(dev);
++ struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->suspend)
+ return priv->ops->suspend(priv);
+@@ -41,9 +42,10 @@ static int __maybe_unused tsens_suspend
+ return 0;
+ }
+
+-static int __maybe_unused tsens_resume(struct device *dev)
++static int __maybe_unused tsens_resume(void *data)
+ {
+- struct tsens_priv *priv = dev_get_drvdata(dev);
++ struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->resume)
+ return priv->ops->resume(priv);
+@@ -51,6 +53,30 @@ static int __maybe_unused tsens_resume(s
+ return 0;
+ }
+
++static int __maybe_unused tsens_set_trip_temp(void *data, int trip, int temp)
++{
++ struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
++
++ if (priv->ops && priv->ops->set_trip_temp)
++ return priv->ops->set_trip_temp(s, trip, temp);
++
++ return 0;
++}
++
++static int __maybe_unused tsens_activate_trip_type(void *data, int trip,
++ enum thermal_trip_activation_mode mode)
++{
++ struct tsens_sensor *s = data;
++ struct tsens_priv *priv = s->priv;
++
++ if (priv->ops && priv->ops->set_trip_activate)
++ return priv->ops->set_trip_activate(s, trip, mode);
++
++ return 0;
++}
++
++
+ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
+
+ static const struct of_device_id tsens_table[] = {
+@@ -80,6 +106,8 @@ MODULE_DEVICE_TABLE(of, tsens_table);
+ static const struct thermal_zone_of_device_ops tsens_of_ops = {
+ .get_temp = tsens_get_temp,
+ .get_trend = tsens_get_trend,
++ .set_trip_temp = tsens_set_trip_temp,
++ .set_trip_activate = tsens_activate_trip_type,
+ };
+
+ static int tsens_register(struct tsens_priv *priv)
+@@ -123,7 +151,7 @@ static int tsens_probe(struct platform_d
+ if (id)
+ data = id->data;
+ else
+- data = &data_8960;
++ return -EINVAL;
+
+ num_sensors = data->num_sensors;
+
+@@ -144,6 +172,9 @@ static int tsens_probe(struct platform_d
+ priv->dev = dev;
+ priv->num_sensors = num_sensors;
+ priv->ops = data->ops;
++
++ priv->tsens_irq = platform_get_irq(pdev, 0);
++
+ for (i = 0; i < priv->num_sensors; i++) {
+ if (data->hw_ids)
+ priv->sensor[i].hw_id = data->hw_ids[i];
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -40,9 +40,12 @@ enum tsens_ver {
+ struct tsens_sensor {
+ struct tsens_priv *priv;
+ struct thermal_zone_device *tzd;
++ struct work_struct notify_work;
+ int offset;
+ unsigned int id;
+ unsigned int hw_id;
++ int calib_data;
++ int calib_data_backup;
+ int slope;
+ u32 status;
+ };
+@@ -57,6 +60,9 @@ struct tsens_sensor {
+ * @suspend: Function to suspend the tsens device
+ * @resume: Function to resume the tsens device
+ * @get_trend: Function to get the thermal/temp trend
++ * @set_trip_temp: Function to set trip temp
++ * @get_trip_temp: Function to get trip temp
++ * @set_trip_activate: Function to activate trip points
+ */
+ struct tsens_ops {
+ /* mandatory callbacks */
+@@ -69,6 +75,9 @@ struct tsens_ops {
+ int (*suspend)(struct tsens_priv *priv);
+ int (*resume)(struct tsens_priv *priv);
+ int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend);
++ int (*set_trip_temp)(void *data, int trip, int temp);
++ int (*set_trip_activate)(void *data, int trip,
++ enum thermal_trip_activation_mode mode);
+ };
+
+ #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
+@@ -300,6 +309,7 @@ struct tsens_context {
+ struct tsens_priv {
+ struct device *dev;
+ u32 num_sensors;
++ u32 tsens_irq;
+ struct regmap *tm_map;
+ struct regmap *srot_map;
+ u32 tm_offset;
+@@ -308,6 +318,7 @@ struct tsens_priv {
+ const struct tsens_features *feat;
+ const struct reg_field *fields;
+ const struct tsens_ops *ops;
++ struct work_struct tsens_work;
+ struct tsens_sensor sensor[0];
+ };
+
+--- a/drivers/thermal/thermal_sysfs.c
++++ b/drivers/thermal/thermal_sysfs.c
+@@ -113,12 +113,48 @@ trip_point_type_show(struct device *dev,
+ return sprintf(buf, "passive\n");
+ case THERMAL_TRIP_ACTIVE:
+ return sprintf(buf, "active\n");
++ case THERMAL_TRIP_CONFIGURABLE_HI:
++ return sprintf(buf, "configurable_hi\n");
++ case THERMAL_TRIP_CONFIGURABLE_LOW:
++ return sprintf(buf, "configurable_low\n");
++ case THERMAL_TRIP_CRITICAL_LOW:
++ return sprintf(buf, "critical_low\n");
+ default:
+ return sprintf(buf, "unknown\n");
+ }
+ }
+
+ static ssize_t
++trip_point_type_activate(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct thermal_zone_device *tz = to_thermal_zone(dev);
++ int trip, ret;
++ char *enabled = "enabled";
++ char *disabled = "disabled";
++
++ if (!tz->ops->set_trip_activate)
++ return -EPERM;
++
++ if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip))
++ return -EINVAL;
++
++ if (!strncmp(buf, enabled, strlen(enabled)))
++ ret = tz->ops->set_trip_activate(tz, trip,
++ THERMAL_TRIP_ACTIVATION_ENABLED);
++ else if (!strncmp(buf, disabled, strlen(disabled)))
++ ret = tz->ops->set_trip_activate(tz, trip,
++ THERMAL_TRIP_ACTIVATION_DISABLED);
++ else
++ ret = -EINVAL;
++
++ if (ret)
++ return ret;
++
++ return count;
++}
++
++static ssize_t
+ trip_point_temp_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+ {
+@@ -559,6 +595,12 @@ static int create_trip_attrs(struct ther
+ tz->trip_type_attrs[indx].attr.show = trip_point_type_show;
+ attrs[indx] = &tz->trip_type_attrs[indx].attr.attr;
+
++ if (IS_ENABLED(CONFIG_THERMAL_WRITABLE_TRIPS)) {
++ tz->trip_type_attrs[indx].attr.store
++ = trip_point_type_activate;
++ tz->trip_type_attrs[indx].attr.attr.mode |= S_IWUSR;
++ }
++
+ /* create trip temp attribute */
+ snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH,
+ "trip_point_%d_temp", indx);
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -63,11 +63,19 @@ enum thermal_device_mode {
+ THERMAL_DEVICE_ENABLED,
+ };
+
++enum thermal_trip_activation_mode {
++ THERMAL_TRIP_ACTIVATION_DISABLED = 0,
++ THERMAL_TRIP_ACTIVATION_ENABLED,
++};
++
+ enum thermal_trip_type {
+ THERMAL_TRIP_ACTIVE = 0,
+ THERMAL_TRIP_PASSIVE,
+ THERMAL_TRIP_HOT,
+ THERMAL_TRIP_CRITICAL,
++ THERMAL_TRIP_CONFIGURABLE_HI,
++ THERMAL_TRIP_CONFIGURABLE_LOW,
++ THERMAL_TRIP_CRITICAL_LOW,
+ };
+
+ enum thermal_trend {
+@@ -105,6 +113,8 @@ struct thermal_zone_device_ops {
+ enum thermal_trip_type *);
+ int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
+ int (*set_trip_temp) (struct thermal_zone_device *, int, int);
++ int (*set_trip_activate) (struct thermal_zone_device *, int,
++ enum thermal_trip_activation_mode);
+ int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
+ int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
+ int (*get_crit_temp) (struct thermal_zone_device *, int *);
+@@ -349,6 +359,8 @@ struct thermal_genl_event {
+ * temperature.
+ * @set_trip_temp: a pointer to a function that sets the trip temperature on
+ * hardware.
++ * @activate_trip_type: a pointer to a function to enable/disable trip
++ * temperature interrupts
+ */
+ struct thermal_zone_of_device_ops {
+ int (*get_temp)(void *, int *);
+@@ -356,6 +368,8 @@ struct thermal_zone_of_device_ops {
+ int (*set_trips)(void *, int, int);
+ int (*set_emul_temp)(void *, int);
+ int (*set_trip_temp)(void *, int, int);
++ int (*set_trip_activate)(void *, int,
++ enum thermal_trip_activation_mode);
+ };
+
+ /**
--- /dev/null
+--- a/drivers/thermal/qcom/tsens-ipq8064.c
++++ b/drivers/thermal/qcom/tsens-ipq8064.c
+@@ -18,6 +18,7 @@
+ #include <linux/regmap.h>
+ #include <linux/thermal.h>
+ #include <linux/nvmem-consumer.h>
++#include <linux/of_platform.h>
+ #include <linux/io.h>
+ #include <linux/interrupt.h>
+ #include "tsens.h"
+@@ -320,15 +321,42 @@ static void hw_init(struct tsens_priv *p
+ INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
+ }
+
++static const struct regmap_config tsens_config = {
++ .name = "tm",
++ .reg_bits = 32,
++ .val_bits = 32,
++ .reg_stride = 4,
++};
++
+ static int init_ipq8064(struct tsens_priv *priv)
+ {
+- int ret, i;
++ struct device *dev = priv->dev;
+ u32 reg_cntl, offset = 0;
++ struct resource *res;
++ resource_size_t size;
++ void __iomem *base;
++ int ret, i;
++ struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
++
++ if (!op)
++ return -EINVAL;
+
+- init_common(priv);
+- if (!priv->tm_map)
+- return -ENODEV;
++ /* old DTs where SROT and TM were in a contiguous 2K block */
++ priv->tm_offset = 0x1000;
+
++ res = platform_get_resource(op, IORESOURCE_MEM, 0);
++ size = resource_size(res);
++ base = devm_ioremap(&op->dev, res->start, size);
++ if (IS_ERR(base)) {
++ ret = PTR_ERR(base);
++ goto err_put_device;
++ }
++
++ priv->tm_map = devm_regmap_init_mmio(dev, base, &tsens_config);
++ if (IS_ERR(priv->tm_map)) {
++ ret = PTR_ERR(priv->tm_map);
++ goto err_put_device;
++ }
+ /*
+ * The status registers for each sensor are discontiguous
+ * because some SoCs have 5 sensors while others have more
+@@ -367,6 +395,10 @@ static int init_ipq8064(struct tsens_pri
+ return ret;
+
+ return 0;
++
++err_put_device:
++ put_device(&op->dev);
++ return ret;
+ }
+
+ static int calibrate_ipq8064(struct tsens_priv *priv)
--- /dev/null
+--- a/drivers/thermal/qcom/tsens-ipq8064.c
++++ b/drivers/thermal/qcom/tsens-ipq8064.c
+@@ -13,10 +13,12 @@
+ */
+
+ #include <linux/platform_device.h>
++#include <linux/err.h>
+ #include <linux/delay.h>
+ #include <linux/bitops.h>
+ #include <linux/regmap.h>
+ #include <linux/thermal.h>
++#include <linux/slab.h>
+ #include <linux/nvmem-consumer.h>
+ #include <linux/of_platform.h>
+ #include <linux/io.h>
+@@ -211,9 +213,8 @@ static void tsens_scheduler_fn(struct wo
+ struct tsens_priv *priv = container_of(work, struct tsens_priv,
+ tsens_work);
+ unsigned int threshold, threshold_low, code, reg, sensor, mask;
+- unsigned int sensor_addr;
+ bool upper_th_x, lower_th_x;
+- int adc_code, ret;
++ int ret;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®);
+ if (ret)
+@@ -262,9 +263,8 @@ static void tsens_scheduler_fn(struct wo
+ if (upper_th_x || lower_th_x) {
+ /* Notify user space */
+ schedule_work(&priv->sensor[0].notify_work);
+- regmap_read(priv->tm_map, sensor_addr, &adc_code);
+ pr_debug("Trigger (%d degrees) for sensor %d\n",
+- code_to_degC(adc_code, &priv->sensor[0]), 0);
++ code_to_degC(code, &priv->sensor[0]), 0);
+ }
+ }
+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
+@@ -404,40 +404,55 @@ err_put_device:
+ static int calibrate_ipq8064(struct tsens_priv *priv)
+ {
+ int i;
+- char *data, *data_backup;
+-
++ int ret = 0;
++ u8 *data, *data_backup;
++ struct device *dev = priv->dev;
+ ssize_t num_read = priv->num_sensors;
+ struct tsens_sensor *s = priv->sensor;
+
+- data = qfprom_read(priv->dev, "calib");
++ data = qfprom_read(dev, "calib");
+ if (IS_ERR(data)) {
+- pr_err("Calibration not found.\n");
+- return PTR_ERR(data);
++ ret = PTR_ERR(data);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "Calibration not found.");
++ goto exit;
+ }
+
+- data_backup = qfprom_read(priv->dev, "calib_backup");
++ data_backup = qfprom_read(dev, "calib_backup");
+ if (IS_ERR(data_backup)) {
+- pr_err("Backup calibration not found.\n");
+- return PTR_ERR(data_backup);
++ ret = PTR_ERR(data_backup);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "Backup Calibration not found.");
++ goto free_data;
+ }
+
+ for (i = 0; i < num_read; i++) {
+ s[i].calib_data = readb_relaxed(data + i);
+- s[i].calib_data_backup = readb_relaxed(data_backup + i);
++
++ if (!s[i].calib_data) {
++ s[i].calib_data_backup = readb_relaxed(data_backup + i);
++
++ if (!s[i].calib_data_backup) {
++ dev_err(dev, "QFPROM TSENS calibration data not present");
++ ret = -ENODEV;
++ goto free_backup;
++ }
+
+- if (s[i].calib_data_backup)
+ s[i].calib_data = s[i].calib_data_backup;
+- if (!s[i].calib_data) {
+- pr_err("QFPROM TSENS calibration data not present\n");
+- return -ENODEV;
+ }
++
+ s[i].slope = tsens_8064_slope[i];
+ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
+ }
+
+ hw_init(priv);
+
+- return 0;
++free_backup:
++ kfree(data_backup);
++free_data:
++ kfree(data);
++exit:
++ return ret;
+ }
+
+ static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
--- /dev/null
+From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 09:33:32 +0100
+Subject: [PATCH 65/69] arm: override compiler flags
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -67,7 +67,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+ arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
+-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
++arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15
+ arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7
--- /dev/null
+From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
+From: Adrian Panella <ianchi74@outlook.com>
+Date: Thu, 9 Mar 2017 09:37:17 +0100
+Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
+
+The command-line arguments provided by the boot loader will be
+appended to a new device tree property: bootloader-args.
+If there is a property "append-rootblock" in DT under /chosen
+and a root= option in bootloaders command line it will be parsed
+and added to DT bootargs with the form: <append-rootblock>XX.
+Only command line ATAG will be processed, the rest of the ATAGs
+sent by bootloader will be ignored.
+This is usefull in dual boot systems, to get the current root partition
+without afecting the rest of the system.
+
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+---
+ arch/arm/Kconfig | 11 +++++
+ arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
+ init/main.c | 16 ++++++++
+ 3 files changed, 98 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1827,6 +1827,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+ The command-line arguments provided by the boot loader will be
+ appended to the the device tree bootargs property.
+
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++ bool "Append rootblock parsing bootloader's kernel arguments"
++ help
++ The command-line arguments provided by the boot loader will be
++ appended to a new device tree property: bootloader-args.
++ If there is a property "append-rootblock" in DT under /chosen
++ and a root= option in bootloaders command line it will be parsed
++ and added to DT bootargs with the form: <append-rootblock>XX.
++ Only command line ATAG will be processed, the rest of the ATAGs
++ sent by bootloader will be ignored.
++
+ endchoice
+
+ config CMDLINE
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -4,6 +4,8 @@
+
+ #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
+ #define do_extend_cmdline 1
++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#define do_extend_cmdline 1
+ #else
+ #define do_extend_cmdline 0
+ #endif
+@@ -67,6 +69,80 @@ static uint32_t get_cell_size(const void
+ return cell_size;
+ }
+
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++/**
++ * taken from arch/x86/boot/string.c
++ * local_strstr - Find the first substring in a %NUL terminated string
++ * @s1: The string to be searched
++ * @s2: The string to search for
++ */
++static char *local_strstr(const char *s1, const char *s2)
++{
++ size_t l1, l2;
++
++ l2 = strlen(s2);
++ if (!l2)
++ return (char *)s1;
++ l1 = strlen(s1);
++ while (l1 >= l2) {
++ l1--;
++ if (!memcmp(s1, s2, l2))
++ return (char *)s1;
++ s1++;
++ }
++ return NULL;
++}
++
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
++{
++ char *ptr, *end, *tmp;
++ char *root="root=";
++ char *find_rootblock;
++ int i, l;
++ const char *rootblock;
++
++ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
++ if(!find_rootblock)
++ find_rootblock = root;
++
++ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86
++ ptr = local_strstr(str, find_rootblock);
++
++ if(!ptr)
++ return dest;
++
++ end = strchr(ptr, ' ');
++ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
++
++ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too.
++ tmp = strchr(ptr, ',');
++
++ if(tmp)
++ end = end < tmp ? end : tmp - 1;
++
++ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
++ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
++ ptr = end + 1;
++
++ /* if append-rootblock property is set use it to append to command line */
++ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
++ if(rootblock != NULL) {
++ if(*dest != ' ') {
++ *dest = ' ';
++ dest++;
++ len++;
++ }
++ if (len + l + i <= COMMAND_LINE_SIZE) {
++ memcpy(dest, rootblock, l);
++ dest += l - 1;
++ memcpy(dest, ptr, i);
++ dest += i;
++ }
++ }
++ return dest;
++}
++#endif
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+ char cmdline[COMMAND_LINE_SIZE];
+@@ -86,12 +162,21 @@ static void merge_fdt_bootargs(void *fdt
+
+ /* and append the ATAG_CMDLINE */
+ if (fdt_cmdline) {
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++ //save original bootloader args
++ //and append ubi.mtd with root partition number to current cmdline
++ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
++ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
++
++#else
+ len = strlen(fdt_cmdline);
+ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+ *ptr++ = ' ';
+ memcpy(ptr, fdt_cmdline, len);
+ ptr += len;
+ }
++#endif
+ }
+ *ptr = '\0';
+
+@@ -166,7 +251,9 @@ int atags_to_fdt(void *atag_list, void *
+ else
+ setprop_string(fdt, "/chosen", "bootargs",
+ atag->u.cmdline.cmdline);
+- } else if (atag->hdr.tag == ATAG_MEM) {
++ }
++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++ else if (atag->hdr.tag == ATAG_MEM) {
+ if (memcount >= sizeof(mem_reg_property)/4)
+ continue;
+ if (!atag->u.mem.size)
+@@ -210,6 +297,10 @@ int atags_to_fdt(void *atag_list, void *
+ setprop(fdt, "/memory", "reg", mem_reg_property,
+ 4 * memcount * memsize);
+ }
++#else
++
++ }
++#endif
+
+ return fdt_pack(fdt);
+ }
+--- a/init/main.c
++++ b/init/main.c
+@@ -104,6 +104,10 @@
+ #define CREATE_TRACE_POINTS
+ #include <trace/events/initcall.h>
+
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#include <linux/of.h>
++#endif
++
+ static int kernel_init(void *);
+
+ extern void init_IRQ(void);
+@@ -633,6 +637,18 @@ asmlinkage __visible void __init start_k
+ pr_notice("Kernel command line: %s\n", boot_command_line);
+ /* parameters may set static keys */
+ jump_label_init();
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++ //Show bootloader's original command line for reference
++ if(of_chosen) {
++ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
++ if(prop)
++ pr_notice("Bootloader command line (ignored): %s\n", prop);
++ else
++ pr_notice("Bootloader command line not present\n");
++ }
++#endif
++
+ parse_early_param();
+ after_dashes = parse_args("Booting kernel",
+ static_command_line, __start___param,
--- /dev/null
+From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 11:03:18 +0100
+Subject: [PATCH 69/69] arm: boot: add dts files
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/Makefile | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -842,7 +842,24 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
++ qcom-ipq8062-wg2600hp3.dtb \
+ qcom-ipq8064-ap148.dtb \
++ qcom-ipq8064-c2600.dtb \
++ qcom-ipq8064-d7800.dtb \
++ qcom-ipq8064-db149.dtb \
++ qcom-ipq8064-ap161.dtb \
++ qcom-ipq8064-ea7500-v1.dtb \
++ qcom-ipq8064-ea8500.dtb \
++ qcom-ipq8064-g10.dtb \
++ qcom-ipq8064-r7500.dtb \
++ qcom-ipq8064-r7500v2.dtb \
++ qcom-ipq8064-unifi-ac-hd.dtb \
++ qcom-ipq8064-wg2600hp.dtb \
++ qcom-ipq8064-wpq864.dtb \
++ qcom-ipq8064-wxr-2533dhp.dtb \
++ qcom-ipq8065-nbg6817.dtb \
++ qcom-ipq8065-r7800.dtb \
++ qcom-ipq8068-ecw5410.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb \
+ qcom-msm8974-fairphone-fp2.dtb \
--- /dev/null
+--- a/drivers/firmware/qcom_scm.c
++++ b/drivers/firmware/qcom_scm.c
+@@ -598,6 +598,7 @@ static const struct of_device_id qcom_sc
+ SCM_HAS_BUS_CLK)
+ },
+ { .compatible = "qcom,scm-ipq4019" },
++ { .compatible = "qcom,scm-ipq806x" },
+ { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
+ { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
+ { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
--- /dev/null
+From patchwork Mon May 21 20:57:38 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
+X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
+X-Patchwork-Id: 917856
+Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
+To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
+Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
+ Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
+ Andy Gross <andy.gross@linaro.org>,
+ Sven Eckelmann <sven.eckelmann@openmesh.com>
+Date: Mon, 21 May 2018 22:57:38 +0200
+From: Christian Lamparter <chunkeey@gmail.com>
+List-Id: <linux-gpio.vger.kernel.org>
+
+This patch adds the gpio-ranges property to almost all of
+the Qualcomm ARM platforms that utilize the pinctrl-msm
+framework.
+
+The gpio-ranges property is part of the gpiolib subsystem.
+As a result, the binding text is available in section
+"2.1 gpio- and pin-controller interaction" of
+Documentation/devicetree/bindings/gpio/gpio.txt
+
+For more information please see the patch titled:
+"pinctrl: msm: fix gpio-hog related boot issues" from
+this series.
+
+Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+---
+To help with git bisect, the DT update patch has been intentionally
+placed after the "pinctrl: msm: fix gpio-hog related boot issues".
+Otherwise - if the order was reveresed - and bisect decides to split
+between these two patches, the gpiochip_add_pin_ranges() function
+will be executed twice with the same parameters for the same pinctrl.
+---
+ arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
+ arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
+ arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
+ arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
+ arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
+ arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
+ arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
+ 13 files changed, 14 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -119,6 +119,7 @@
+ reg = <0x800000 0x4000>;
+
+ gpio-controller;
++ gpio-ranges = <&qcom_pinmux 0 0 69>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
--- /dev/null
+From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Thu, 19 Mar 2020 23:44:24 +0100
+Subject: ARM: dts: qcom: add scm definition to ipq806x
+
+Add missing scm definition for ipq806x soc
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -93,6 +93,12 @@
+ };
+ };
+
++ firmware {
++ scm {
++ compatible = "qcom,scm-ipq806x", "qcom,scm";
++ };
++ };
++
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -20,7 +20,7 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+@@ -30,7 +30,7 @@
+ qcom,saw = <&saw0>;
+ };
+
+- cpu@1 {
++ cpu1: cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+@@ -67,7 +67,7 @@
+ no-map;
+ };
+
+- smem@41000000 {
++ smem: smem@41000000 {
+ reg = <0x41000000 0x200000>;
+ no-map;
+ };
+@@ -155,6 +155,7 @@
+ function = "pcie3_rst";
+ drive-strength = <12>;
+ bias-disable;
++ output-low;
+ };
+ };
+
+@@ -219,21 +220,23 @@
+ acc0: clock-controller@2088000 {
+ compatible = "qcom,kpss-acc-v1";
+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
++ clock-output-names = "acpu0_aux";
+ };
+
+ acc1: clock-controller@2098000 {
+ compatible = "qcom,kpss-acc-v1";
+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
++ clock-output-names = "acpu1_aux";
+ };
+
+ saw0: regulator@2089000 {
+- compatible = "qcom,saw2";
++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+ regulator;
+ };
+
+ saw1: regulator@2099000 {
+- compatible = "qcom,saw2";
++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+ regulator;
+ };
+@@ -251,7 +254,7 @@
+
+ syscon-tcsr = <&tcsr>;
+
+- serial@12490000 {
++ gsbi2_serial: serial@12490000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12490000 0x1000>,
+ <0x12480000 0x1000>;
+@@ -326,7 +329,7 @@
+
+ syscon-tcsr = <&tcsr>;
+
+- serial@1a240000 {
++ gsbi5_serial: serial@1a240000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x1a240000 0x1000>,
+ <0x1a200000 0x1000>;
+@@ -397,7 +400,7 @@
+ status = "disabled";
+ };
+
+- sata@29000000 {
++ sata: sata@29000000 {
+ compatible = "qcom,ipq806x-ahci", "generic-ahci";
+ reg = <0x29000000 0x180>;
+
+@@ -430,6 +433,7 @@
+ reg = <0x00900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
++ #power-domain-cells = <1>;
+ };
+
+ tcsr: syscon@1a400000 {
+@@ -625,13 +629,13 @@
+ qcom,ee = <0>;
+ };
+
+- amba {
+- compatible = "simple-bus";
++ amba: amba {
++ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+- sdcc@12400000 {
++ sdcc1: sdcc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+@@ -645,13 +649,12 @@
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+- mmc-ddr-1_8v;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+- sdcc@12180000 {
++ sdcc3: sdcc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -8,6 +8,8 @@
+ #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/mfd/qcom-rpm.h>
++#include <dt-bindings/clock/qcom,rpmcc.h>
+
+ / {
+ #address-cells = <1>;
+@@ -28,6 +30,16 @@
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
++ clocks = <&kraitcc 0>, <&kraitcc 4>;
++ clock-names = "cpu", "l2";
++ clock-latency = <100000>;
++ cpu-supply = <&smb208_s2a>;
++ operating-points-v2 = <&opp_table0>;
++ voltage-tolerance = <5>;
++ cooling-min-state = <0>;
++ cooling-max-state = <10>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ cpu1: cpu@1 {
+@@ -38,11 +50,458 @@
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
++ clocks = <&kraitcc 1>, <&kraitcc 4>;
++ clock-names = "cpu", "l2";
++ clock-latency = <100000>;
++ cpu-supply = <&smb208_s2b>;
++ operating-points-v2 = <&opp_table0>;
++ voltage-tolerance = <5>;
++ cooling-min-state = <0>;
++ cooling-max-state = <10>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
++ qcom,saw = <&saw_l2>;
++ };
++
++ qcom,l2 {
++ qcom,l2-rates = <384000000 1000000000 1200000000>;
++ qcom,l2-cpufreq = <384000000 600000000 1200000000>;
++ qcom,l2-volt = <1100000 1100000 1150000>;
++ qcom,l2-supply = <&smb208_s1a>;
++ };
++
++ idle-states {
++ CPU_SPC: spc {
++ compatible = "qcom,idle-state-spc", "arm,idle-state";
++ status = "disabled";
++ entry-latency-us = <400>;
++ exit-latency-us = <900>;
++ min-residency-us = <3000>;
++ };
++ };
++ };
++
++ opp_table0: opp_table0 {
++ compatible = "operating-points-v2-kryo-cpu";
++ nvmem-cells = <&speedbin_efuse>;
++
++ opp-384000000 {
++ opp-hz = /bits/ 64 <384000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1000000>;
++ opp-microvolt-speed0-pvs1-v0 = <925000>;
++ opp-microvolt-speed0-pvs2-v0 = <875000>;
++ opp-microvolt-speed0-pvs3-v0 = <800000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1050000>;
++ opp-microvolt-speed0-pvs1-v0 = <975000>;
++ opp-microvolt-speed0-pvs2-v0 = <925000>;
++ opp-microvolt-speed0-pvs3-v0 = <850000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++
++ opp-800000000 {
++ opp-hz = /bits/ 64 <800000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1100000>;
++ opp-microvolt-speed0-pvs1-v0 = <1025000>;
++ opp-microvolt-speed0-pvs2-v0 = <995000>;
++ opp-microvolt-speed0-pvs3-v0 = <900000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++
++ opp-1000000000 {
++ opp-hz = /bits/ 64 <1000000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1150000>;
++ opp-microvolt-speed0-pvs1-v0 = <1075000>;
++ opp-microvolt-speed0-pvs2-v0 = <1025000>;
++ opp-microvolt-speed0-pvs3-v0 = <950000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1200000>;
++ opp-microvolt-speed0-pvs1-v0 = <1125000>;
++ opp-microvolt-speed0-pvs2-v0 = <1075000>;
++ opp-microvolt-speed0-pvs3-v0 = <1000000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++
++ opp-1400000000 {
++ opp-hz = /bits/ 64 <1400000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1250000>;
++ opp-microvolt-speed0-pvs1-v0 = <1175000>;
++ opp-microvolt-speed0-pvs2-v0 = <1125000>;
++ opp-microvolt-speed0-pvs3-v0 = <1050000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ };
++ };
++
++ thermal-zones {
++ tsens_tz_sensor0 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 0>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor1 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 1>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor2 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 2>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor3 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 3>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor4 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 4>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor5 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 5>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor6 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 6>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor7 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 7>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor8 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 8>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor9 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 9>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
++ };
++
++ tsens_tz_sensor10 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 10>;
++
++ trips {
++ cpu-critical-hi {
++ temperature = <125000>;
++ hysteresis = <2000>;
++ type = "critical_high";
++ };
++
++ cpu-config-hi {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "configurable_hi";
++ };
++
++ cpu-config-lo {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "configurable_lo";
++ };
++
++ cpu-critical-low {
++ temperature = <0>;
++ hysteresis = <2000>;
++ type = "critical_low";
++ };
++ };
+ };
+ };
+
+@@ -93,6 +552,15 @@
+ };
+ };
+
++ fab-scaling {
++ compatible = "qcom,fab-scaling";
++ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
++ clock-names = "apps-fab-clk", "ddr-fab-clk";
++ fab_freq_high = <533000000>;
++ fab_freq_nominal = <400000000>;
++ cpu_freq_threshold = <1000000000>;
++ };
++
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
+@@ -120,6 +588,84 @@
+ reg-names = "lpass-lpaif";
+ };
+
++ qfprom: qfprom@700000 {
++ compatible = "qcom,qfprom", "syscon";
++ reg = <0x700000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "okay";
++ tsens_calib: calib@400 {
++ reg = <0x400 0xb>;
++ };
++ tsens_backup: backup@410 {
++ reg = <0x410 0xb>;
++ };
++ speedbin_efuse: speedbin@0c0 {
++ reg = <0x0c0 0x4>;
++ };
++ };
++
++ rpm: rpm@108000 {
++ compatible = "qcom,rpm-ipq8064";
++ reg = <0x108000 0x1000>;
++ qcom,ipc = <&l2cc 0x8 2>;
++
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "ack", "err", "wakeup";
++
++ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
++ clock-names = "ram";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rpmcc: clock-controller {
++ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
++ #clock-cells = <1>;
++ };
++
++ regulators {
++ compatible = "qcom,rpm-smb208-regulators";
++
++ smb208_s1a: s1a {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s1b: s1b {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2a: s2a {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2b: s2b {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++ };
++ };
++
++ rng@1a500000 {
++ compatible = "qcom,prng";
++ reg = <0x1a500000 0x200>;
++ clocks = <&gcc PRNG_CLK>;
++ clock-names = "core";
++ };
++
+ qcom_pinmux: pinmux@800000 {
+ compatible = "qcom,ipq8064-pinctrl";
+ reg = <0x800000 0x4000>;
+@@ -159,6 +705,15 @@
+ };
+ };
+
++ i2c4_pins: i2c4_pinmux {
++ mux {
++ pins = "gpio12", "gpio13";
++ function = "gsbi4";
++ drive-strength = <12>;
++ bias-disable;
++ };
++ };
++
+ spi_pins: spi_pins {
+ mux {
+ pins = "gpio18", "gpio19", "gpio21";
+@@ -168,6 +723,53 @@
+ };
+ };
+
++ nand_pins: nand_pins {
++ disable {
++ pins = "gpio34", "gpio35", "gpio36",
++ "gpio37", "gpio38";
++ function = "nand";
++ drive-strength = <10>;
++ bias-disable;
++ };
++
++ pullups {
++ pins = "gpio39";
++ function = "nand";
++ drive-strength = <10>;
++ bias-pull-up;
++ };
++
++ hold {
++ pins = "gpio40", "gpio41", "gpio42",
++ "gpio43", "gpio44", "gpio45",
++ "gpio46", "gpio47";
++ function = "nand";
++ drive-strength = <10>;
++ bias-bus-hold;
++ };
++ };
++
++ mdio0_pins: mdio0_pins {
++ mux {
++ pins = "gpio0", "gpio1";
++ function = "mdio";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ rgmii2_pins: rgmii2_pins {
++ mux {
++ pins = "gpio27", "gpio28", "gpio29",
++ "gpio30", "gpio31", "gpio32",
++ "gpio51", "gpio52", "gpio59",
++ "gpio60", "gpio61", "gpio62";
++ function = "rgmii2";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
+ leds_pins: leds_pins {
+ mux {
+ pins = "gpio7", "gpio8", "gpio9",
+@@ -229,6 +831,17 @@
+ clock-output-names = "acpu1_aux";
+ };
+
++ l2cc: clock-controller@2011000 {
++ compatible = "qcom,kpss-gcc", "syscon";
++ reg = <0x2011000 0x1000>;
++ clock-output-names = "acpu_l2_aux";
++ };
++
++ kraitcc: clock-controller {
++ compatible = "qcom,krait-cc-v1";
++ #clock-cells = <1>;
++ };
++
+ saw0: regulator@2089000 {
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+@@ -241,6 +854,17 @@
+ regulator;
+ };
+
++ saw_l2: regulator@02012000 {
++ compatible = "qcom,saw2", "syscon";
++ reg = <0x02012000 0x1000>;
++ regulator;
++ };
++
++ sic_non_secure: sic-non-secure@12100000 {
++ compatible = "syscon";
++ reg = <0x12100000 0x10000>;
++ };
++
+ gsbi2: gsbi@12480000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
+@@ -436,6 +1060,15 @@
+ #power-domain-cells = <1>;
+ };
+
++ tsens: thermal-sensor@900000 {
++ compatible = "qcom,ipq8064-tsens";
++ reg = <0x900000 0x3680>;
++ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
++ nvmem-cell-names = "calib", "calib_backup";
++ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-ipq8064", "syscon";
+ reg = <0x1a400000 0x100>;
+@@ -448,6 +1081,95 @@
+ #reset-cells = <1>;
+ };
+
++ sfpb_mutex_block: syscon@1200600 {
++ compatible = "syscon";
++ reg = <0x01200600 0x100>;
++ };
++
++ hs_phy_0: hs_phy_0 {
++ compatible = "qcom,ipq806x-usb-phy-hs";
++ reg = <0x110f8800 0x30>;
++ clocks = <&gcc USB30_0_UTMI_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ ss_phy_0: ss_phy_0 {
++ compatible = "qcom,ipq806x-usb-phy-ss";
++ reg = <0x110f8830 0x30>;
++ clocks = <&gcc USB30_0_MASTER_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ usb3_0: usb3@110f8800 {
++ compatible = "qcom,dwc3", "syscon";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x110f8800 0x8000>;
++ clocks = <&gcc USB30_0_MASTER_CLK>;
++ clock-names = "core";
++
++ ranges;
++
++ resets = <&gcc USB30_0_MASTER_RESET>;
++ reset-names = "master";
++
++ status = "disabled";
++
++ dwc3_0: dwc3@11000000 {
++ compatible = "snps,dwc3";
++ reg = <0x11000000 0xcd00>;
++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&hs_phy_0>, <&ss_phy_0>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ snps,dis_u3_susphy_quirk;
++ };
++ };
++
++ hs_phy_1: hs_phy_1 {
++ compatible = "qcom,ipq806x-usb-phy-hs";
++ reg = <0x100f8800 0x30>;
++ clocks = <&gcc USB30_1_UTMI_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ ss_phy_1: ss_phy_1 {
++ compatible = "qcom,ipq806x-usb-phy-ss";
++ reg = <0x100f8830 0x30>;
++ clocks = <&gcc USB30_1_MASTER_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ usb3_1: usb3@100f8800 {
++ compatible = "qcom,dwc3", "syscon";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x100f8800 0x8000>;
++ clocks = <&gcc USB30_1_MASTER_CLK>;
++ clock-names = "core";
++
++ ranges;
++
++ resets = <&gcc USB30_1_MASTER_RESET>;
++ reset-names = "master";
++
++ status = "disabled";
++
++ dwc3_1: dwc3@10000000 {
++ compatible = "snps,dwc3";
++ reg = <0x10000000 0xcd00>;
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&hs_phy_1>, <&ss_phy_1>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ snps,dis_u3_susphy_quirk;
++ };
++ };
++
+ pcie0: pci@1b500000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b500000 0x1000
+@@ -601,6 +1323,167 @@
+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ };
+
++ adm_dma: dma@18300000 {
++ compatible = "qcom,adm";
++ reg = <0x18300000 0x100000>;
++ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++
++ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
++ clock-names = "core", "iface";
++
++ resets = <&gcc ADM0_RESET>,
++ <&gcc ADM0_PBUS_RESET>,
++ <&gcc ADM0_C0_RESET>,
++ <&gcc ADM0_C1_RESET>,
++ <&gcc ADM0_C2_RESET>;
++ reset-names = "clk", "pbus", "c0", "c1", "c2";
++ qcom,ee = <0>;
++
++ status = "disabled";
++ };
++
++ nand_controller: nand-controller@1ac00000 {
++ compatible = "qcom,ipq806x-nand";
++ reg = <0x1ac00000 0x800>;
++
++ clocks = <&gcc EBI2_CLK>,
++ <&gcc EBI2_AON_CLK>;
++ clock-names = "core", "aon";
++
++ dmas = <&adm_dma 3>;
++ dma-names = "rxtx";
++ qcom,cmd-crci = <15>;
++ qcom,data-crci = <3>;
++
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ nss_common: syscon@03000000 {
++ compatible = "syscon";
++ reg = <0x03000000 0x0000FFFF>;
++ };
++
++ qsgmii_csr: syscon@1bb00000 {
++ compatible = "syscon";
++ reg = <0x1bb00000 0x000001FF>;
++ };
++
++ stmmac_axi_setup: stmmac-axi-config {
++ snps,wr_osr_lmt = <7>;
++ snps,rd_osr_lmt = <7>;
++ snps,blen = <16 0 0 0 0 0 0>;
++ };
++
++ mdio0: mdio@37000000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ compatible = "qcom,ipq8064-mdio", "syscon";
++ reg = <0x37000000 0x200000>;
++ resets = <&gcc GMAC_CORE1_RESET>;
++ reset-names = "stmmaceth";
++ clocks = <&gcc GMAC_CORE1_CLK>;
++ clock-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
++ gmac0: ethernet@37000000 {
++ device_type = "network";
++ compatible = "qcom,ipq806x-gmac";
++ reg = <0x37000000 0x200000>;
++ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++
++ snps,axi-config = <&stmmac_axi_setup>;
++ snps,pbl = <32>;
++ snps,aal = <1>;
++
++ qcom,nss-common = <&nss_common>;
++ qcom,qsgmii-csr = <&qsgmii_csr>;
++
++ clocks = <&gcc GMAC_CORE1_CLK>;
++ clock-names = "stmmaceth";
++
++ resets = <&gcc GMAC_CORE1_RESET>;
++ reset-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
++ gmac1: ethernet@37200000 {
++ device_type = "network";
++ compatible = "qcom,ipq806x-gmac";
++ reg = <0x37200000 0x200000>;
++ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++
++ snps,axi-config = <&stmmac_axi_setup>;
++ snps,pbl = <32>;
++ snps,aal = <1>;
++
++ qcom,nss-common = <&nss_common>;
++ qcom,qsgmii-csr = <&qsgmii_csr>;
++
++ clocks = <&gcc GMAC_CORE2_CLK>;
++ clock-names = "stmmaceth";
++
++ resets = <&gcc GMAC_CORE2_RESET>;
++ reset-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
++ gmac2: ethernet@37400000 {
++ device_type = "network";
++ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
++ reg = <0x37400000 0x200000>;
++ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++
++ snps,axi-config = <&stmmac_axi_setup>;
++ snps,pbl = <32>;
++ snps,aal = <1>;
++
++ qcom,nss-common = <&nss_common>;
++ qcom,qsgmii-csr = <&qsgmii_csr>;
++
++ clocks = <&gcc GMAC_CORE3_CLK>;
++ clock-names = "stmmaceth";
++
++ resets = <&gcc GMAC_CORE3_RESET>;
++ reset-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
++ gmac3: ethernet@37600000 {
++ device_type = "network";
++ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
++ reg = <0x37600000 0x200000>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++
++ snps,axi-config = <&stmmac_axi_setup>;
++ snps,pbl = <32>;
++ snps,aal = <1>;
++
++ qcom,nss-common = <&nss_common>;
++ qcom,qsgmii-csr = <&qsgmii_csr>;
++
++ clocks = <&gcc GMAC_CORE4_CLK>;
++ clock-names = "stmmaceth";
++
++ resets = <&gcc GMAC_CORE4_RESET>;
++ reset-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+@@ -676,4 +1559,17 @@
+ };
+ };
+ };
++
++ sfpb_mutex: sfpb-mutex {
++ compatible = "qcom,sfpb-mutex";
++ syscon = <&sfpb_mutex_block 4 4>;
++
++ #hwlock-cells = <1>;
++ };
++
++ smem {
++ compatible = "qcom,smem";
++ memory-region = <&smem>;
++ hwlocks = <&sfpb_mutex 3>;
++ };
+ };
--- /dev/null
+This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
+instead of keeping a local version.
+We drop partitions, LEDs and keys from the file as we will implement
+them differently anyway.
+
+--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+@@ -42,16 +42,6 @@
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+-
+- partition@0 {
+- label = "rootfs";
+- reg = <0x0 0x1000000>;
+- };
+-
+- partition@1 {
+- label = "scratch";
+- reg = <0x1000000 0x1000000>;
+- };
+ };
+ };
+ };
+@@ -64,64 +54,5 @@
+ ports-implemented = <0x1>;
+ status = "ok";
+ };
+-
+- gpio_keys {
+- compatible = "gpio-keys";
+- pinctrl-0 = <&buttons_pins>;
+- pinctrl-names = "default";
+-
+- button@1 {
+- label = "reset";
+- linux,code = <KEY_RESTART>;
+- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+- linux,input-type = <1>;
+- debounce-interval = <60>;
+- };
+- button@2 {
+- label = "wps";
+- linux,code = <KEY_WPS_BUTTON>;
+- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
+- linux,input-type = <1>;
+- debounce-interval = <60>;
+- };
+- };
+-
+- leds {
+- compatible = "gpio-leds";
+- pinctrl-0 = <&leds_pins>;
+- pinctrl-names = "default";
+-
+- led@7 {
+- label = "led_usb1";
+- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "usbdev";
+- default-state = "off";
+- };
+-
+- led@8 {
+- label = "led_usb3";
+- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "usbdev";
+- default-state = "off";
+- };
+-
+- led@9 {
+- label = "status_led_fail";
+- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
+- default-state = "off";
+- };
+-
+- led@26 {
+- label = "sata_led";
+- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
+- default-state = "off";
+- };
+-
+- led@53 {
+- label = "status_led_pass";
+- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
+- default-state = "off";
+- };
+- };
+ };
+ };
--- /dev/null
+This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
+instead of keeping a local version. This patch adds our local adjustments
+for the (local) additional contents of qcom-ipq8064.dtsi
+
+--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+@@ -56,3 +56,7 @@
+ };
+ };
+ };
++
++&CPU_SPC {
++ status = "okay";
++};
--- /dev/null
+From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
+From: Ajay Kishore <akisho@codeaurora.org>
+Date: Fri, 27 Mar 2020 23:32:08 +0100
+Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
+
+For IPQ806x targets, TZ protects the registers that are used to
+configure the routing of interrupts to a target processor.
+To resolve this, this patch uses scm call to route GPIO interrupts
+to application processor. Also the scm call interface is changed.
+
+Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
+
+--- a/drivers/pinctrl/qcom/pinctrl-msm.c
++++ b/drivers/pinctrl/qcom/pinctrl-msm.c
+@@ -22,6 +22,8 @@
+ #include <linux/reboot.h>
+ #include <linux/pm.h>
+ #include <linux/log2.h>
++#include <linux/qcom_scm.h>
++#include <linux/io.h>
+
+ #include "../core.h"
+ #include "../pinconf.h"
+@@ -57,6 +59,8 @@ struct msm_pinctrl {
+ struct irq_chip irq_chip;
+ int irq;
+
++ bool intr_target_use_scm;
++
+ raw_spinlock_t lock;
+
+ DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
+@@ -64,6 +68,7 @@ struct msm_pinctrl {
+
+ const struct msm_pinctrl_soc_data *soc;
+ void __iomem *regs[MAX_NR_TILES];
++ u32 phys_base[MAX_NR_TILES];
+ };
+
+ #define MSM_ACCESSOR(name) \
+@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
+ else
+ clear_bit(d->hwirq, pctrl->dual_edge_irqs);
+
+- /* Route interrupts to application cpu */
+- val = msm_readl_intr_target(pctrl, g);
+- val &= ~(7 << g->intr_target_bit);
+- val |= g->intr_target_kpss_val << g->intr_target_bit;
+- msm_writel_intr_target(val, pctrl, g);
++ /* Route interrupts to application cpu.
++ * With intr_target_use_scm interrupts are routed to
++ * application cpu using scm calls.
++ */
++ if (pctrl->intr_target_use_scm) {
++ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
++ int ret;
++
++ qcom_scm_io_readl(addr, &val);
++
++ val &= ~(7 << g->intr_target_bit);
++ val |= g->intr_target_kpss_val << g->intr_target_bit;
++
++ ret = qcom_scm_io_writel(addr, val);
++ if (ret)
++ dev_err(pctrl->dev,
++ "Failed routing %lu interrupt to Apps proc",
++ d->hwirq);
++ } else {
++ val = msm_readl_intr_target(pctrl, g);
++ val &= ~(7 << g->intr_target_bit);
++ val |= g->intr_target_kpss_val << g->intr_target_bit;
++ msm_writel_intr_target(val, pctrl, g);
++ }
+
+ /* Update configuration for gpio.
+ * RAW_STATUS_EN is left on for all gpio irqs. Due to the
+@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
+ pctrl->dev = &pdev->dev;
+ pctrl->soc = soc_data;
+ pctrl->chip = msm_gpio_template;
++ pctrl->intr_target_use_scm = of_device_is_compatible(
++ pctrl->dev->of_node,
++ "qcom,ipq8064-pinctrl");
+
+ raw_spin_lock_init(&pctrl->lock);
+
+@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
+ pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pctrl->regs[0]))
+ return PTR_ERR(pctrl->regs[0]);
++
++ pctrl->phys_base[0] = res->start;
+ }
+
+ msm_pinctrl_setup_pm_reset(pctrl);
--- /dev/null
+From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 19 Feb 2020 18:59:39 +0100
+Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
+
+Add missing gpio definition for mdio and rgmii2.
+
+Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
++++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+@@ -299,7 +299,7 @@ static const char * const gpio_groups[]
+ };
+
+ static const char * const mdio_groups[] = {
+- "gpio0", "gpio1", "gpio10", "gpio11",
++ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
+ };
+
+ static const char * const mi2s_groups[] = {
+@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou
+ };
+
+ static const char * const rgmii2_groups[] = {
+- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
++ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
+ };
+
+ static const char * const sata_groups[] = {
+@@ -539,7 +539,7 @@ static const struct msm_function ipq8064
+ static const struct msm_pingroup ipq8064_groups[] = {
+ PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
+@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064
+ PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
--- /dev/null
+From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 4 Feb 2020 20:56:48 +0100
+Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
+
+Some platform like ipq806x doesn't support pretimeout and define
+some interrupts used by qcom,msm-timer. Change the driver to check
+and use pretimeout only on qcom,kpss-wdt as it's the only platform
+that actually supports it.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
+[groeck: Conflict resolution]
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
+ 1 file changed, 23 insertions(+), 8 deletions(-)
+
+--- a/drivers/watchdog/qcom-wdt.c
++++ b/drivers/watchdog/qcom-wdt.c
+@@ -40,6 +40,11 @@ static const u32 reg_offset_data_kpss[]
+ [WDT_BITE_TIME] = 0x14,
+ };
+
++struct qcom_wdt_match_data {
++ const u32 *offset;
++ bool pretimeout;
++};
++
+ struct qcom_wdt {
+ struct watchdog_device wdd;
+ unsigned long rate;
+@@ -179,19 +184,29 @@ static void qcom_clk_disable_unprepare(v
+ clk_disable_unprepare(data);
+ }
+
++static const struct qcom_wdt_match_data match_data_apcs_tmr = {
++ .offset = reg_offset_data_apcs_tmr,
++ .pretimeout = false,
++};
++
++static const struct qcom_wdt_match_data match_data_kpss = {
++ .offset = reg_offset_data_kpss,
++ .pretimeout = true,
++};
++
+ static int qcom_wdt_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ struct device_node *np = dev->of_node;
+- const u32 *regs;
++ const struct qcom_wdt_match_data *data;
+ u32 percpu_offset;
+ int irq, ret;
+ struct clk *clk;
+
+- regs = of_device_get_match_data(dev);
+- if (!regs) {
++ data = of_device_get_match_data(dev);
++ if (!data) {
+ dev_err(dev, "Unsupported QCOM WDT module\n");
+ return -ENODEV;
+ }
+@@ -247,7 +262,7 @@ static int qcom_wdt_probe(struct platfor
+
+ /* check if there is pretimeout support */
+ irq = platform_get_irq_optional(pdev, 0);
+- if (irq > 0) {
++ if (data->pretimeout && irq > 0) {
+ ret = devm_request_irq(dev, irq, qcom_wdt_isr,
+ IRQF_TRIGGER_RISING,
+ "wdt_bark", &wdt->wdd);
+@@ -267,7 +282,7 @@ static int qcom_wdt_probe(struct platfor
+ wdt->wdd.min_timeout = 1;
+ wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
+ wdt->wdd.parent = dev;
+- wdt->layout = regs;
++ wdt->layout = data->offset;
+
+ if (readl(wdt_addr(wdt, WDT_STS)) & 1)
+ wdt->wdd.bootstatus = WDIOF_CARDRESET;
+@@ -311,9 +326,9 @@ static int __maybe_unused qcom_wdt_resum
+ static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
+
+ static const struct of_device_id qcom_wdt_of_table[] = {
+- { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
+- { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
+- { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
++ { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
++ { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
++ { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
+ { },
+ };
+ MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
--- /dev/null
+From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Wed, 18 Mar 2020 14:16:56 +0100
+Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
+
+Kernel got hanged while reading from /dev/hwrng at the
+time of PRNG clock enable
+
+Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = {
+ .parent_map = gcc_pxo_pll8_map,
+ },
+ .clkr = {
++ .enable_reg = 0x2e80,
++ .enable_mask = BIT(11),
+ .hw.init = &(struct clk_init_data){
+ .name = "prng_src",
+ .parent_names = gcc_pxo_pll8,
--- /dev/null
+From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 10 Mar 2020 15:37:56 +0100
+Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
+
+Add missing definition of rpm clk for ipq806x soc
+
+Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: John Crispin <john@phrozen.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
+ drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++
+ include/dt-bindings/clock/qcom,rpmcc.h | 4 +++
+ 3 files changed, 40 insertions(+)
+
+--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
++++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+@@ -15,6 +15,7 @@ Required properties :
+ "qcom,rpmcc-msm8916", "qcom,rpmcc"
+ "qcom,rpmcc-msm8974", "qcom,rpmcc"
+ "qcom,rpmcc-apq8064", "qcom,rpmcc"
++ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
+ "qcom,rpmcc-msm8996", "qcom,rpmcc"
+ "qcom,rpmcc-msm8998", "qcom,rpmcc"
+ "qcom,rpmcc-qcs404", "qcom,rpmcc"
+--- a/drivers/clk/qcom/clk-rpm.c
++++ b/drivers/clk/qcom/clk-rpm.c
+@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
+ .num_clks = ARRAY_SIZE(apq8064_clks),
+ };
+
++/* ipq806x */
++DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
++DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
++DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
++DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
++DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
++DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
++DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
++DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
++
++static struct clk_rpm *ipq806x_clks[] = {
++ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
++ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
++ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
++ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
++ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
++ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
++ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
++ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
++ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
++ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
++ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
++ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
++ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
++ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
++ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
++ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
++};
++
++static const struct rpm_clk_desc rpm_clk_ipq806x = {
++ .clks = ipq806x_clks,
++ .num_clks = ARRAY_SIZE(ipq806x_clks),
++};
++
+ static const struct of_device_id rpm_clk_match_table[] = {
+ { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
+ { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
+ { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
++ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
+ { }
+ };
+ MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
+--- a/include/dt-bindings/clock/qcom,rpmcc.h
++++ b/include/dt-bindings/clock/qcom,rpmcc.h
+@@ -37,6 +37,10 @@
+ #define RPM_XO_A0 27
+ #define RPM_XO_A1 28
+ #define RPM_XO_A2 29
++#define RPM_NSS_FABRIC_0_CLK 30
++#define RPM_NSS_FABRIC_0_A_CLK 31
++#define RPM_NSS_FABRIC_1_CLK 32
++#define RPM_NSS_FABRIC_1_A_CLK 33
+
+ /* SMD RPM clocks */
+ #define RPM_SMD_XO_CLK_SRC 0
--- /dev/null
+From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 19 Feb 2020 17:37:11 +0100
+Subject: regulator: add smb208 support
+
+Smb208 regulators are used on some ipq806x soc.
+Add support for it to make it avaiable on some routers
+that use it.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
+ drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
++++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
+@@ -61,6 +61,7 @@ Regulator nodes are identified by their
+ "qcom,rpm-pm8901-regulators"
+ "qcom,rpm-pm8921-regulators"
+ "qcom,rpm-pm8018-regulators"
++ "qcom,rpm-smb208-regulators"
+
+ - vdd_l0_l1_lvs-supply:
+ - vdd_l2_l11_l12-supply:
+@@ -171,6 +172,9 @@ pm8018:
+ s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
+ l12, l14, lvs1
+
++smb208:
++ s1a, s1b, s2a, s2b
++
+ The content of each sub-node is defined by the standard binding for regulators -
+ see regulator.txt - with additional custom properties described below:
+
+--- a/drivers/regulator/qcom_rpm-regulator.c
++++ b/drivers/regulator/qcom_rpm-regulator.c
+@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r
+ { }
+ };
+
++static const struct rpm_regulator_data rpm_smb208_regulators[] = {
++ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
++ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
++ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
++ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
++ { }
++};
++
+ static const struct of_device_id rpm_of_match[] = {
+ { .compatible = "qcom,rpm-pm8018-regulators",
+ .data = &rpm_pm8018_regulators },
+ { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
+ { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
+ { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
++ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
+ { }
+ };
+ MODULE_DEVICE_TABLE(of, rpm_of_match);
--- /dev/null
+From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Fri, 13 Mar 2020 18:52:13 +0100
+Subject: cpufreq: qcom: Add support for krait based socs
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage/current value of each OPP
+varies based on the silicon variant in use.
+
+The required OPP related data is determined based on
+the efuse value. This is similar to the existing code for
+kryo cores. So adding support for krait cores here.
+
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
+ drivers/cpufreq/Kconfig.arm | 2 +-
+ drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 191 +++++++++++++++++++--
+ 4 files changed, 183 insertions(+), 18 deletions(-)
+
+--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
++++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+@@ -19,7 +19,8 @@ In 'cpu' nodes:
+
+ In 'operating-points-v2' table:
+ - compatible: Should be
+- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
++ - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
++ apq8064, ipq8064, msm8960 and ipq8074.
+
+ Optional properties:
+ --------------------
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -135,7 +135,7 @@ config ARM_OMAP2PLUS_CPUFREQ
+
+ config ARM_QCOM_CPUFREQ_NVMEM
+ tristate "Qualcomm nvmem based CPUFreq"
+- depends on ARM64
++ depends on ARCH_QCOM
+ depends on QCOM_QFPROM
+ depends on QCOM_SMEM
+ select PM_OPP
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -138,6 +138,11 @@ static const struct of_device_id blackli
+ { .compatible = "ti,am43", },
+ { .compatible = "ti,dra7", },
+
++ { .compatible = "qcom,ipq8064", },
++ { .compatible = "qcom,apq8064", },
++ { .compatible = "qcom,msm8974", },
++ { .compatible = "qcom,msm8960", },
++
+ { }
+ };
+
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
+ struct qcom_cpufreq_match_data {
+ int (*get_version)(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
++ char **pvs_name,
+ struct qcom_cpufreq_drv *drv);
+ const char **genpd_names;
+ };
+
+ struct qcom_cpufreq_drv {
+- struct opp_table **opp_tables;
++ struct opp_table **names_opp_tables;
++ struct opp_table **hw_opp_tables;
+ struct opp_table **genpd_opp_tables;
+ u32 versions;
+ const struct qcom_cpufreq_match_data *data;
+@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
+
+ static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
+
++static void get_krait_bin_format_a(struct device *cpu_dev,
++ int *speed, int *pvs, int *pvs_ver,
++ struct nvmem_cell *pvs_nvmem, u8 *buf)
++{
++ u32 pte_efuse;
++
++ pte_efuse = *((u32 *)buf);
++
++ *speed = pte_efuse & 0xf;
++ if (*speed == 0xf)
++ *speed = (pte_efuse >> 4) & 0xf;
++
++ if (*speed == 0xf) {
++ *speed = 0;
++ dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
++ } else {
++ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
++ }
++
++ *pvs = (pte_efuse >> 10) & 0x7;
++ if (*pvs == 0x7)
++ *pvs = (pte_efuse >> 13) & 0x7;
++
++ if (*pvs == 0x7) {
++ *pvs = 0;
++ dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
++ } else {
++ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
++ }
++}
++
++static void get_krait_bin_format_b(struct device *cpu_dev,
++ int *speed, int *pvs, int *pvs_ver,
++ struct nvmem_cell *pvs_nvmem, u8 *buf)
++{
++ u32 pte_efuse, redundant_sel;
++
++ pte_efuse = *((u32 *)buf);
++ redundant_sel = (pte_efuse >> 24) & 0x7;
++
++ *pvs_ver = (pte_efuse >> 4) & 0x3;
++
++ switch (redundant_sel) {
++ case 1:
++ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
++ *speed = (pte_efuse >> 27) & 0xf;
++ break;
++ case 2:
++ *pvs = (pte_efuse >> 27) & 0xf;
++ *speed = pte_efuse & 0x7;
++ break;
++ default:
++ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
++ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
++ *speed = pte_efuse & 0x7;
++ }
++
++ /* Check SPEED_BIN_BLOW_STATUS */
++ if (pte_efuse & BIT(3)) {
++ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
++ } else {
++ dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
++ *speed = 0;
++ }
++
++ /* Check PVS_BLOW_STATUS */
++ pte_efuse = *(((u32 *)buf) + 4);
++ pte_efuse &= BIT(21);
++ if (pte_efuse) {
++ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
++ } else {
++ dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
++ *pvs = 0;
++ }
++
++ dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
++}
++
+ static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
+ {
+ size_t len;
+@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre
+
+ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
++ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+ {
+ size_t len;
+ u8 *speedbin;
+ enum _msm8996_version msm8996_version;
++ *pvs_name = NULL;
+
+ msm8996_version = qcom_cpufreq_get_msm_id();
+ if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
+@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio
+ return 0;
+ }
+
++static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
++ struct nvmem_cell *speedbin_nvmem,
++ char **pvs_name,
++ struct qcom_cpufreq_drv *drv)
++{
++ int speed = 0, pvs = 0, pvs_ver = 0;
++ u8 *speedbin;
++ size_t len;
++
++ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
++
++ if (IS_ERR(speedbin))
++ return PTR_ERR(speedbin);
++
++ switch (len) {
++ case 4:
++ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
++ speedbin_nvmem, speedbin);
++ break;
++ case 8:
++ get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
++ speedbin_nvmem, speedbin);
++ break;
++ default:
++ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
++ return -ENODEV;
++ }
++
++ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
++ speed, pvs, pvs_ver);
++
++ drv->versions = (1 << speed);
++
++ kfree(speedbin);
++ return 0;
++}
++
+ static const struct qcom_cpufreq_match_data match_data_kryo = {
+ .get_version = qcom_cpufreq_kryo_name_version,
+ };
+
++static const struct qcom_cpufreq_match_data match_data_krait = {
++ .get_version = qcom_cpufreq_krait_name_version,
++};
++
+ static const char *qcs404_genpd_names[] = { "cpr", NULL };
+
+ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
+@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla
+ struct nvmem_cell *speedbin_nvmem;
+ struct device_node *np;
+ struct device *cpu_dev;
++ char *pvs_name = "speedXX-pvsXX-vXX";
+ unsigned cpu;
+ const struct of_device_id *match;
+ int ret;
+@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
+ if (!np)
+ return -ENOENT;
+
+- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
++ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
+ if (!ret) {
+ of_node_put(np);
+ return -ENOENT;
+@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla
+ goto free_drv;
+ }
+
+- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
++ ret = drv->data->get_version(cpu_dev,
++ speedbin_nvmem, &pvs_name, drv);
+ if (ret) {
+ nvmem_cell_put(speedbin_nvmem);
+ goto free_drv;
+@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla
+ }
+ of_node_put(np);
+
+- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
++ drv->names_opp_tables = kcalloc(num_possible_cpus(),
++ sizeof(*drv->names_opp_tables),
+ GFP_KERNEL);
+- if (!drv->opp_tables) {
++ if (!drv->names_opp_tables) {
+ ret = -ENOMEM;
+ goto free_drv;
+ }
++ drv->hw_opp_tables = kcalloc(num_possible_cpus(),
++ sizeof(*drv->hw_opp_tables),
++ GFP_KERNEL);
++ if (!drv->hw_opp_tables) {
++ ret = -ENOMEM;
++ goto free_opp_names;
++ }
+
+ drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
+ sizeof(*drv->genpd_opp_tables),
+@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla
+ }
+
+ if (drv->data->get_version) {
+- drv->opp_tables[cpu] =
+- dev_pm_opp_set_supported_hw(cpu_dev,
+- &drv->versions, 1);
+- if (IS_ERR(drv->opp_tables[cpu])) {
+- ret = PTR_ERR(drv->opp_tables[cpu]);
++
++ if (pvs_name) {
++ drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
++ cpu_dev,
++ pvs_name);
++ if (IS_ERR(drv->names_opp_tables[cpu])) {
++ ret = PTR_ERR(drv->names_opp_tables[cpu]);
++ dev_err(cpu_dev, "Failed to add OPP name %s\n",
++ pvs_name);
++ goto free_opp;
++ }
++ }
++
++ drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
++ cpu_dev, &drv->versions, 1);
++ if (IS_ERR(drv->hw_opp_tables[cpu])) {
++ ret = PTR_ERR(drv->hw_opp_tables[cpu]);
+ dev_err(cpu_dev,
+ "Failed to set supported hardware\n");
+ goto free_genpd_opp;
+@@ -259,11 +404,18 @@ free_genpd_opp:
+ kfree(drv->genpd_opp_tables);
+ free_opp:
+ for_each_possible_cpu(cpu) {
+- if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
++ if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
++ break;
++ dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
++ }
++ for_each_possible_cpu(cpu) {
++ if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
+ break;
+- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
++ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
+ }
+- kfree(drv->opp_tables);
++ kfree(drv->hw_opp_tables);
++free_opp_names:
++ kfree(drv->names_opp_tables);
+ free_drv:
+ kfree(drv);
+
+@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl
+ platform_device_unregister(cpufreq_dt_pdev);
+
+ for_each_possible_cpu(cpu) {
+- if (drv->opp_tables[cpu])
+- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
++ if (drv->names_opp_tables[cpu])
++ dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
++ if (drv->hw_opp_tables[cpu])
++ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
+ if (drv->genpd_opp_tables[cpu])
+ dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
+ }
+
+- kfree(drv->opp_tables);
++ kfree(drv->names_opp_tables);
++ kfree(drv->hw_opp_tables);
+ kfree(drv->genpd_opp_tables);
+ kfree(drv);
+
+@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp
+ { .compatible = "qcom,apq8096", .data = &match_data_kryo },
+ { .compatible = "qcom,msm8996", .data = &match_data_kryo },
+ { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
++ { .compatible = "qcom,ipq8064", .data = &match_data_krait },
++ { .compatible = "qcom,apq8064", .data = &match_data_krait },
++ { .compatible = "qcom,msm8974", .data = &match_data_krait },
++ { .compatible = "qcom,msm8960", .data = &match_data_krait },
+ {},
+ };
+ MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
--- /dev/null
+From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Fri, 1 May 2020 00:22:25 +0200
+Subject: cpufreq: qcom: fix wrong compatible binding
+
+Binding in Documentation is still "operating-points-v2-kryo-cpu".
+Restore the old binding to fix the compatibility problem.
+
+Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
+ if (!np)
+ return -ENOENT;
+
+- ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
++ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+ if (!ret) {
+ of_node_put(np);
+ return -ENOENT;
--- /dev/null
+From 6a114526af4689938863bf34976c83bfd279f517 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 15 Jun 2020 23:06:02 +0200
+Subject: PCI: qcom: Use bulk clk api and assert on error
+
+Rework 2.1.0 revision to use bulk clk api and fix missing assert on
+reset_control_deassert error.
+
+Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 131 ++++++++++++---------------------
+ 1 file changed, 46 insertions(+), 85 deletions(-)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -99,12 +99,9 @@
+ #define SLV_ADDR_SPACE_SZ 0x10000000
+
+ #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
++#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
+ struct qcom_pcie_resources_2_1_0 {
+- struct clk *iface_clk;
+- struct clk *core_clk;
+- struct clk *phy_clk;
+- struct clk *aux_clk;
+- struct clk *ref_clk;
++ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
+ struct reset_control *pci_reset;
+ struct reset_control *axi_reset;
+ struct reset_control *ahb_reset;
+@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0
+ if (ret)
+ return ret;
+
+- res->iface_clk = devm_clk_get(dev, "iface");
+- if (IS_ERR(res->iface_clk))
+- return PTR_ERR(res->iface_clk);
+-
+- res->core_clk = devm_clk_get(dev, "core");
+- if (IS_ERR(res->core_clk))
+- return PTR_ERR(res->core_clk);
+-
+- res->phy_clk = devm_clk_get(dev, "phy");
+- if (IS_ERR(res->phy_clk))
+- return PTR_ERR(res->phy_clk);
+-
+- res->aux_clk = devm_clk_get_optional(dev, "aux");
+- if (IS_ERR(res->aux_clk))
+- return PTR_ERR(res->aux_clk);
+-
+- res->ref_clk = devm_clk_get_optional(dev, "ref");
+- if (IS_ERR(res->ref_clk))
+- return PTR_ERR(res->ref_clk);
++ res->clks[0].id = "iface";
++ res->clks[1].id = "core";
++ res->clks[2].id = "phy";
++ res->clks[3].id = "aux";
++ res->clks[4].id = "ref";
++
++ /* iface, core, phy are required */
++ ret = devm_clk_bulk_get(dev, 3, res->clks);
++ if (ret < 0)
++ return ret;
++
++ /* aux, ref are optional */
++ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
++ if (ret < 0)
++ return ret;
+
+ res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
+ if (IS_ERR(res->pci_reset))
+@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc
+ {
+ struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+
+- clk_disable_unprepare(res->phy_clk);
++ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+ reset_control_assert(res->pci_reset);
+ reset_control_assert(res->axi_reset);
+ reset_control_assert(res->ahb_reset);
+ reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
+ reset_control_assert(res->phy_reset);
+- clk_disable_unprepare(res->iface_clk);
+- clk_disable_unprepare(res->core_clk);
+- clk_disable_unprepare(res->aux_clk);
+- clk_disable_unprepare(res->ref_clk);
+
+ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+@@ -334,47 +323,45 @@ static int qcom_pcie_init_2_1_0(struct q
+ return ret;
+ }
+
+- ret = reset_control_assert(res->ahb_reset);
++ ret = reset_control_deassert(res->ahb_reset);
+ if (ret) {
+- dev_err(dev, "cannot assert ahb reset\n");
+- goto err_assert_ahb;
++ dev_err(dev, "cannot deassert ahb reset\n");
++ goto err_deassert_ahb;
+ }
+
+- ret = clk_prepare_enable(res->iface_clk);
++ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+- dev_err(dev, "cannot prepare/enable iface clock\n");
+- goto err_assert_ahb;
++ dev_err(dev, "cannot deassert ext reset\n");
++ goto err_deassert_ext;
+ }
+
+- ret = clk_prepare_enable(res->core_clk);
++ ret = reset_control_deassert(res->phy_reset);
+ if (ret) {
+- dev_err(dev, "cannot prepare/enable core clock\n");
+- goto err_clk_core;
++ dev_err(dev, "cannot deassert phy reset\n");
++ goto err_deassert_phy;
+ }
+
+- ret = clk_prepare_enable(res->aux_clk);
++ ret = reset_control_deassert(res->pci_reset);
+ if (ret) {
+- dev_err(dev, "cannot prepare/enable aux clock\n");
+- goto err_clk_aux;
++ dev_err(dev, "cannot deassert pci reset\n");
++ goto err_deassert_pci;
+ }
+
+- ret = clk_prepare_enable(res->ref_clk);
++ ret = reset_control_deassert(res->por_reset);
+ if (ret) {
+- dev_err(dev, "cannot prepare/enable ref clock\n");
+- goto err_clk_ref;
++ dev_err(dev, "cannot deassert por reset\n");
++ goto err_deassert_por;
+ }
+
+- ret = reset_control_deassert(res->ahb_reset);
++ ret = reset_control_deassert(res->axi_reset);
+ if (ret) {
+- dev_err(dev, "cannot deassert ahb reset\n");
+- goto err_deassert_ahb;
++ dev_err(dev, "cannot deassert axi reset\n");
++ goto err_deassert_axi;
+ }
+
+- ret = reset_control_deassert(res->ext_reset);
+- if (ret) {
+- dev_err(dev, "cannot deassert ext reset\n");
+- goto err_deassert_ahb;
+- }
++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
++ if (ret)
++ goto err_clks;
+
+ /* enable PCIe clocks and resets */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+@@ -406,36 +393,6 @@ static int qcom_pcie_init_2_1_0(struct q
+ val |= PHY_REFCLK_SSP_EN;
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+
+- ret = reset_control_deassert(res->phy_reset);
+- if (ret) {
+- dev_err(dev, "cannot deassert phy reset\n");
+- return ret;
+- }
+-
+- ret = reset_control_deassert(res->pci_reset);
+- if (ret) {
+- dev_err(dev, "cannot deassert pci reset\n");
+- return ret;
+- }
+-
+- ret = reset_control_deassert(res->por_reset);
+- if (ret) {
+- dev_err(dev, "cannot deassert por reset\n");
+- return ret;
+- }
+-
+- ret = reset_control_deassert(res->axi_reset);
+- if (ret) {
+- dev_err(dev, "cannot deassert axi reset\n");
+- return ret;
+- }
+-
+- ret = clk_prepare_enable(res->phy_clk);
+- if (ret) {
+- dev_err(dev, "cannot prepare/enable phy clock\n");
+- goto err_deassert_ahb;
+- }
+-
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
+
+@@ -448,15 +405,19 @@ static int qcom_pcie_init_2_1_0(struct q
+
+ return 0;
+
++err_clks:
++ reset_control_assert(res->axi_reset);
++err_deassert_axi:
++ reset_control_assert(res->por_reset);
++err_deassert_por:
++ reset_control_assert(res->pci_reset);
++err_deassert_pci:
++ reset_control_assert(res->phy_reset);
++err_deassert_phy:
++ reset_control_assert(res->ext_reset);
++err_deassert_ext:
++ reset_control_assert(res->ahb_reset);
+ err_deassert_ahb:
+- clk_disable_unprepare(res->ref_clk);
+-err_clk_ref:
+- clk_disable_unprepare(res->aux_clk);
+-err_clk_aux:
+- clk_disable_unprepare(res->core_clk);
+-err_clk_core:
+- clk_disable_unprepare(res->iface_clk);
+-err_assert_ahb:
+ regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
+
+ return ret;
--- /dev/null
+From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 15 Jun 2020 23:06:05 +0200
+Subject: PCI: qcom: Add ipq8064 rev2 variant
+
+Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
+different offset based on the revision.
+
+Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
++ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+@@ -1328,6 +1329,7 @@ err_pm_runtime_put:
+ static const struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
++ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
+ { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
--- /dev/null
+From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Mon, 15 Jun 2020 23:06:07 +0200
+Subject: PCI: qcom: Support pci speed set for ipq806x
+
+Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to
+some hardware limitations. Add support for speed setting defined by the
+max-link-speed binding. If not defined the max speed is set to GEN2 by
+default.
+
+Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
+---
+
+Backported with light changes:
+* One include is missing in kernel 5.4
+
+ drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -27,6 +27,7 @@
+ #include <linux/slab.h>
+ #include <linux/types.h>
+
++#include "../../pci.h"
+ #include "pcie-designware.h"
+
+ #define PCIE20_PARF_SYS_CTRL 0x00
+@@ -98,6 +99,8 @@
+ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
+ #define SLV_ADDR_SPACE_SZ 0x10000000
+
++#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
++
+ #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
+ #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
+ struct qcom_pcie_resources_2_1_0 {
+@@ -184,6 +187,7 @@ struct qcom_pcie {
+ struct phy *phy;
+ struct gpio_desc *reset;
+ const struct qcom_pcie_ops *ops;
++ int gen;
+ };
+
+ #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
+@@ -397,6 +401,11 @@ static int qcom_pcie_init_2_1_0(struct q
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
+
++ if (pcie->gen == 1) {
++ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
++ val |= PCI_EXP_LNKSTA_CLS_2_5GB;
++ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
++ }
+
+ /* Set the Max TLP size to 2K, instead of using default of 4K */
+ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
+@@ -1261,6 +1270,10 @@ static int qcom_pcie_probe(struct platfo
+ goto err_pm_runtime_put;
+ }
+
++ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
++ if (pcie->gen < 0)
++ pcie->gen = 2;
++
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
+ pcie->parf = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->parf)) {
--- /dev/null
+From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 4 Mar 2020 22:38:32 +0100
+Subject: net: mdio: add ipq8064 mdio driver
+
+Currently ipq806x soc use generic bitbang driver to
+comunicate with the gmac ethernet interface.
+Add a dedicated driver created by chunkeey to fix this.
+
+Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/Kconfig | 8 ++
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 175 insertions(+)
+ create mode 100644 drivers/net/phy/mdio-ipq8064.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -156,6 +156,14 @@ config MDIO_I2C
+
+ This is library mode.
+
++config MDIO_IPQ8064
++ tristate "Qualcomm IPQ8064 MDIO interface support"
++ depends on HAS_IOMEM && OF_MDIO
++ depends on MFD_SYSCON
++ help
++ This driver supports the MDIO interface found in the network
++ interface units of the IPQ8064 SoC
++
+ config MDIO_MOXART
+ tristate "MOXA ART MDIO interface support"
+ depends on ARCH_MOXART || COMPILE_TEST
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
+ obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
+ obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
+ obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
++obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o
+ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
+ obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
+ obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
+--- /dev/null
++++ b/drivers/net/phy/mdio-ipq8064.c
+@@ -0,0 +1,166 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Qualcomm IPQ8064 MDIO interface driver
++ *
++ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
++ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
++ */
++
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <linux/of_mdio.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/mfd/syscon.h>
++
++/* MII address register definitions */
++#define MII_ADDR_REG_ADDR 0x10
++#define MII_BUSY BIT(0)
++#define MII_WRITE BIT(1)
++#define MII_CLKRANGE_60_100M (0 << 2)
++#define MII_CLKRANGE_100_150M (1 << 2)
++#define MII_CLKRANGE_20_35M (2 << 2)
++#define MII_CLKRANGE_35_60M (3 << 2)
++#define MII_CLKRANGE_150_250M (4 << 2)
++#define MII_CLKRANGE_250_300M (5 << 2)
++#define MII_CLKRANGE_MASK GENMASK(4, 2)
++#define MII_REG_SHIFT 6
++#define MII_REG_MASK GENMASK(10, 6)
++#define MII_ADDR_SHIFT 11
++#define MII_ADDR_MASK GENMASK(15, 11)
++
++#define MII_DATA_REG_ADDR 0x14
++
++#define MII_MDIO_DELAY_USEC (1000)
++#define MII_MDIO_RETRY_MSEC (10)
++
++struct ipq8064_mdio {
++ struct regmap *base; /* NSS_GMAC0_BASE */
++};
++
++static int
++ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
++{
++ u32 busy;
++
++ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
++ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
++ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
++}
++
++static int
++ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
++{
++ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
++ struct ipq8064_mdio *priv = bus->priv;
++ u32 ret_val;
++ int err;
++
++ /* Reject clause 45 */
++ if (reg_offset & MII_ADDR_C45)
++ return -EOPNOTSUPP;
++
++ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
++ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
++
++ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
++ usleep_range(8, 10);
++
++ err = ipq8064_mdio_wait_busy(priv);
++ if (err)
++ return err;
++
++ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
++ return (int)ret_val;
++}
++
++static int
++ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
++{
++ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
++ struct ipq8064_mdio *priv = bus->priv;
++
++ /* Reject clause 45 */
++ if (reg_offset & MII_ADDR_C45)
++ return -EOPNOTSUPP;
++
++ regmap_write(priv->base, MII_DATA_REG_ADDR, data);
++
++ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
++ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
++
++ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
++ usleep_range(8, 10);
++
++ return ipq8064_mdio_wait_busy(priv);
++}
++
++static int
++ipq8064_mdio_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct ipq8064_mdio *priv;
++ struct mii_bus *bus;
++ int ret;
++
++ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
++ if (!bus)
++ return -ENOMEM;
++
++ bus->name = "ipq8064_mdio_bus";
++ bus->read = ipq8064_mdio_read;
++ bus->write = ipq8064_mdio_write;
++ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
++ bus->parent = &pdev->dev;
++
++ priv = bus->priv;
++ priv->base = device_node_to_regmap(np);
++ if (IS_ERR(priv->base)) {
++ if (priv->base == ERR_PTR(-EPROBE_DEFER))
++ return -EPROBE_DEFER;
++
++ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
++ priv->base);
++ return PTR_ERR(priv->base);
++ }
++
++ ret = of_mdiobus_register(bus, np);
++ if (ret)
++ return ret;
++
++ platform_set_drvdata(pdev, bus);
++ return 0;
++}
++
++static int
++ipq8064_mdio_remove(struct platform_device *pdev)
++{
++ struct mii_bus *bus = platform_get_drvdata(pdev);
++
++ mdiobus_unregister(bus);
++
++ return 0;
++}
++
++static const struct of_device_id ipq8064_mdio_dt_ids[] = {
++ { .compatible = "qcom,ipq8064-mdio" },
++ { }
++};
++MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
++
++static struct platform_driver ipq8064_mdio_driver = {
++ .probe = ipq8064_mdio_probe,
++ .remove = ipq8064_mdio_remove,
++ .driver = {
++ .name = "ipq8064-mdio",
++ .of_match_table = ipq8064_mdio_dt_ids,
++ },
++};
++
++module_platform_driver(ipq8064_mdio_driver);
++
++MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
++MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
++MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Fri, 17 Jul 2020 15:16:31 +0200
+Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
+
+This has lost in the original push for the dwc3 qcom driver.
+This is needed for ipq806x SoC as without this the usb ports
+doesn't work at all.
+
+Signed-off-by: Andy Gross <agross@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Tested-by: Jonathan McDowell <noodles@earth.li>
+Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+
+Light modification to Kconfig as some config are missing in kernel 5.4
+
+ drivers/phy/qualcomm/Kconfig | 10 +
+ drivers/phy/qualcomm/Makefile | 1 +
+ drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
+ 3 files changed, 582 insertions(+)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
+
+--- a/drivers/phy/qualcomm/Kconfig
++++ b/drivers/phy/qualcomm/Kconfig
+@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
+ select GENERIC_PHY
+ help
+ Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
++
++config PHY_QCOM_IPQ806X_USB
++ tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
++ depends on HAS_IOMEM
++ depends on OF && (ARCH_QCOM || COMPILE_TEST)
++ select GENERIC_PHY
++ help
++ This option enables support for the Synopsis PHYs present inside the
++ Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
++ both HS and SS PHY controllers.
+--- a/drivers/phy/qualcomm/Makefile
++++ b/drivers/phy/qualcomm/Makefile
+@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
+ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
+ obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
+ obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
++obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
+@@ -0,0 +1,571 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++
++/* USB QSCRATCH Hardware registers */
++#define QSCRATCH_GENERAL_CFG (0x08)
++#define HSUSB_PHY_CTRL_REG (0x10)
++
++/* PHY_CTRL_REG */
++#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
++#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
++#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
++#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
++#define HSUSB_CTRL_USE_CLKCORE BIT(18)
++#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
++#define HSUSB_CTRL_COMMONONN BIT(11)
++#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
++#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
++#define HSUSB_CTRL_CLAMP_EN BIT(7)
++#define HSUSB_CTRL_RETENABLEN BIT(1)
++#define HSUSB_CTRL_POR BIT(0)
++
++/* QSCRATCH_GENERAL_CFG */
++#define HSUSB_GCFG_XHCI_REV BIT(2)
++
++/* USB QSCRATCH Hardware registers */
++#define SSUSB_PHY_CTRL_REG (0x00)
++#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
++#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
++#define CR_PROTOCOL_DATA_IN_REG (0x0c)
++#define CR_PROTOCOL_DATA_OUT_REG (0x10)
++#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
++#define CR_PROTOCOL_CAP_DATA_REG (0x18)
++#define CR_PROTOCOL_READ_REG (0x1c)
++#define CR_PROTOCOL_WRITE_REG (0x20)
++
++/* PHY_CTRL_REG */
++#define SSUSB_CTRL_REF_USE_PAD BIT(28)
++#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
++#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
++#define SSUSB_CTRL_SS_PHY_EN BIT(8)
++#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
++
++/* SSPHY control registers - Does this need 0x30? */
++#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
++#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
++
++/* SSPHY SoC version specific values */
++#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
++/* Override value for transmit preemphasis */
++#define SSPHY_TX_DEEMPH_3_5DB 23
++/* Override value for mpll */
++#define SSPHY_MPLL_VALUE 0
++
++/* QSCRATCH PHY_PARAM_CTRL1 fields */
++#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
++#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
++#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
++#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
++
++#define PHY_PARAM_CTRL1_MASK \
++ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
++ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
++ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
++ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
++
++#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
++ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
++#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
++ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
++#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
++ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
++#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
++ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
++
++/* RX OVRD IN HI bits */
++#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
++#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
++#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
++#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
++#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
++#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
++#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
++#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
++#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
++#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
++#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
++
++/* TX OVRD DRV LO register bits */
++#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
++#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
++#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
++#define TX_OVRD_DRV_LO_EN BIT(14)
++
++/* MPLL bits */
++#define SSPHY_MPLL_MASK GENMASK(8, 5)
++#define SSPHY_MPLL(x) ((x) << 5)
++
++/* SS CAP register bits */
++#define SS_CR_CAP_ADDR_REG BIT(0)
++#define SS_CR_CAP_DATA_REG BIT(0)
++#define SS_CR_READ_REG BIT(0)
++#define SS_CR_WRITE_REG BIT(0)
++
++struct usb_phy {
++ void __iomem *base;
++ struct device *dev;
++ struct clk *xo_clk;
++ struct clk *ref_clk;
++ u32 rx_eq;
++ u32 tx_deamp_3_5db;
++ u32 mpll;
++};
++
++struct phy_drvdata {
++ struct phy_ops ops;
++ u32 clk_rate;
++};
++
++/**
++ * Write register and read back masked value to confirm it is written
++ *
++ * @base - QCOM DWC3 PHY base virtual address.
++ * @offset - register offset.
++ * @mask - register bitmask specifying what should be updated
++ * @val - value to write.
++ */
++static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
++ u32 offset,
++ const u32 mask, u32 val)
++{
++ u32 write_val, tmp = readl(phy_dwc3->base + offset);
++
++ tmp &= ~mask; /* retain other bits */
++ write_val = tmp | val;
++
++ writel(write_val, phy_dwc3->base + offset);
++
++ /* Read back to see if val was written */
++ tmp = readl(phy_dwc3->base + offset);
++ tmp &= mask; /* clear other bits */
++
++ if (tmp != val)
++ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
++}
++
++static int wait_for_latch(void __iomem *addr)
++{
++ u32 retry = 10;
++
++ while (true) {
++ if (!readl(addr))
++ break;
++
++ if (--retry == 0)
++ return -ETIMEDOUT;
++
++ usleep_range(10, 20);
++ }
++
++ return 0;
++}
++
++/**
++ * Write SSPHY register
++ *
++ * @base - QCOM DWC3 PHY base virtual address.
++ * @addr - SSPHY address to write.
++ * @val - value to write.
++ */
++static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
++ u32 addr, u32 val)
++{
++ int ret;
++
++ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
++ writel(SS_CR_CAP_ADDR_REG,
++ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
++ if (ret)
++ goto err_wait;
++
++ writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
++ writel(SS_CR_CAP_DATA_REG,
++ phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
++ if (ret)
++ goto err_wait;
++
++ writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
++
++err_wait:
++ if (ret)
++ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
++ return ret;
++}
++
++/**
++ * Read SSPHY register.
++ *
++ * @base - QCOM DWC3 PHY base virtual address.
++ * @addr - SSPHY address to read.
++ */
++static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
++ u32 addr, u32 *val)
++{
++ int ret;
++
++ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
++ writel(SS_CR_CAP_ADDR_REG,
++ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
++ if (ret)
++ goto err_wait;
++
++ /*
++ * Due to hardware bug, first read of SSPHY register might be
++ * incorrect. Hence as workaround, SW should perform SSPHY register
++ * read twice, but use only second read and ignore first read.
++ */
++ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
++ if (ret)
++ goto err_wait;
++
++ /* throwaway read */
++ readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
++
++ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
++
++ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
++ if (ret)
++ goto err_wait;
++
++ *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
++
++err_wait:
++ return ret;
++}
++
++static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
++{
++ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
++ int ret;
++ u32 val;
++
++ ret = clk_prepare_enable(phy_dwc3->xo_clk);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(phy_dwc3->ref_clk);
++ if (ret) {
++ clk_disable_unprepare(phy_dwc3->xo_clk);
++ return ret;
++ }
++
++ /*
++ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
++ * enable clamping, and disable RETENTION (power-on default is ENABLED)
++ */
++ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
++ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
++ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
++ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
++ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
++
++ /* use core clock if external reference is not present */
++ if (!phy_dwc3->xo_clk)
++ val |= HSUSB_CTRL_USE_CLKCORE;
++
++ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
++ usleep_range(2000, 2200);
++
++ /* Disable (bypass) VBUS and ID filters */
++ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
++
++ return 0;
++}
++
++static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
++{
++ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
++
++ clk_disable_unprepare(phy_dwc3->ref_clk);
++ clk_disable_unprepare(phy_dwc3->xo_clk);
++
++ return 0;
++}
++
++static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
++{
++ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
++ int ret;
++ u32 data;
++
++ ret = clk_prepare_enable(phy_dwc3->xo_clk);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(phy_dwc3->ref_clk);
++ if (ret) {
++ clk_disable_unprepare(phy_dwc3->xo_clk);
++ return ret;
++ }
++
++ /* reset phy */
++ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
++ writel(data | SSUSB_CTRL_SS_PHY_RESET,
++ phy_dwc3->base + SSUSB_PHY_CTRL_REG);
++ usleep_range(2000, 2200);
++ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
++
++ /* clear REF_PAD if we don't have XO clk */
++ if (!phy_dwc3->xo_clk)
++ data &= ~SSUSB_CTRL_REF_USE_PAD;
++ else
++ data |= SSUSB_CTRL_REF_USE_PAD;
++
++ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
++
++ /* wait for ref clk to become stable, this can take up to 30ms */
++ msleep(30);
++
++ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
++ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
++
++ /*
++ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
++ * in HS mode instead of SS mode. Workaround it by asserting
++ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
++ */
++ ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
++ if (ret)
++ goto err_phy_trans;
++
++ data |= (1 << 7);
++ ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
++ if (ret)
++ goto err_phy_trans;
++
++ ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
++ if (ret)
++ goto err_phy_trans;
++
++ data &= ~0xff0;
++ data |= 0x20;
++ ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
++ if (ret)
++ goto err_phy_trans;
++
++ /*
++ * Fix RX Equalization setting as follows
++ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
++ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
++ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
++ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
++ */
++ ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
++ if (ret)
++ goto err_phy_trans;
++
++ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
++ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
++ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
++ data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
++ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
++ ret = usb_ss_write_phycreg(phy_dwc3,
++ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
++ if (ret)
++ goto err_phy_trans;
++
++ /*
++ * Set EQ and TX launch amplitudes as follows
++ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
++ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
++ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
++ */
++ ret = usb_ss_read_phycreg(phy_dwc3,
++ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
++ if (ret)
++ goto err_phy_trans;
++
++ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
++ data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
++ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
++ data |= 0x6E;
++ data |= TX_OVRD_DRV_LO_EN;
++ ret = usb_ss_write_phycreg(phy_dwc3,
++ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
++ if (ret)
++ goto err_phy_trans;
++
++ data = 0;
++ data &= ~SSPHY_MPLL_MASK;
++ data |= SSPHY_MPLL(phy_dwc3->mpll);
++ usb_ss_write_phycreg(phy_dwc3, 0x30, data);
++
++ /*
++ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
++ * TX_FULL_SWING [26:20] amplitude to 110
++ * TX_DEEMPH_6DB [19:14] to 32
++ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
++ * LOS_BIAS [7:3] to 9
++ */
++ data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
++
++ data &= ~PHY_PARAM_CTRL1_MASK;
++
++ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
++ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
++ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
++ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
++
++ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
++ PHY_PARAM_CTRL1_MASK, data);
++
++err_phy_trans:
++ return ret;
++}
++
++static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
++{
++ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
++
++ /* Sequence to put SSPHY in low power state:
++ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
++ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
++ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
++ */
++ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
++ SSUSB_CTRL_SS_PHY_EN, 0x0);
++ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
++ SSUSB_CTRL_REF_USE_PAD, 0x0);
++ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
++ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
++
++ clk_disable_unprepare(phy_dwc3->ref_clk);
++ clk_disable_unprepare(phy_dwc3->xo_clk);
++
++ return 0;
++}
++
++static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
++ .ops = {
++ .init = qcom_ipq806x_usb_hs_phy_init,
++ .exit = qcom_ipq806x_usb_hs_phy_exit,
++ .owner = THIS_MODULE,
++ },
++ .clk_rate = 60000000,
++};
++
++static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
++ .ops = {
++ .init = qcom_ipq806x_usb_ss_phy_init,
++ .exit = qcom_ipq806x_usb_ss_phy_exit,
++ .owner = THIS_MODULE,
++ },
++ .clk_rate = 125000000,
++};
++
++static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
++ { .compatible = "qcom,ipq806x-usb-phy-hs",
++ .data = &qcom_ipq806x_usb_hs_drvdata },
++ { .compatible = "qcom,ipq806x-usb-phy-ss",
++ .data = &qcom_ipq806x_usb_ss_drvdata },
++ { /* Sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
++
++static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ resource_size_t size;
++ struct phy *generic_phy;
++ struct usb_phy *phy_dwc3;
++ const struct phy_drvdata *data;
++ struct phy_provider *phy_provider;
++
++ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
++ if (!phy_dwc3)
++ return -ENOMEM;
++
++ data = of_device_get_match_data(&pdev->dev);
++
++ phy_dwc3->dev = &pdev->dev;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -EINVAL;
++ size = resource_size(res);
++ phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
++
++ if (IS_ERR(phy_dwc3->base)) {
++ dev_err(phy_dwc3->dev, "failed to map reg\n");
++ return PTR_ERR(phy_dwc3->base);
++ }
++
++ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
++ if (IS_ERR(phy_dwc3->ref_clk)) {
++ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
++ return PTR_ERR(phy_dwc3->ref_clk);
++ }
++
++ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
++
++ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
++ if (IS_ERR(phy_dwc3->xo_clk)) {
++ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
++ phy_dwc3->xo_clk = NULL;
++ }
++
++ /* Parse device node to probe HSIO settings */
++ if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
++ &phy_dwc3->rx_eq))
++ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
++
++ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
++ &phy_dwc3->tx_deamp_3_5db))
++ phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
++
++ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
++ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
++
++ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
++
++ if (IS_ERR(generic_phy))
++ return PTR_ERR(generic_phy);
++
++ phy_set_drvdata(generic_phy, phy_dwc3);
++ platform_set_drvdata(pdev, phy_dwc3);
++
++ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
++ of_phy_simple_xlate);
++
++ if (IS_ERR(phy_provider))
++ return PTR_ERR(phy_provider);
++
++ return 0;
++}
++
++static struct platform_driver qcom_ipq806x_usb_phy_driver = {
++ .probe = qcom_ipq806x_usb_phy_probe,
++ .driver = {
++ .name = "qcom-ipq806x-usb-phy",
++ .owner = THIS_MODULE,
++ .of_match_table = qcom_ipq806x_usb_phy_table,
++ },
++};
++
++module_platform_driver(qcom_ipq806x_usb_phy_driver);
++
++MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
++MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
--- /dev/null
+From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Tue, 21 Jul 2020 16:06:13 +0100
+Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property
+ read fails
+
+Currently when reading of the device property for "qcom,tx-deamp_3_5db"
+fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
+looks like a copy-n-paste error and in fact should be assigning the
+default instead to phy_dwc3->tx_deamp_3_5db
+
+Addresses-Coverity: ("Copy-paste error")
+Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
+@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st
+
+ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
+ &phy_dwc3->tx_deamp_3_5db))
+- phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
++ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
+
+ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
--- /dev/null
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
+ obj-$(CONFIG_QCOM_SMSM) += smsm.o
+ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
+ obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
+ obj-$(CONFIG_QCOM_APR) += apr.o
+ obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
+ obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -183,6 +183,13 @@ config QCOM_SOCINFO
+ Say yes here to support the Qualcomm socinfo driver, providing
+ information about the SoC to user space.
+
++config QCOM_TCSR
++ tristate "QCOM Top Control and Status Registers"
++ depends on ARCH_QCOM
++ help
++ Say y here to enable TCSR support. The TCSR provides control
++ functions for various peripherals.
++
+ config QCOM_WCNSS_CTRL
+ tristate "Qualcomm WCNSS control driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+--- /dev/null
++++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2014, The Linux foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License rev 2 and
++ * only rev 2 as published by the free Software foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define TCSR_USB_PORT_SEL 0xb0
++
++static int tcsr_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ const struct device_node *node = pdev->dev.of_node;
++ void __iomem *base;
++ u32 val;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
++ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
++ writel(val, base + TCSR_USB_PORT_SEL);
++ }
++
++ return 0;
++}
++
++static const struct of_device_id tcsr_dt_match[] = {
++ { .compatible = "qcom,tcsr", },
++ { },
++};
++
++MODULE_DEVICE_TABLE(of, tcsr_dt_match);
++
++static struct platform_driver tcsr_driver = {
++ .driver = {
++ .name = "tcsr",
++ .owner = THIS_MODULE,
++ .of_match_table = tcsr_dt_match,
++ },
++ .probe = tcsr_probe,
++};
++
++module_platform_driver(tcsr_driver);
++
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_DESCRIPTION("QCOM TCSR driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,23 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_TCSR_H
++#define __DT_BINDINGS_QCOM_TCSR_H
++
++#define TCSR_USB_SELECT_USB3_P0 0x1
++#define TCSR_USB_SELECT_USB3_P1 0x2
++#define TCSR_USB_SELECT_USB3_DUAL 0x3
++
++/* TCSR A/B REG */
++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
++
++#endif
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -865,6 +865,41 @@
+ reg = <0x12100000 0x10000>;
+ };
+
++ gsbi1: gsbi@12440000 {
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <1>;
++ reg = <0x12440000 0x100>;
++ clocks = <&gcc GSBI1_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ status = "disabled";
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi1_serial: serial@12450000 {
++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++ reg = <0x12450000 0x100>,
++ <0x12400000 0x03>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++ };
++
++ gsbi1_i2c: i2c@12460000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x12460000 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
+ gsbi2: gsbi@12480000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
--- /dev/null
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1840,6 +1840,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
+
+ endchoice
+
++config CMDLINE_OVERRIDE
++ bool "Use alternative cmdline from device tree"
++ help
++ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++ be used, this is not a good option for kernels that are shared across
++ devices. This setting enables using "chosen/cmdline-override" as the
++ cmdline if it exists in the device tree.
++
+ config CMDLINE
+ string "Default kernel command string"
+ default ""
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1060,6 +1060,17 @@ int __init early_init_dt_scan_chosen(uns
+ if (p != NULL && l > 0)
+ strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
+
++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++ * device tree option of chosen/bootargs-override. This is
++ * helpful on boards where u-boot sets bootargs, and is unable
++ * to be modified.
++ */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++ if (p != NULL && l > 0)
++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ /*
+ * CONFIG_CMDLINE is meant to be a default in case nothing else
+ * managed to set the command line, unless CONFIG_CMDLINE_FORCE
--- /dev/null
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1059,6 +1059,9 @@ int __init early_init_dt_scan_chosen(uns
+ p = of_get_flat_dt_prop(node, "bootargs", &l);
+ if (p != NULL && l > 0)
+ strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
++ p = of_get_flat_dt_prop(node, "bootargs-append", &l);
++ if (p != NULL && l > 0)
++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+
+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
+ * device tree option of chosen/bootargs-override. This is
projects / openwrt / staging / zorun.git / commitdiff